2 * Copyright (C) 2014 ARM Limited
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/init.h>
11 #include <linux/list.h>
12 #include <linux/perf_event.h>
13 #include <linux/sched.h>
14 #include <linux/slab.h>
15 #include <linux/sysctl.h>
17 #include <asm/cpufeature.h>
19 #include <asm/sysreg.h>
20 #include <asm/system_misc.h>
21 #include <asm/traps.h>
22 #include <asm/kprobes.h>
23 #include <linux/uaccess.h>
24 #include <asm/cpufeature.h>
26 #define CREATE_TRACE_POINTS
27 #include "trace-events-emulation.h"
30 * The runtime support for deprecated instruction support can be in one of
31 * following three states -
34 * 1 = emulate (software emulation)
35 * 2 = hw (supported in hardware)
37 enum insn_emulation_mode {
43 enum legacy_insn_status {
48 struct insn_emulation_ops {
50 enum legacy_insn_status status;
51 struct undef_hook *hooks;
52 int (*set_hw_mode)(bool enable);
55 struct insn_emulation {
56 struct list_head node;
57 struct insn_emulation_ops *ops;
63 static LIST_HEAD(insn_emulation);
64 static int nr_insn_emulated __initdata;
65 static DEFINE_RAW_SPINLOCK(insn_emulation_lock);
66 static DEFINE_MUTEX(insn_emulation_mutex);
68 static void register_emulation_hooks(struct insn_emulation_ops *ops)
70 struct undef_hook *hook;
74 for (hook = ops->hooks; hook->instr_mask; hook++)
75 register_undef_hook(hook);
77 pr_notice("Registered %s emulation handler\n", ops->name);
80 static void remove_emulation_hooks(struct insn_emulation_ops *ops)
82 struct undef_hook *hook;
86 for (hook = ops->hooks; hook->instr_mask; hook++)
87 unregister_undef_hook(hook);
89 pr_notice("Removed %s emulation handler\n", ops->name);
92 static void enable_insn_hw_mode(void *data)
94 struct insn_emulation *insn = (struct insn_emulation *)data;
95 if (insn->ops->set_hw_mode)
96 insn->ops->set_hw_mode(true);
99 static void disable_insn_hw_mode(void *data)
101 struct insn_emulation *insn = (struct insn_emulation *)data;
102 if (insn->ops->set_hw_mode)
103 insn->ops->set_hw_mode(false);
106 /* Run set_hw_mode(mode) on all active CPUs */
107 static int run_all_cpu_set_hw_mode(struct insn_emulation *insn, bool enable)
109 if (!insn->ops->set_hw_mode)
112 on_each_cpu(enable_insn_hw_mode, (void *)insn, true);
114 on_each_cpu(disable_insn_hw_mode, (void *)insn, true);
119 * Run set_hw_mode for all insns on a starting CPU.
121 * 0 - If all the hooks ran successfully.
122 * -EINVAL - At least one hook is not supported by the CPU.
124 static int run_all_insn_set_hw_mode(unsigned int cpu)
128 struct insn_emulation *insn;
130 raw_spin_lock_irqsave(&insn_emulation_lock, flags);
131 list_for_each_entry(insn, &insn_emulation, node) {
132 bool enable = (insn->current_mode == INSN_HW);
133 if (insn->ops->set_hw_mode && insn->ops->set_hw_mode(enable)) {
134 pr_warn("CPU[%u] cannot support the emulation of %s",
135 cpu, insn->ops->name);
139 raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
143 static int update_insn_emulation_mode(struct insn_emulation *insn,
144 enum insn_emulation_mode prev)
149 case INSN_UNDEF: /* Nothing to be done */
152 remove_emulation_hooks(insn->ops);
155 if (!run_all_cpu_set_hw_mode(insn, false))
156 pr_notice("Disabled %s support\n", insn->ops->name);
160 switch (insn->current_mode) {
164 register_emulation_hooks(insn->ops);
167 ret = run_all_cpu_set_hw_mode(insn, true);
169 pr_notice("Enabled %s support\n", insn->ops->name);
176 static void __init register_insn_emulation(struct insn_emulation_ops *ops)
179 struct insn_emulation *insn;
181 insn = kzalloc(sizeof(*insn), GFP_KERNEL);
183 insn->min = INSN_UNDEF;
185 switch (ops->status) {
186 case INSN_DEPRECATED:
187 insn->current_mode = INSN_EMULATE;
188 /* Disable the HW mode if it was turned on at early boot time */
189 run_all_cpu_set_hw_mode(insn, false);
193 insn->current_mode = INSN_UNDEF;
194 insn->max = INSN_EMULATE;
198 raw_spin_lock_irqsave(&insn_emulation_lock, flags);
199 list_add(&insn->node, &insn_emulation);
201 raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
203 /* Register any handlers if required */
204 update_insn_emulation_mode(insn, INSN_UNDEF);
207 static int emulation_proc_handler(struct ctl_table *table, int write,
208 void __user *buffer, size_t *lenp,
212 struct insn_emulation *insn = container_of(table->data, struct insn_emulation, current_mode);
213 enum insn_emulation_mode prev_mode = insn->current_mode;
215 mutex_lock(&insn_emulation_mutex);
216 ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
218 if (ret || !write || prev_mode == insn->current_mode)
221 ret = update_insn_emulation_mode(insn, prev_mode);
223 /* Mode change failed, revert to previous mode. */
224 insn->current_mode = prev_mode;
225 update_insn_emulation_mode(insn, INSN_UNDEF);
228 mutex_unlock(&insn_emulation_mutex);
232 static struct ctl_table ctl_abi[] = {
240 static void __init register_insn_emulation_sysctl(struct ctl_table *table)
244 struct insn_emulation *insn;
245 struct ctl_table *insns_sysctl, *sysctl;
247 insns_sysctl = kzalloc(sizeof(*sysctl) * (nr_insn_emulated + 1),
250 raw_spin_lock_irqsave(&insn_emulation_lock, flags);
251 list_for_each_entry(insn, &insn_emulation, node) {
252 sysctl = &insns_sysctl[i];
255 sysctl->maxlen = sizeof(int);
257 sysctl->procname = insn->ops->name;
258 sysctl->data = &insn->current_mode;
259 sysctl->extra1 = &insn->min;
260 sysctl->extra2 = &insn->max;
261 sysctl->proc_handler = emulation_proc_handler;
264 raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
266 table->child = insns_sysctl;
267 register_sysctl_table(table);
271 * Implement emulation of the SWP/SWPB instructions using load-exclusive and
274 * Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>]
275 * Where: Rt = destination
281 * Error-checking SWP macros implemented using ldxr{b}/stxr{b}
284 /* Arbitrary constant to ensure forward-progress of the LL/SC loop */
285 #define __SWP_LL_SC_LOOPS 4
287 #define __user_swpX_asm(data, addr, res, temp, temp2, B) \
290 __asm__ __volatile__( \
292 "0: ldxr"B" %w2, [%4]\n" \
293 "1: stxr"B" %w0, %w1, [%4]\n" \
295 " sub %w3, %w3, #1\n" \
302 " .pushsection .fixup,\"ax\"\n" \
304 "4: mov %w0, %w6\n" \
307 _ASM_EXTABLE(0b, 4b) \
308 _ASM_EXTABLE(1b, 4b) \
309 : "=&r" (res), "+r" (data), "=&r" (temp), "=&r" (temp2) \
310 : "r" ((unsigned long)addr), "i" (-EAGAIN), \
312 "i" (__SWP_LL_SC_LOOPS) \
317 #define __user_swp_asm(data, addr, res, temp, temp2) \
318 __user_swpX_asm(data, addr, res, temp, temp2, "")
319 #define __user_swpb_asm(data, addr, res, temp, temp2) \
320 __user_swpX_asm(data, addr, res, temp, temp2, "b")
323 * Bit 22 of the instruction encoding distinguishes between
324 * the SWP and SWPB variants (bit set means SWPB).
326 #define TYPE_SWPB (1 << 22)
328 static int emulate_swpX(unsigned int address, unsigned int *data,
331 unsigned int res = 0;
333 if ((type != TYPE_SWPB) && (address & 0x3)) {
334 /* SWP to unaligned address not permitted */
335 pr_debug("SWP instruction on unaligned pointer!\n");
340 unsigned long temp, temp2;
342 if (type == TYPE_SWPB)
343 __user_swpb_asm(*data, address, res, temp, temp2);
345 __user_swp_asm(*data, address, res, temp, temp2);
347 if (likely(res != -EAGAIN) || signal_pending(current))
356 #define ARM_OPCODE_CONDTEST_FAIL 0
357 #define ARM_OPCODE_CONDTEST_PASS 1
358 #define ARM_OPCODE_CONDTEST_UNCOND 2
360 #define ARM_OPCODE_CONDITION_UNCOND 0xf
362 static unsigned int __kprobes aarch32_check_condition(u32 opcode, u32 psr)
364 u32 cc_bits = opcode >> 28;
366 if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) {
367 if ((*aarch32_opcode_cond_checks[cc_bits])(psr))
368 return ARM_OPCODE_CONDTEST_PASS;
370 return ARM_OPCODE_CONDTEST_FAIL;
372 return ARM_OPCODE_CONDTEST_UNCOND;
376 * swp_handler logs the id of calling process, dissects the instruction, sanity
377 * checks the memory location, calls emulate_swpX for the actual operation and
378 * deals with fixup/error handling before returning
380 static int swp_handler(struct pt_regs *regs, u32 instr)
382 u32 destreg, data, type, address = 0;
383 int rn, rt2, res = 0;
385 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
387 type = instr & TYPE_SWPB;
389 switch (aarch32_check_condition(instr, regs->pstate)) {
390 case ARM_OPCODE_CONDTEST_PASS:
392 case ARM_OPCODE_CONDTEST_FAIL:
393 /* Condition failed - return to next instruction */
395 case ARM_OPCODE_CONDTEST_UNCOND:
396 /* If unconditional encoding - not a SWP, undef */
402 rn = aarch32_insn_extract_reg_num(instr, A32_RN_OFFSET);
403 rt2 = aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET);
405 address = (u32)regs->user_regs.regs[rn];
406 data = (u32)regs->user_regs.regs[rt2];
407 destreg = aarch32_insn_extract_reg_num(instr, A32_RT_OFFSET);
409 pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n",
410 rn, address, destreg,
411 aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET), data);
413 /* Check access in reasonable access range for both SWP and SWPB */
414 if (!access_ok(VERIFY_WRITE, (address & ~3), 4)) {
415 pr_debug("SWP{B} emulation: access to 0x%08x not allowed!\n",
420 res = emulate_swpX(address, &data, type);
424 regs->user_regs.regs[destreg] = data;
427 if (type == TYPE_SWPB)
428 trace_instruction_emulation("swpb", regs->pc);
430 trace_instruction_emulation("swp", regs->pc);
432 pr_warn_ratelimited("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n",
433 current->comm, (unsigned long)current->pid, regs->pc);
435 arm64_skip_faulting_instruction(regs, 4);
439 pr_debug("SWP{B} emulation: access caused memory abort!\n");
440 arm64_notify_segfault(regs, address);
446 * Only emulate SWP/SWPB executed in ARM state/User mode.
447 * The kernel must be SWP free and SWP{B} does not exist in Thumb.
449 static struct undef_hook swp_hooks[] = {
451 .instr_mask = 0x0fb00ff0,
452 .instr_val = 0x01000090,
453 .pstate_mask = COMPAT_PSR_MODE_MASK,
454 .pstate_val = COMPAT_PSR_MODE_USR,
460 static struct insn_emulation_ops swp_ops = {
462 .status = INSN_OBSOLETE,
467 static int cp15barrier_handler(struct pt_regs *regs, u32 instr)
469 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
471 switch (aarch32_check_condition(instr, regs->pstate)) {
472 case ARM_OPCODE_CONDTEST_PASS:
474 case ARM_OPCODE_CONDTEST_FAIL:
475 /* Condition failed - return to next instruction */
477 case ARM_OPCODE_CONDTEST_UNCOND:
478 /* If unconditional encoding - not a barrier instruction */
484 switch (aarch32_insn_mcr_extract_crm(instr)) {
487 * dmb - mcr p15, 0, Rt, c7, c10, 5
488 * dsb - mcr p15, 0, Rt, c7, c10, 4
490 if (aarch32_insn_mcr_extract_opc2(instr) == 5) {
492 trace_instruction_emulation(
493 "mcr p15, 0, Rt, c7, c10, 5 ; dmb", regs->pc);
496 trace_instruction_emulation(
497 "mcr p15, 0, Rt, c7, c10, 4 ; dsb", regs->pc);
502 * isb - mcr p15, 0, Rt, c7, c5, 4
504 * Taking an exception or returning from one acts as an
505 * instruction barrier. So no explicit barrier needed here.
507 trace_instruction_emulation(
508 "mcr p15, 0, Rt, c7, c5, 4 ; isb", regs->pc);
513 pr_warn_ratelimited("\"%s\" (%ld) uses deprecated CP15 Barrier instruction at 0x%llx\n",
514 current->comm, (unsigned long)current->pid, regs->pc);
516 arm64_skip_faulting_instruction(regs, 4);
520 static int cp15_barrier_set_hw_mode(bool enable)
523 config_sctlr_el1(0, SCTLR_EL1_CP15BEN);
525 config_sctlr_el1(SCTLR_EL1_CP15BEN, 0);
529 static struct undef_hook cp15_barrier_hooks[] = {
531 .instr_mask = 0x0fff0fdf,
532 .instr_val = 0x0e070f9a,
533 .pstate_mask = COMPAT_PSR_MODE_MASK,
534 .pstate_val = COMPAT_PSR_MODE_USR,
535 .fn = cp15barrier_handler,
538 .instr_mask = 0x0fff0fff,
539 .instr_val = 0x0e070f95,
540 .pstate_mask = COMPAT_PSR_MODE_MASK,
541 .pstate_val = COMPAT_PSR_MODE_USR,
542 .fn = cp15barrier_handler,
547 static struct insn_emulation_ops cp15_barrier_ops = {
548 .name = "cp15_barrier",
549 .status = INSN_DEPRECATED,
550 .hooks = cp15_barrier_hooks,
551 .set_hw_mode = cp15_barrier_set_hw_mode,
554 static int setend_set_hw_mode(bool enable)
556 if (!cpu_supports_mixed_endian_el0())
560 config_sctlr_el1(SCTLR_EL1_SED, 0);
562 config_sctlr_el1(0, SCTLR_EL1_SED);
566 static int compat_setend_handler(struct pt_regs *regs, u32 big_endian)
570 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
574 regs->pstate |= COMPAT_PSR_E_BIT;
577 regs->pstate &= ~COMPAT_PSR_E_BIT;
580 trace_instruction_emulation(insn, regs->pc);
581 pr_warn_ratelimited("\"%s\" (%ld) uses deprecated setend instruction at 0x%llx\n",
582 current->comm, (unsigned long)current->pid, regs->pc);
587 static int a32_setend_handler(struct pt_regs *regs, u32 instr)
589 int rc = compat_setend_handler(regs, (instr >> 9) & 1);
590 arm64_skip_faulting_instruction(regs, 4);
594 static int t16_setend_handler(struct pt_regs *regs, u32 instr)
596 int rc = compat_setend_handler(regs, (instr >> 3) & 1);
597 arm64_skip_faulting_instruction(regs, 2);
601 static struct undef_hook setend_hooks[] = {
603 .instr_mask = 0xfffffdff,
604 .instr_val = 0xf1010000,
605 .pstate_mask = COMPAT_PSR_MODE_MASK,
606 .pstate_val = COMPAT_PSR_MODE_USR,
607 .fn = a32_setend_handler,
611 .instr_mask = 0xfffffff7,
612 .instr_val = 0x0000b650,
613 .pstate_mask = (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_MASK),
614 .pstate_val = (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_USR),
615 .fn = t16_setend_handler,
620 static struct insn_emulation_ops setend_ops = {
622 .status = INSN_DEPRECATED,
623 .hooks = setend_hooks,
624 .set_hw_mode = setend_set_hw_mode,
628 * Invoked as late_initcall, since not needed before init spawned.
630 static int __init armv8_deprecated_init(void)
632 if (IS_ENABLED(CONFIG_SWP_EMULATION))
633 register_insn_emulation(&swp_ops);
635 if (IS_ENABLED(CONFIG_CP15_BARRIER_EMULATION))
636 register_insn_emulation(&cp15_barrier_ops);
638 if (IS_ENABLED(CONFIG_SETEND_EMULATION)) {
639 if(system_supports_mixed_endian_el0())
640 register_insn_emulation(&setend_ops);
642 pr_info("setend instruction emulation is not supported on this system\n");
645 cpuhp_setup_state_nocalls(CPUHP_AP_ARM64_ISNDEP_STARTING,
646 "arm64/isndep:starting",
647 run_all_insn_set_hw_mode, NULL);
648 register_insn_emulation_sysctl(ctl_abi);
653 core_initcall(armv8_deprecated_init);