arch/arm64/kernel/armv8_deprecated.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  Copyright (C) 2014 ARM Limited
   4  */
   5
   6 #include <linux/cpu.h>
   7 #include <linux/init.h>
   8 #include <linux/list.h>
   9 #include <linux/perf_event.h>
  10 #include <linux/sched.h>
  11 #include <linux/slab.h>
  12 #include <linux/sysctl.h>
  13 #include <linux/uaccess.h>
  14
  15 #include <asm/cpufeature.h>
  16 #include <asm/insn.h>
  17 #include <asm/sysreg.h>
  18 #include <asm/system_misc.h>
  19 #include <asm/traps.h>
  20 #include <asm/kprobes.h>
  21
  22 #define CREATE_TRACE_POINTS
  23 #include "trace-events-emulation.h"
  24
  25 /*
  26  * The runtime support for deprecated instruction support can be in one of
  27  * following three states -
  28  *
  29  * 0 = undef
  30  * 1 = emulate (software emulation)
  31  * 2 = hw (supported in hardware)
  32  */
  33 enum insn_emulation_mode {
  34         INSN_UNDEF,
  35         INSN_EMULATE,
  36         INSN_HW,
  37 };
  38
  39 enum legacy_insn_status {
  40         INSN_DEPRECATED,
  41         INSN_OBSOLETE,
  42 };
  43
  44 struct insn_emulation_ops {
  45         const char              *name;
  46         enum legacy_insn_status status;
  47         struct undef_hook       *hooks;
  48         int                     (*set_hw_mode)(bool enable);
  49 };
  50
  51 struct insn_emulation {
  52         struct list_head node;
  53         struct insn_emulation_ops *ops;
  54         int current_mode;
  55         int min;
  56         int max;
  57 };
  58
  59 static LIST_HEAD(insn_emulation);
  60 static int nr_insn_emulated __initdata;
  61 static DEFINE_RAW_SPINLOCK(insn_emulation_lock);
  62 static DEFINE_MUTEX(insn_emulation_mutex);
  63
  64 static void register_emulation_hooks(struct insn_emulation_ops *ops)
  65 {
  66         struct undef_hook *hook;
  67
  68         BUG_ON(!ops->hooks);
  69
  70         for (hook = ops->hooks; hook->instr_mask; hook++)
  71                 register_undef_hook(hook);
  72
  73         pr_notice("Registered %s emulation handler\n", ops->name);
  74 }
  75
  76 static void remove_emulation_hooks(struct insn_emulation_ops *ops)
  77 {
  78         struct undef_hook *hook;
  79
  80         BUG_ON(!ops->hooks);
  81
  82         for (hook = ops->hooks; hook->instr_mask; hook++)
  83                 unregister_undef_hook(hook);
  84
  85         pr_notice("Removed %s emulation handler\n", ops->name);
  86 }
  87
  88 static void enable_insn_hw_mode(void *data)
  89 {
  90         struct insn_emulation *insn = (struct insn_emulation *)data;
  91         if (insn->ops->set_hw_mode)
  92                 insn->ops->set_hw_mode(true);
  93 }
  94
  95 static void disable_insn_hw_mode(void *data)
  96 {
  97         struct insn_emulation *insn = (struct insn_emulation *)data;
  98         if (insn->ops->set_hw_mode)
  99                 insn->ops->set_hw_mode(false);
 100 }
 101
 102 /* Run set_hw_mode(mode) on all active CPUs */
 103 static int run_all_cpu_set_hw_mode(struct insn_emulation *insn, bool enable)
 104 {
 105         if (!insn->ops->set_hw_mode)
 106                 return -EINVAL;
 107         if (enable)
 108                 on_each_cpu(enable_insn_hw_mode, (void *)insn, true);
 109         else
 110                 on_each_cpu(disable_insn_hw_mode, (void *)insn, true);
 111         return 0;
 112 }
 113
 114 /*
 115  * Run set_hw_mode for all insns on a starting CPU.
 116  * Returns:
 117  *  0           - If all the hooks ran successfully.
 118  * -EINVAL      - At least one hook is not supported by the CPU.
 119  */
 120 static int run_all_insn_set_hw_mode(unsigned int cpu)
 121 {
 122         int rc = 0;
 123         unsigned long flags;
 124         struct insn_emulation *insn;
 125
 126         raw_spin_lock_irqsave(&insn_emulation_lock, flags);
 127         list_for_each_entry(insn, &insn_emulation, node) {
 128                 bool enable = (insn->current_mode == INSN_HW);
 129                 if (insn->ops->set_hw_mode && insn->ops->set_hw_mode(enable)) {
 130                         pr_warn("CPU[%u] cannot support the emulation of %s",
 131                                 cpu, insn->ops->name);
 132                         rc = -EINVAL;
 133                 }
 134         }
 135         raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
 136         return rc;
 137 }
 138
 139 static int update_insn_emulation_mode(struct insn_emulation *insn,
 140                                        enum insn_emulation_mode prev)
 141 {
 142         int ret = 0;
 143
 144         switch (prev) {
 145         case INSN_UNDEF: /* Nothing to be done */
 146                 break;
 147         case INSN_EMULATE:
 148                 remove_emulation_hooks(insn->ops);
 149                 break;
 150         case INSN_HW:
 151                 if (!run_all_cpu_set_hw_mode(insn, false))
 152                         pr_notice("Disabled %s support\n", insn->ops->name);
 153                 break;
 154         }
 155
 156         switch (insn->current_mode) {
 157         case INSN_UNDEF:
 158                 break;
 159         case INSN_EMULATE:
 160                 register_emulation_hooks(insn->ops);
 161                 break;
 162         case INSN_HW:
 163                 ret = run_all_cpu_set_hw_mode(insn, true);
 164                 if (!ret)
 165                         pr_notice("Enabled %s support\n", insn->ops->name);
 166                 break;
 167         }
 168
 169         return ret;
 170 }
 171
 172 static void __init register_insn_emulation(struct insn_emulation_ops *ops)
 173 {
 174         unsigned long flags;
 175         struct insn_emulation *insn;
 176
 177         insn = kzalloc(sizeof(*insn), GFP_KERNEL);
 178         if (!insn)
 179                 return;
 180
 181         insn->ops = ops;
 182         insn->min = INSN_UNDEF;
 183
 184         switch (ops->status) {
 185         case INSN_DEPRECATED:
 186                 insn->current_mode = INSN_EMULATE;
 187                 /* Disable the HW mode if it was turned on at early boot time */
 188                 run_all_cpu_set_hw_mode(insn, false);
 189                 insn->max = INSN_HW;
 190                 break;
 191         case INSN_OBSOLETE:
 192                 insn->current_mode = INSN_UNDEF;
 193                 insn->max = INSN_EMULATE;
 194                 break;
 195         }
 196
 197         raw_spin_lock_irqsave(&insn_emulation_lock, flags);
 198         list_add(&insn->node, &insn_emulation);
 199         nr_insn_emulated++;
 200         raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
 201
 202         /* Register any handlers if required */
 203         update_insn_emulation_mode(insn, INSN_UNDEF);
 204 }
 205
 206 static int emulation_proc_handler(struct ctl_table *table, int write,
 207                                   void __user *buffer, size_t *lenp,
 208                                   loff_t *ppos)
 209 {
 210         int ret = 0;
 211         struct insn_emulation *insn;
 212         enum insn_emulation_mode prev_mode;
 213
 214         mutex_lock(&insn_emulation_mutex);
 215         insn = container_of(table->data, struct insn_emulation, current_mode);
 216         prev_mode = insn->current_mode;
 217         ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
 218
 219         if (ret || !write || prev_mode == insn->current_mode)
 220                 goto ret;
 221
 222         ret = update_insn_emulation_mode(insn, prev_mode);
 223         if (ret) {
 224                 /* Mode change failed, revert to previous mode. */
 225                 insn->current_mode = prev_mode;
 226                 update_insn_emulation_mode(insn, INSN_UNDEF);
 227         }
 228 ret:
 229         mutex_unlock(&insn_emulation_mutex);
 230         return ret;
 231 }
 232
 233 static void __init register_insn_emulation_sysctl(void)
 234 {
 235         unsigned long flags;
 236         int i = 0;
 237         struct insn_emulation *insn;
 238         struct ctl_table *insns_sysctl, *sysctl;
 239
 240         insns_sysctl = kcalloc(nr_insn_emulated + 1, sizeof(*sysctl),
 241                                GFP_KERNEL);
 242         if (!insns_sysctl)
 243                 return;
 244
 245         raw_spin_lock_irqsave(&insn_emulation_lock, flags);
 246         list_for_each_entry(insn, &insn_emulation, node) {
 247                 sysctl = &insns_sysctl[i];
 248
 249                 sysctl->mode = 0644;
 250                 sysctl->maxlen = sizeof(int);
 251
 252                 sysctl->procname = insn->ops->name;
 253                 sysctl->data = &insn->current_mode;
 254                 sysctl->extra1 = &insn->min;
 255                 sysctl->extra2 = &insn->max;
 256                 sysctl->proc_handler = emulation_proc_handler;
 257                 i++;
 258         }
 259         raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
 260
 261         register_sysctl("abi", insns_sysctl);
 262 }
 263
 264 /*
 265  *  Implement emulation of the SWP/SWPB instructions using load-exclusive and
 266  *  store-exclusive.
 267  *
 268  *  Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>]
 269  *  Where: Rt  = destination
 270  *         Rt2 = source
 271  *         Rn  = address
 272  */
 273
 274 /*
 275  * Error-checking SWP macros implemented using ldxr{b}/stxr{b}
 276  */
 277
 278 /* Arbitrary constant to ensure forward-progress of the LL/SC loop */
 279 #define __SWP_LL_SC_LOOPS       4
 280
 281 #define __user_swpX_asm(data, addr, res, temp, temp2, B)        \
 282 do {                                                            \
 283         uaccess_enable();                                       \
 284         __asm__ __volatile__(                                   \
 285         "       mov             %w3, %w7\n"                     \
 286         "0:     ldxr"B"         %w2, [%4]\n"                    \
 287         "1:     stxr"B"         %w0, %w1, [%4]\n"               \
 288         "       cbz             %w0, 2f\n"                      \
 289         "       sub             %w3, %w3, #1\n"                 \
 290         "       cbnz            %w3, 0b\n"                      \
 291         "       mov             %w0, %w5\n"                     \
 292         "       b               3f\n"                           \
 293         "2:\n"                                                  \
 294         "       mov             %w1, %w2\n"                     \
 295         "3:\n"                                                  \
 296         "       .pushsection     .fixup,\"ax\"\n"               \
 297         "       .align          2\n"                            \
 298         "4:     mov             %w0, %w6\n"                     \
 299         "       b               3b\n"                           \
 300         "       .popsection"                                    \
 301         _ASM_EXTABLE(0b, 4b)                                    \
 302         _ASM_EXTABLE(1b, 4b)                                    \
 303         : "=&r" (res), "+r" (data), "=&r" (temp), "=&r" (temp2) \
 304         : "r" ((unsigned long)addr), "i" (-EAGAIN),             \
 305           "i" (-EFAULT),                                        \
 306           "i" (__SWP_LL_SC_LOOPS)                               \
 307         : "memory");                                            \
 308         uaccess_disable();                                      \
 309 } while (0)
 310
 311 #define __user_swp_asm(data, addr, res, temp, temp2) \
 312         __user_swpX_asm(data, addr, res, temp, temp2, "")
 313 #define __user_swpb_asm(data, addr, res, temp, temp2) \
 314         __user_swpX_asm(data, addr, res, temp, temp2, "b")
 315
 316 /*
 317  * Bit 22 of the instruction encoding distinguishes between
 318  * the SWP and SWPB variants (bit set means SWPB).
 319  */
 320 #define TYPE_SWPB (1 << 22)
 321
 322 static int emulate_swpX(unsigned int address, unsigned int *data,
 323                         unsigned int type)
 324 {
 325         unsigned int res = 0;
 326
 327         if ((type != TYPE_SWPB) && (address & 0x3)) {
 328                 /* SWP to unaligned address not permitted */
 329                 pr_debug("SWP instruction on unaligned pointer!\n");
 330                 return -EFAULT;
 331         }
 332
 333         while (1) {
 334                 unsigned long temp, temp2;
 335
 336                 if (type == TYPE_SWPB)
 337                         __user_swpb_asm(*data, address, res, temp, temp2);
 338                 else
 339                         __user_swp_asm(*data, address, res, temp, temp2);
 340
 341                 if (likely(res != -EAGAIN) || signal_pending(current))
 342                         break;
 343
 344                 cond_resched();
 345         }
 346
 347         return res;
 348 }
 349
 350 #define ARM_OPCODE_CONDTEST_FAIL   0
 351 #define ARM_OPCODE_CONDTEST_PASS   1
 352 #define ARM_OPCODE_CONDTEST_UNCOND 2
 353
 354 #define ARM_OPCODE_CONDITION_UNCOND     0xf
 355
 356 static unsigned int __kprobes aarch32_check_condition(u32 opcode, u32 psr)
 357 {
 358         u32 cc_bits  = opcode >> 28;
 359
 360         if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) {
 361                 if ((*aarch32_opcode_cond_checks[cc_bits])(psr))
 362                         return ARM_OPCODE_CONDTEST_PASS;
 363                 else
 364                         return ARM_OPCODE_CONDTEST_FAIL;
 365         }
 366         return ARM_OPCODE_CONDTEST_UNCOND;
 367 }
 368
 369 /*
 370  * swp_handler logs the id of calling process, dissects the instruction, sanity
 371  * checks the memory location, calls emulate_swpX for the actual operation and
 372  * deals with fixup/error handling before returning
 373  */
 374 static int swp_handler(struct pt_regs *regs, u32 instr)
 375 {
 376         u32 destreg, data, type, address = 0;
 377         const void __user *user_ptr;
 378         int rn, rt2, res = 0;
 379
 380         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
 381
 382         type = instr & TYPE_SWPB;
 383
 384         switch (aarch32_check_condition(instr, regs->pstate)) {
 385         case ARM_OPCODE_CONDTEST_PASS:
 386                 break;
 387         case ARM_OPCODE_CONDTEST_FAIL:
 388                 /* Condition failed - return to next instruction */
 389                 goto ret;
 390         case ARM_OPCODE_CONDTEST_UNCOND:
 391                 /* If unconditional encoding - not a SWP, undef */
 392                 return -EFAULT;
 393         default:
 394                 return -EINVAL;
 395         }
 396
 397         rn = aarch32_insn_extract_reg_num(instr, A32_RN_OFFSET);
 398         rt2 = aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET);
 399
 400         address = (u32)regs->user_regs.regs[rn];
 401         data    = (u32)regs->user_regs.regs[rt2];
 402         destreg = aarch32_insn_extract_reg_num(instr, A32_RT_OFFSET);
 403
 404         pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n",
 405                 rn, address, destreg,
 406                 aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET), data);
 407
 408         /* Check access in reasonable access range for both SWP and SWPB */
 409         user_ptr = (const void __user *)(unsigned long)(address & ~3);
 410         if (!access_ok(user_ptr, 4)) {
 411                 pr_debug("SWP{B} emulation: access to 0x%08x not allowed!\n",
 412                         address);
 413                 goto fault;
 414         }
 415
 416         res = emulate_swpX(address, &data, type);
 417         if (res == -EFAULT)
 418                 goto fault;
 419         else if (res == 0)
 420                 regs->user_regs.regs[destreg] = data;
 421
 422 ret:
 423         if (type == TYPE_SWPB)
 424                 trace_instruction_emulation("swpb", regs->pc);
 425         else
 426                 trace_instruction_emulation("swp", regs->pc);
 427
 428         pr_warn_ratelimited("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n",
 429                         current->comm, (unsigned long)current->pid, regs->pc);
 430
 431         arm64_skip_faulting_instruction(regs, 4);
 432         return 0;
 433
 434 fault:
 435         pr_debug("SWP{B} emulation: access caused memory abort!\n");
 436         arm64_notify_segfault(address);
 437
 438         return 0;
 439 }
 440
 441 /*
 442  * Only emulate SWP/SWPB executed in ARM state/User mode.
 443  * The kernel must be SWP free and SWP{B} does not exist in Thumb.
 444  */
 445 static struct undef_hook swp_hooks[] = {
 446         {
 447                 .instr_mask     = 0x0fb00ff0,
 448                 .instr_val      = 0x01000090,
 449                 .pstate_mask    = PSR_AA32_MODE_MASK,
 450                 .pstate_val     = PSR_AA32_MODE_USR,
 451                 .fn             = swp_handler
 452         },
 453         { }
 454 };
 455
 456 static struct insn_emulation_ops swp_ops = {
 457         .name = "swp",
 458         .status = INSN_OBSOLETE,
 459         .hooks = swp_hooks,
 460         .set_hw_mode = NULL,
 461 };
 462
 463 static int cp15barrier_handler(struct pt_regs *regs, u32 instr)
 464 {
 465         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
 466
 467         switch (aarch32_check_condition(instr, regs->pstate)) {
 468         case ARM_OPCODE_CONDTEST_PASS:
 469                 break;
 470         case ARM_OPCODE_CONDTEST_FAIL:
 471                 /* Condition failed - return to next instruction */
 472                 goto ret;
 473         case ARM_OPCODE_CONDTEST_UNCOND:
 474                 /* If unconditional encoding - not a barrier instruction */
 475                 return -EFAULT;
 476         default:
 477                 return -EINVAL;
 478         }
 479
 480         switch (aarch32_insn_mcr_extract_crm(instr)) {
 481         case 10:
 482                 /*
 483                  * dmb - mcr p15, 0, Rt, c7, c10, 5
 484                  * dsb - mcr p15, 0, Rt, c7, c10, 4
 485                  */
 486                 if (aarch32_insn_mcr_extract_opc2(instr) == 5) {
 487                         dmb(sy);
 488                         trace_instruction_emulation(
 489                                 "mcr p15, 0, Rt, c7, c10, 5 ; dmb", regs->pc);
 490                 } else {
 491                         dsb(sy);
 492                         trace_instruction_emulation(
 493                                 "mcr p15, 0, Rt, c7, c10, 4 ; dsb", regs->pc);
 494                 }
 495                 break;
 496         case 5:
 497                 /*
 498                  * isb - mcr p15, 0, Rt, c7, c5, 4
 499                  *
 500                  * Taking an exception or returning from one acts as an
 501                  * instruction barrier. So no explicit barrier needed here.
 502                  */
 503                 trace_instruction_emulation(
 504                         "mcr p15, 0, Rt, c7, c5, 4 ; isb", regs->pc);
 505                 break;
 506         }
 507
 508 ret:
 509         pr_warn_ratelimited("\"%s\" (%ld) uses deprecated CP15 Barrier instruction at 0x%llx\n",
 510                         current->comm, (unsigned long)current->pid, regs->pc);
 511
 512         arm64_skip_faulting_instruction(regs, 4);
 513         return 0;
 514 }
 515
 516 static int cp15_barrier_set_hw_mode(bool enable)
 517 {
 518         if (enable)
 519                 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_CP15BEN);
 520         else
 521                 sysreg_clear_set(sctlr_el1, SCTLR_EL1_CP15BEN, 0);
 522         return 0;
 523 }
 524
 525 static struct undef_hook cp15_barrier_hooks[] = {
 526         {
 527                 .instr_mask     = 0x0fff0fdf,
 528                 .instr_val      = 0x0e070f9a,
 529                 .pstate_mask    = PSR_AA32_MODE_MASK,
 530                 .pstate_val     = PSR_AA32_MODE_USR,
 531                 .fn             = cp15barrier_handler,
 532         },
 533         {
 534                 .instr_mask     = 0x0fff0fff,
 535                 .instr_val      = 0x0e070f95,
 536                 .pstate_mask    = PSR_AA32_MODE_MASK,
 537                 .pstate_val     = PSR_AA32_MODE_USR,
 538                 .fn             = cp15barrier_handler,
 539         },
 540         { }
 541 };
 542
 543 static struct insn_emulation_ops cp15_barrier_ops = {
 544         .name = "cp15_barrier",
 545         .status = INSN_DEPRECATED,
 546         .hooks = cp15_barrier_hooks,
 547         .set_hw_mode = cp15_barrier_set_hw_mode,
 548 };
 549
 550 static int setend_set_hw_mode(bool enable)
 551 {
 552         if (!cpu_supports_mixed_endian_el0())
 553                 return -EINVAL;
 554
 555         if (enable)
 556                 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SED, 0);
 557         else
 558                 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_SED);
 559         return 0;
 560 }
 561
 562 static int compat_setend_handler(struct pt_regs *regs, u32 big_endian)
 563 {
 564         char *insn;
 565
 566         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
 567
 568         if (big_endian) {
 569                 insn = "setend be";
 570                 regs->pstate |= PSR_AA32_E_BIT;
 571         } else {
 572                 insn = "setend le";
 573                 regs->pstate &= ~PSR_AA32_E_BIT;
 574         }
 575
 576         trace_instruction_emulation(insn, regs->pc);
 577         pr_warn_ratelimited("\"%s\" (%ld) uses deprecated setend instruction at 0x%llx\n",
 578                         current->comm, (unsigned long)current->pid, regs->pc);
 579
 580         return 0;
 581 }
 582
 583 static int a32_setend_handler(struct pt_regs *regs, u32 instr)
 584 {
 585         int rc = compat_setend_handler(regs, (instr >> 9) & 1);
 586         arm64_skip_faulting_instruction(regs, 4);
 587         return rc;
 588 }
 589
 590 static int t16_setend_handler(struct pt_regs *regs, u32 instr)
 591 {
 592         int rc = compat_setend_handler(regs, (instr >> 3) & 1);
 593         arm64_skip_faulting_instruction(regs, 2);
 594         return rc;
 595 }
 596
 597 static struct undef_hook setend_hooks[] = {
 598         {
 599                 .instr_mask     = 0xfffffdff,
 600                 .instr_val      = 0xf1010000,
 601                 .pstate_mask    = PSR_AA32_MODE_MASK,
 602                 .pstate_val     = PSR_AA32_MODE_USR,
 603                 .fn             = a32_setend_handler,
 604         },
 605         {
 606                 /* Thumb mode */
 607                 .instr_mask     = 0xfffffff7,
 608                 .instr_val      = 0x0000b650,
 609                 .pstate_mask    = (PSR_AA32_T_BIT | PSR_AA32_MODE_MASK),
 610                 .pstate_val     = (PSR_AA32_T_BIT | PSR_AA32_MODE_USR),
 611                 .fn             = t16_setend_handler,
 612         },
 613         {}
 614 };
 615
 616 static struct insn_emulation_ops setend_ops = {
 617         .name = "setend",
 618         .status = INSN_DEPRECATED,
 619         .hooks = setend_hooks,
 620         .set_hw_mode = setend_set_hw_mode,
 621 };
 622
 623 /*
 624  * Invoked as late_initcall, since not needed before init spawned.
 625  */
 626 static int __init armv8_deprecated_init(void)
 627 {
 628         if (IS_ENABLED(CONFIG_SWP_EMULATION))
 629                 register_insn_emulation(&swp_ops);
 630
 631         if (IS_ENABLED(CONFIG_CP15_BARRIER_EMULATION))
 632                 register_insn_emulation(&cp15_barrier_ops);
 633
 634         if (IS_ENABLED(CONFIG_SETEND_EMULATION)) {
 635                 if(system_supports_mixed_endian_el0())
 636                         register_insn_emulation(&setend_ops);
 637                 else
 638                         pr_info("setend instruction emulation is not supported on this system\n");
 639         }
 640
 641         cpuhp_setup_state_nocalls(CPUHP_AP_ARM64_ISNDEP_STARTING,
 642                                   "arm64/isndep:starting",
 643                                   run_all_insn_set_hw_mode, NULL);
 644         register_insn_emulation_sysctl();
 645
 646         return 0;
 647 }
 648
 649 core_initcall(armv8_deprecated_init);