2 * Copyright (C) 2014 ARM Limited
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/init.h>
11 #include <linux/list.h>
12 #include <linux/perf_event.h>
13 #include <linux/sched.h>
14 #include <linux/slab.h>
15 #include <linux/sysctl.h>
17 #include <asm/cpufeature.h>
19 #include <asm/sysreg.h>
20 #include <asm/system_misc.h>
21 #include <asm/traps.h>
22 #include <asm/kprobes.h>
23 #include <linux/uaccess.h>
24 #include <asm/cpufeature.h>
26 #define CREATE_TRACE_POINTS
27 #include "trace-events-emulation.h"
30 * The runtime support for deprecated instruction support can be in one of
31 * following three states -
34 * 1 = emulate (software emulation)
35 * 2 = hw (supported in hardware)
37 enum insn_emulation_mode {
43 enum legacy_insn_status {
48 struct insn_emulation_ops {
50 enum legacy_insn_status status;
51 struct undef_hook *hooks;
52 int (*set_hw_mode)(bool enable);
55 struct insn_emulation {
56 struct list_head node;
57 struct insn_emulation_ops *ops;
63 static LIST_HEAD(insn_emulation);
64 static int nr_insn_emulated __initdata;
65 static DEFINE_RAW_SPINLOCK(insn_emulation_lock);
67 static void register_emulation_hooks(struct insn_emulation_ops *ops)
69 struct undef_hook *hook;
73 for (hook = ops->hooks; hook->instr_mask; hook++)
74 register_undef_hook(hook);
76 pr_notice("Registered %s emulation handler\n", ops->name);
79 static void remove_emulation_hooks(struct insn_emulation_ops *ops)
81 struct undef_hook *hook;
85 for (hook = ops->hooks; hook->instr_mask; hook++)
86 unregister_undef_hook(hook);
88 pr_notice("Removed %s emulation handler\n", ops->name);
91 static void enable_insn_hw_mode(void *data)
93 struct insn_emulation *insn = (struct insn_emulation *)data;
94 if (insn->ops->set_hw_mode)
95 insn->ops->set_hw_mode(true);
98 static void disable_insn_hw_mode(void *data)
100 struct insn_emulation *insn = (struct insn_emulation *)data;
101 if (insn->ops->set_hw_mode)
102 insn->ops->set_hw_mode(false);
105 /* Run set_hw_mode(mode) on all active CPUs */
106 static int run_all_cpu_set_hw_mode(struct insn_emulation *insn, bool enable)
108 if (!insn->ops->set_hw_mode)
111 on_each_cpu(enable_insn_hw_mode, (void *)insn, true);
113 on_each_cpu(disable_insn_hw_mode, (void *)insn, true);
118 * Run set_hw_mode for all insns on a starting CPU.
120 * 0 - If all the hooks ran successfully.
121 * -EINVAL - At least one hook is not supported by the CPU.
123 static int run_all_insn_set_hw_mode(unsigned int cpu)
127 struct insn_emulation *insn;
129 raw_spin_lock_irqsave(&insn_emulation_lock, flags);
130 list_for_each_entry(insn, &insn_emulation, node) {
131 bool enable = (insn->current_mode == INSN_HW);
132 if (insn->ops->set_hw_mode && insn->ops->set_hw_mode(enable)) {
133 pr_warn("CPU[%u] cannot support the emulation of %s",
134 cpu, insn->ops->name);
138 raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
142 static int update_insn_emulation_mode(struct insn_emulation *insn,
143 enum insn_emulation_mode prev)
148 case INSN_UNDEF: /* Nothing to be done */
151 remove_emulation_hooks(insn->ops);
154 if (!run_all_cpu_set_hw_mode(insn, false))
155 pr_notice("Disabled %s support\n", insn->ops->name);
159 switch (insn->current_mode) {
163 register_emulation_hooks(insn->ops);
166 ret = run_all_cpu_set_hw_mode(insn, true);
168 pr_notice("Enabled %s support\n", insn->ops->name);
175 static void __init register_insn_emulation(struct insn_emulation_ops *ops)
178 struct insn_emulation *insn;
180 insn = kzalloc(sizeof(*insn), GFP_KERNEL);
182 insn->min = INSN_UNDEF;
184 switch (ops->status) {
185 case INSN_DEPRECATED:
186 insn->current_mode = INSN_EMULATE;
187 /* Disable the HW mode if it was turned on at early boot time */
188 run_all_cpu_set_hw_mode(insn, false);
192 insn->current_mode = INSN_UNDEF;
193 insn->max = INSN_EMULATE;
197 raw_spin_lock_irqsave(&insn_emulation_lock, flags);
198 list_add(&insn->node, &insn_emulation);
200 raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
202 /* Register any handlers if required */
203 update_insn_emulation_mode(insn, INSN_UNDEF);
206 static int emulation_proc_handler(struct ctl_table *table, int write,
207 void __user *buffer, size_t *lenp,
211 struct insn_emulation *insn = (struct insn_emulation *) table->data;
212 enum insn_emulation_mode prev_mode = insn->current_mode;
214 table->data = &insn->current_mode;
215 ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
217 if (ret || !write || prev_mode == insn->current_mode)
220 ret = update_insn_emulation_mode(insn, prev_mode);
222 /* Mode change failed, revert to previous mode. */
223 insn->current_mode = prev_mode;
224 update_insn_emulation_mode(insn, INSN_UNDEF);
231 static struct ctl_table ctl_abi[] = {
239 static void __init register_insn_emulation_sysctl(struct ctl_table *table)
243 struct insn_emulation *insn;
244 struct ctl_table *insns_sysctl, *sysctl;
246 insns_sysctl = kzalloc(sizeof(*sysctl) * (nr_insn_emulated + 1),
249 raw_spin_lock_irqsave(&insn_emulation_lock, flags);
250 list_for_each_entry(insn, &insn_emulation, node) {
251 sysctl = &insns_sysctl[i];
254 sysctl->maxlen = sizeof(int);
256 sysctl->procname = insn->ops->name;
258 sysctl->extra1 = &insn->min;
259 sysctl->extra2 = &insn->max;
260 sysctl->proc_handler = emulation_proc_handler;
263 raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
265 table->child = insns_sysctl;
266 register_sysctl_table(table);
270 * Implement emulation of the SWP/SWPB instructions using load-exclusive and
273 * Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>]
274 * Where: Rt = destination
280 * Error-checking SWP macros implemented using ldxr{b}/stxr{b}
283 /* Arbitrary constant to ensure forward-progress of the LL/SC loop */
284 #define __SWP_LL_SC_LOOPS 4
286 #define __user_swpX_asm(data, addr, res, temp, temp2, B) \
289 __asm__ __volatile__( \
291 "0: ldxr"B" %w2, [%4]\n" \
292 "1: stxr"B" %w0, %w1, [%4]\n" \
294 " sub %w3, %w3, #1\n" \
301 " .pushsection .fixup,\"ax\"\n" \
303 "4: mov %w0, %w6\n" \
306 _ASM_EXTABLE(0b, 4b) \
307 _ASM_EXTABLE(1b, 4b) \
308 : "=&r" (res), "+r" (data), "=&r" (temp), "=&r" (temp2) \
309 : "r" ((unsigned long)addr), "i" (-EAGAIN), \
311 "i" (__SWP_LL_SC_LOOPS) \
316 #define __user_swp_asm(data, addr, res, temp, temp2) \
317 __user_swpX_asm(data, addr, res, temp, temp2, "")
318 #define __user_swpb_asm(data, addr, res, temp, temp2) \
319 __user_swpX_asm(data, addr, res, temp, temp2, "b")
322 * Bit 22 of the instruction encoding distinguishes between
323 * the SWP and SWPB variants (bit set means SWPB).
325 #define TYPE_SWPB (1 << 22)
327 static int emulate_swpX(unsigned int address, unsigned int *data,
330 unsigned int res = 0;
332 if ((type != TYPE_SWPB) && (address & 0x3)) {
333 /* SWP to unaligned address not permitted */
334 pr_debug("SWP instruction on unaligned pointer!\n");
339 unsigned long temp, temp2;
341 if (type == TYPE_SWPB)
342 __user_swpb_asm(*data, address, res, temp, temp2);
344 __user_swp_asm(*data, address, res, temp, temp2);
346 if (likely(res != -EAGAIN) || signal_pending(current))
355 #define ARM_OPCODE_CONDTEST_FAIL 0
356 #define ARM_OPCODE_CONDTEST_PASS 1
357 #define ARM_OPCODE_CONDTEST_UNCOND 2
359 #define ARM_OPCODE_CONDITION_UNCOND 0xf
361 static unsigned int __kprobes aarch32_check_condition(u32 opcode, u32 psr)
363 u32 cc_bits = opcode >> 28;
365 if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) {
366 if ((*aarch32_opcode_cond_checks[cc_bits])(psr))
367 return ARM_OPCODE_CONDTEST_PASS;
369 return ARM_OPCODE_CONDTEST_FAIL;
371 return ARM_OPCODE_CONDTEST_UNCOND;
375 * swp_handler logs the id of calling process, dissects the instruction, sanity
376 * checks the memory location, calls emulate_swpX for the actual operation and
377 * deals with fixup/error handling before returning
379 static int swp_handler(struct pt_regs *regs, u32 instr)
381 u32 destreg, data, type, address = 0;
382 int rn, rt2, res = 0;
384 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
386 type = instr & TYPE_SWPB;
388 switch (aarch32_check_condition(instr, regs->pstate)) {
389 case ARM_OPCODE_CONDTEST_PASS:
391 case ARM_OPCODE_CONDTEST_FAIL:
392 /* Condition failed - return to next instruction */
394 case ARM_OPCODE_CONDTEST_UNCOND:
395 /* If unconditional encoding - not a SWP, undef */
401 rn = aarch32_insn_extract_reg_num(instr, A32_RN_OFFSET);
402 rt2 = aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET);
404 address = (u32)regs->user_regs.regs[rn];
405 data = (u32)regs->user_regs.regs[rt2];
406 destreg = aarch32_insn_extract_reg_num(instr, A32_RT_OFFSET);
408 pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n",
409 rn, address, destreg,
410 aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET), data);
412 /* Check access in reasonable access range for both SWP and SWPB */
413 if (!access_ok(VERIFY_WRITE, (address & ~3), 4)) {
414 pr_debug("SWP{B} emulation: access to 0x%08x not allowed!\n",
419 res = emulate_swpX(address, &data, type);
423 regs->user_regs.regs[destreg] = data;
426 if (type == TYPE_SWPB)
427 trace_instruction_emulation("swpb", regs->pc);
429 trace_instruction_emulation("swp", regs->pc);
431 pr_warn_ratelimited("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n",
432 current->comm, (unsigned long)current->pid, regs->pc);
434 arm64_skip_faulting_instruction(regs, 4);
438 pr_debug("SWP{B} emulation: access caused memory abort!\n");
439 arm64_notify_segfault(regs, address);
445 * Only emulate SWP/SWPB executed in ARM state/User mode.
446 * The kernel must be SWP free and SWP{B} does not exist in Thumb.
448 static struct undef_hook swp_hooks[] = {
450 .instr_mask = 0x0fb00ff0,
451 .instr_val = 0x01000090,
452 .pstate_mask = COMPAT_PSR_MODE_MASK,
453 .pstate_val = COMPAT_PSR_MODE_USR,
459 static struct insn_emulation_ops swp_ops = {
461 .status = INSN_OBSOLETE,
466 static int cp15barrier_handler(struct pt_regs *regs, u32 instr)
468 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
470 switch (aarch32_check_condition(instr, regs->pstate)) {
471 case ARM_OPCODE_CONDTEST_PASS:
473 case ARM_OPCODE_CONDTEST_FAIL:
474 /* Condition failed - return to next instruction */
476 case ARM_OPCODE_CONDTEST_UNCOND:
477 /* If unconditional encoding - not a barrier instruction */
483 switch (aarch32_insn_mcr_extract_crm(instr)) {
486 * dmb - mcr p15, 0, Rt, c7, c10, 5
487 * dsb - mcr p15, 0, Rt, c7, c10, 4
489 if (aarch32_insn_mcr_extract_opc2(instr) == 5) {
491 trace_instruction_emulation(
492 "mcr p15, 0, Rt, c7, c10, 5 ; dmb", regs->pc);
495 trace_instruction_emulation(
496 "mcr p15, 0, Rt, c7, c10, 4 ; dsb", regs->pc);
501 * isb - mcr p15, 0, Rt, c7, c5, 4
503 * Taking an exception or returning from one acts as an
504 * instruction barrier. So no explicit barrier needed here.
506 trace_instruction_emulation(
507 "mcr p15, 0, Rt, c7, c5, 4 ; isb", regs->pc);
512 pr_warn_ratelimited("\"%s\" (%ld) uses deprecated CP15 Barrier instruction at 0x%llx\n",
513 current->comm, (unsigned long)current->pid, regs->pc);
515 arm64_skip_faulting_instruction(regs, 4);
519 static int cp15_barrier_set_hw_mode(bool enable)
522 config_sctlr_el1(0, SCTLR_EL1_CP15BEN);
524 config_sctlr_el1(SCTLR_EL1_CP15BEN, 0);
528 static struct undef_hook cp15_barrier_hooks[] = {
530 .instr_mask = 0x0fff0fdf,
531 .instr_val = 0x0e070f9a,
532 .pstate_mask = COMPAT_PSR_MODE_MASK,
533 .pstate_val = COMPAT_PSR_MODE_USR,
534 .fn = cp15barrier_handler,
537 .instr_mask = 0x0fff0fff,
538 .instr_val = 0x0e070f95,
539 .pstate_mask = COMPAT_PSR_MODE_MASK,
540 .pstate_val = COMPAT_PSR_MODE_USR,
541 .fn = cp15barrier_handler,
546 static struct insn_emulation_ops cp15_barrier_ops = {
547 .name = "cp15_barrier",
548 .status = INSN_DEPRECATED,
549 .hooks = cp15_barrier_hooks,
550 .set_hw_mode = cp15_barrier_set_hw_mode,
553 static int setend_set_hw_mode(bool enable)
555 if (!cpu_supports_mixed_endian_el0())
559 config_sctlr_el1(SCTLR_EL1_SED, 0);
561 config_sctlr_el1(0, SCTLR_EL1_SED);
565 static int compat_setend_handler(struct pt_regs *regs, u32 big_endian)
569 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
573 regs->pstate |= COMPAT_PSR_E_BIT;
576 regs->pstate &= ~COMPAT_PSR_E_BIT;
579 trace_instruction_emulation(insn, regs->pc);
580 pr_warn_ratelimited("\"%s\" (%ld) uses deprecated setend instruction at 0x%llx\n",
581 current->comm, (unsigned long)current->pid, regs->pc);
586 static int a32_setend_handler(struct pt_regs *regs, u32 instr)
588 int rc = compat_setend_handler(regs, (instr >> 9) & 1);
589 arm64_skip_faulting_instruction(regs, 4);
593 static int t16_setend_handler(struct pt_regs *regs, u32 instr)
595 int rc = compat_setend_handler(regs, (instr >> 3) & 1);
596 arm64_skip_faulting_instruction(regs, 2);
600 static struct undef_hook setend_hooks[] = {
602 .instr_mask = 0xfffffdff,
603 .instr_val = 0xf1010000,
604 .pstate_mask = COMPAT_PSR_MODE_MASK,
605 .pstate_val = COMPAT_PSR_MODE_USR,
606 .fn = a32_setend_handler,
610 .instr_mask = 0xfffffff7,
611 .instr_val = 0x0000b650,
612 .pstate_mask = (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_MASK),
613 .pstate_val = (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_USR),
614 .fn = t16_setend_handler,
619 static struct insn_emulation_ops setend_ops = {
621 .status = INSN_DEPRECATED,
622 .hooks = setend_hooks,
623 .set_hw_mode = setend_set_hw_mode,
627 * Invoked as late_initcall, since not needed before init spawned.
629 static int __init armv8_deprecated_init(void)
631 if (IS_ENABLED(CONFIG_SWP_EMULATION))
632 register_insn_emulation(&swp_ops);
634 if (IS_ENABLED(CONFIG_CP15_BARRIER_EMULATION))
635 register_insn_emulation(&cp15_barrier_ops);
637 if (IS_ENABLED(CONFIG_SETEND_EMULATION)) {
638 if(system_supports_mixed_endian_el0())
639 register_insn_emulation(&setend_ops);
641 pr_info("setend instruction emulation is not supported on this system\n");
644 cpuhp_setup_state_nocalls(CPUHP_AP_ARM64_ISNDEP_STARTING,
645 "arm64/isndep:starting",
646 run_all_insn_set_hw_mode, NULL);
647 register_insn_emulation_sysctl(ctl_abi);
652 core_initcall(armv8_deprecated_init);