1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Macros for accessing system registers with older binutils.
5 * Copyright (C) 2014 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
10 #define __ASM_SYSREG_H
12 #include <linux/bits.h>
13 #include <linux/stringify.h>
16 * ARMv8 ARM reserves the following encoding for system registers:
17 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
18 * C5.2, version:ARM DDI 0487A.f)
36 #define sys_reg(op0, op1, crn, crm, op2) \
37 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \
38 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
41 #define sys_insn sys_reg
43 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask)
44 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask)
45 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask)
46 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask)
47 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask)
49 #ifndef CONFIG_BROKEN_GAS_INST
52 // The space separator is omitted so that __emit_inst(x) can be parsed as
53 // either an assembler directive or an assembler macro argument.
54 #define __emit_inst(x) .inst(x)
56 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t"
59 #else /* CONFIG_BROKEN_GAS_INST */
61 #ifndef CONFIG_CPU_BIG_ENDIAN
62 #define __INSTR_BSWAP(x) (x)
63 #else /* CONFIG_CPU_BIG_ENDIAN */
64 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \
65 (((x) << 8) & 0x00ff0000) | \
66 (((x) >> 8) & 0x0000ff00) | \
67 (((x) >> 24) & 0x000000ff))
68 #endif /* CONFIG_CPU_BIG_ENDIAN */
71 #define __emit_inst(x) .long __INSTR_BSWAP(x)
72 #else /* __ASSEMBLY__ */
73 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t"
74 #endif /* __ASSEMBLY__ */
76 #endif /* CONFIG_BROKEN_GAS_INST */
79 * Instructions for modifying PSTATE fields.
80 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
81 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions
82 * for accessing PSTATE fields have the following encoding:
84 * Op1, Op2 encodes the PSTATE field modified and defines the constraints.
85 * CRm = Imm4 for the instruction.
88 #define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift)
89 #define PSTATE_Imm_shift CRm_shift
91 #define PSTATE_PAN pstate_field(0, 4)
92 #define PSTATE_UAO pstate_field(0, 3)
93 #define PSTATE_SSBS pstate_field(3, 1)
95 #define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift))
96 #define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
97 #define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
99 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \
100 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
102 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31)
104 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
105 #define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4)
106 #define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6)
107 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
108 #define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4)
109 #define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6)
110 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
111 #define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4)
112 #define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6)
114 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2)
115 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0)
116 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2)
117 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2)
118 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2)
119 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
120 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
121 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
122 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
123 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
124 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4)
125 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
126 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
127 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
128 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
129 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
130 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
131 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
132 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
133 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
134 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
135 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
137 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
138 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
139 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
141 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0)
142 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
143 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
144 #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
145 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4)
146 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
147 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
148 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)
150 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0)
151 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)
152 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2)
153 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
154 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
155 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5)
156 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)
158 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
159 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
160 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
162 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0)
163 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1)
164 #define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4)
166 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0)
167 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1)
169 #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4)
170 #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5)
172 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
173 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
174 #define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2)
176 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
177 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
178 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
180 #define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0)
181 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
182 #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2)
184 #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
186 #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
187 #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
188 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
190 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
191 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1)
192 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2)
193 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3)
195 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0)
196 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1)
197 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2)
198 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3)
200 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0)
201 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1)
203 #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0)
204 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1)
206 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
208 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
209 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
210 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
212 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
213 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
214 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
215 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
216 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
217 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
218 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
219 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
221 #define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0)
222 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
224 #define SYS_PAR_EL1_F BIT(0)
225 #define SYS_PAR_EL1_FST GENMASK(6, 1)
227 /*** Statistical Profiling Extension ***/
229 #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7)
230 #define SYS_PMSIDR_EL1_FE_SHIFT 0
231 #define SYS_PMSIDR_EL1_FT_SHIFT 1
232 #define SYS_PMSIDR_EL1_FL_SHIFT 2
233 #define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3
234 #define SYS_PMSIDR_EL1_LDS_SHIFT 4
235 #define SYS_PMSIDR_EL1_ERND_SHIFT 5
236 #define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8
237 #define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL
238 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12
239 #define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL
240 #define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16
241 #define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL
243 #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7)
244 #define SYS_PMBIDR_EL1_ALIGN_SHIFT 0
245 #define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU
246 #define SYS_PMBIDR_EL1_P_SHIFT 4
247 #define SYS_PMBIDR_EL1_F_SHIFT 5
249 /* Sampling controls */
250 #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0)
251 #define SYS_PMSCR_EL1_E0SPE_SHIFT 0
252 #define SYS_PMSCR_EL1_E1SPE_SHIFT 1
253 #define SYS_PMSCR_EL1_CX_SHIFT 3
254 #define SYS_PMSCR_EL1_PA_SHIFT 4
255 #define SYS_PMSCR_EL1_TS_SHIFT 5
256 #define SYS_PMSCR_EL1_PCT_SHIFT 6
258 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0)
259 #define SYS_PMSCR_EL2_E0HSPE_SHIFT 0
260 #define SYS_PMSCR_EL2_E2SPE_SHIFT 1
261 #define SYS_PMSCR_EL2_CX_SHIFT 3
262 #define SYS_PMSCR_EL2_PA_SHIFT 4
263 #define SYS_PMSCR_EL2_TS_SHIFT 5
264 #define SYS_PMSCR_EL2_PCT_SHIFT 6
266 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2)
268 #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3)
269 #define SYS_PMSIRR_EL1_RND_SHIFT 0
270 #define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8
271 #define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL
273 /* Filtering controls */
274 #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4)
275 #define SYS_PMSFCR_EL1_FE_SHIFT 0
276 #define SYS_PMSFCR_EL1_FT_SHIFT 1
277 #define SYS_PMSFCR_EL1_FL_SHIFT 2
278 #define SYS_PMSFCR_EL1_B_SHIFT 16
279 #define SYS_PMSFCR_EL1_LD_SHIFT 17
280 #define SYS_PMSFCR_EL1_ST_SHIFT 18
282 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5)
283 #define SYS_PMSEVFR_EL1_RES0 0x0000ffff00ff0f55UL
285 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6)
286 #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0
288 /* Buffer controls */
289 #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0)
290 #define SYS_PMBLIMITR_EL1_E_SHIFT 0
291 #define SYS_PMBLIMITR_EL1_FM_SHIFT 1
292 #define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL
293 #define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT)
295 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1)
297 /* Buffer error reporting */
298 #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3)
299 #define SYS_PMBSR_EL1_COLL_SHIFT 16
300 #define SYS_PMBSR_EL1_S_SHIFT 17
301 #define SYS_PMBSR_EL1_EA_SHIFT 18
302 #define SYS_PMBSR_EL1_DL_SHIFT 19
303 #define SYS_PMBSR_EL1_EC_SHIFT 26
304 #define SYS_PMBSR_EL1_EC_MASK 0x3fUL
306 #define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT)
307 #define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT)
308 #define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT)
310 #define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0
311 #define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL
313 #define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0
314 #define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL
316 #define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT)
318 /*** End of Statistical Profiling Extension ***/
320 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
321 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
323 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
324 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
326 #define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0)
327 #define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1)
328 #define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2)
329 #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3)
330 #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7)
332 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
333 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
335 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
336 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
337 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
338 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
339 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
340 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0)
341 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1)
342 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2)
343 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3)
344 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
345 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0)
346 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1)
347 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2)
348 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3)
349 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
350 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
351 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
352 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
353 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
354 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
355 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
356 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
357 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
358 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
359 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
360 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
361 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
363 #define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1)
364 #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4)
366 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
368 #define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0)
369 #define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1)
370 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
372 #define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0)
374 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
375 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
377 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
378 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
379 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
380 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
381 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
382 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
383 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
384 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
385 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
386 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
387 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
388 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
389 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
391 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
392 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
394 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
396 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
397 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
398 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
400 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1)
401 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2)
403 #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0)
404 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1)
405 #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0)
407 #define __PMEV_op2(n) ((n) & 0x7)
408 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
409 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
410 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
411 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
413 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
415 #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0)
416 #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
417 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
418 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
419 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
420 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
421 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
422 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
423 #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
425 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
426 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
427 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0)
428 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1)
429 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2)
430 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
432 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
433 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0)
434 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1)
435 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2)
436 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
438 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
439 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
440 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
441 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
442 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
443 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
444 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
445 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
447 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
448 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0)
449 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1)
450 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2)
451 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
452 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4)
453 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5)
454 #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6)
455 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7)
457 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
458 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0)
459 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1)
460 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2)
461 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
462 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4)
463 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5)
464 #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6)
465 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
467 /* VHE encodings for architectural EL0/1 system registers */
468 #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
469 #define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
470 #define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0)
471 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
472 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
473 #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
474 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
475 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
476 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
477 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
478 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
479 #define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0)
480 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
481 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
482 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
483 #define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1)
484 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
485 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
486 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
487 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
488 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
489 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
490 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
492 /* Common SCTLR_ELx flags. */
493 #define SCTLR_ELx_DSSBS (BIT(44))
494 #define SCTLR_ELx_ENIA (BIT(31))
495 #define SCTLR_ELx_ENIB (BIT(30))
496 #define SCTLR_ELx_ENDA (BIT(27))
497 #define SCTLR_ELx_EE (BIT(25))
498 #define SCTLR_ELx_IESB (BIT(21))
499 #define SCTLR_ELx_WXN (BIT(19))
500 #define SCTLR_ELx_ENDB (BIT(13))
501 #define SCTLR_ELx_I (BIT(12))
502 #define SCTLR_ELx_SA (BIT(3))
503 #define SCTLR_ELx_C (BIT(2))
504 #define SCTLR_ELx_A (BIT(1))
505 #define SCTLR_ELx_M (BIT(0))
507 #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \
508 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_IESB)
510 /* SCTLR_EL2 specific flags. */
511 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \
512 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
515 #ifdef CONFIG_CPU_BIG_ENDIAN
516 #define ENDIAN_SET_EL2 SCTLR_ELx_EE
518 #define ENDIAN_SET_EL2 0
521 /* SCTLR_EL1 specific flags. */
522 #define SCTLR_EL1_UCI (BIT(26))
523 #define SCTLR_EL1_E0E (BIT(24))
524 #define SCTLR_EL1_SPAN (BIT(23))
525 #define SCTLR_EL1_NTWE (BIT(18))
526 #define SCTLR_EL1_NTWI (BIT(16))
527 #define SCTLR_EL1_UCT (BIT(15))
528 #define SCTLR_EL1_DZE (BIT(14))
529 #define SCTLR_EL1_UMA (BIT(9))
530 #define SCTLR_EL1_SED (BIT(8))
531 #define SCTLR_EL1_ITD (BIT(7))
532 #define SCTLR_EL1_CP15BEN (BIT(5))
533 #define SCTLR_EL1_SA0 (BIT(4))
535 #define SCTLR_EL1_RES1 ((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \
538 #ifdef CONFIG_CPU_BIG_ENDIAN
539 #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE)
541 #define ENDIAN_SET_EL1 0
544 #define SCTLR_EL1_SET (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA |\
545 SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I |\
546 SCTLR_EL1_DZE | SCTLR_EL1_UCT |\
547 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN |\
548 ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_RES1)
551 #define ID_AA64ISAR0_TS_SHIFT 52
552 #define ID_AA64ISAR0_FHM_SHIFT 48
553 #define ID_AA64ISAR0_DP_SHIFT 44
554 #define ID_AA64ISAR0_SM4_SHIFT 40
555 #define ID_AA64ISAR0_SM3_SHIFT 36
556 #define ID_AA64ISAR0_SHA3_SHIFT 32
557 #define ID_AA64ISAR0_RDM_SHIFT 28
558 #define ID_AA64ISAR0_ATOMICS_SHIFT 20
559 #define ID_AA64ISAR0_CRC32_SHIFT 16
560 #define ID_AA64ISAR0_SHA2_SHIFT 12
561 #define ID_AA64ISAR0_SHA1_SHIFT 8
562 #define ID_AA64ISAR0_AES_SHIFT 4
565 #define ID_AA64ISAR1_SB_SHIFT 36
566 #define ID_AA64ISAR1_FRINTTS_SHIFT 32
567 #define ID_AA64ISAR1_GPI_SHIFT 28
568 #define ID_AA64ISAR1_GPA_SHIFT 24
569 #define ID_AA64ISAR1_LRCPC_SHIFT 20
570 #define ID_AA64ISAR1_FCMA_SHIFT 16
571 #define ID_AA64ISAR1_JSCVT_SHIFT 12
572 #define ID_AA64ISAR1_API_SHIFT 8
573 #define ID_AA64ISAR1_APA_SHIFT 4
574 #define ID_AA64ISAR1_DPB_SHIFT 0
576 #define ID_AA64ISAR1_APA_NI 0x0
577 #define ID_AA64ISAR1_APA_ARCHITECTED 0x1
578 #define ID_AA64ISAR1_API_NI 0x0
579 #define ID_AA64ISAR1_API_IMP_DEF 0x1
580 #define ID_AA64ISAR1_GPA_NI 0x0
581 #define ID_AA64ISAR1_GPA_ARCHITECTED 0x1
582 #define ID_AA64ISAR1_GPI_NI 0x0
583 #define ID_AA64ISAR1_GPI_IMP_DEF 0x1
586 #define ID_AA64ISAR2_CLEARBHB_SHIFT 28
587 #define ID_AA64ISAR2_RPRES_SHIFT 4
588 #define ID_AA64ISAR2_WFXT_SHIFT 0
590 #define ID_AA64ISAR2_RPRES_8BIT 0x0
591 #define ID_AA64ISAR2_RPRES_12BIT 0x1
593 * Value 0x1 has been removed from the architecture, and is
594 * reserved, but has not yet been removed from the ARM ARM
595 * as of ARM DDI 0487G.b.
597 #define ID_AA64ISAR2_WFXT_NI 0x0
598 #define ID_AA64ISAR2_WFXT_SUPPORTED 0x2
601 #define ID_AA64PFR0_CSV3_SHIFT 60
602 #define ID_AA64PFR0_CSV2_SHIFT 56
603 #define ID_AA64PFR0_DIT_SHIFT 48
604 #define ID_AA64PFR0_SVE_SHIFT 32
605 #define ID_AA64PFR0_RAS_SHIFT 28
606 #define ID_AA64PFR0_GIC_SHIFT 24
607 #define ID_AA64PFR0_ASIMD_SHIFT 20
608 #define ID_AA64PFR0_FP_SHIFT 16
609 #define ID_AA64PFR0_EL3_SHIFT 12
610 #define ID_AA64PFR0_EL2_SHIFT 8
611 #define ID_AA64PFR0_EL1_SHIFT 4
612 #define ID_AA64PFR0_EL0_SHIFT 0
614 #define ID_AA64PFR0_SVE 0x1
615 #define ID_AA64PFR0_RAS_V1 0x1
616 #define ID_AA64PFR0_FP_NI 0xf
617 #define ID_AA64PFR0_FP_SUPPORTED 0x0
618 #define ID_AA64PFR0_ASIMD_NI 0xf
619 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0
620 #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1
621 #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1
622 #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2
625 #define ID_AA64PFR1_SSBS_SHIFT 4
627 #define ID_AA64PFR1_SSBS_PSTATE_NI 0
628 #define ID_AA64PFR1_SSBS_PSTATE_ONLY 1
629 #define ID_AA64PFR1_SSBS_PSTATE_INSNS 2
632 #define ID_AA64ZFR0_SM4_SHIFT 40
633 #define ID_AA64ZFR0_SHA3_SHIFT 32
634 #define ID_AA64ZFR0_BITPERM_SHIFT 16
635 #define ID_AA64ZFR0_AES_SHIFT 4
636 #define ID_AA64ZFR0_SVEVER_SHIFT 0
638 #define ID_AA64ZFR0_SM4 0x1
639 #define ID_AA64ZFR0_SHA3 0x1
640 #define ID_AA64ZFR0_BITPERM 0x1
641 #define ID_AA64ZFR0_AES 0x1
642 #define ID_AA64ZFR0_AES_PMULL 0x2
643 #define ID_AA64ZFR0_SVEVER_SVE2 0x1
646 #define ID_AA64MMFR0_TGRAN4_SHIFT 28
647 #define ID_AA64MMFR0_TGRAN64_SHIFT 24
648 #define ID_AA64MMFR0_TGRAN16_SHIFT 20
649 #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16
650 #define ID_AA64MMFR0_SNSMEM_SHIFT 12
651 #define ID_AA64MMFR0_BIGENDEL_SHIFT 8
652 #define ID_AA64MMFR0_ASID_SHIFT 4
653 #define ID_AA64MMFR0_PARANGE_SHIFT 0
655 #define ID_AA64MMFR0_TGRAN4_NI 0xf
656 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
657 #define ID_AA64MMFR0_TGRAN64_NI 0xf
658 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
659 #define ID_AA64MMFR0_TGRAN16_NI 0x0
660 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
661 #define ID_AA64MMFR0_PARANGE_48 0x5
662 #define ID_AA64MMFR0_PARANGE_52 0x6
664 #ifdef CONFIG_ARM64_PA_BITS_52
665 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_52
667 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_48
671 #define ID_AA64MMFR1_ECBHB_SHIFT 60
672 #define ID_AA64MMFR1_PAN_SHIFT 20
673 #define ID_AA64MMFR1_LOR_SHIFT 16
674 #define ID_AA64MMFR1_HPD_SHIFT 12
675 #define ID_AA64MMFR1_VHE_SHIFT 8
676 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4
677 #define ID_AA64MMFR1_HADBS_SHIFT 0
679 #define ID_AA64MMFR1_VMIDBITS_8 0
680 #define ID_AA64MMFR1_VMIDBITS_16 2
683 #define ID_AA64MMFR2_FWB_SHIFT 40
684 #define ID_AA64MMFR2_AT_SHIFT 32
685 #define ID_AA64MMFR2_LVA_SHIFT 16
686 #define ID_AA64MMFR2_IESB_SHIFT 12
687 #define ID_AA64MMFR2_LSM_SHIFT 8
688 #define ID_AA64MMFR2_UAO_SHIFT 4
689 #define ID_AA64MMFR2_CNP_SHIFT 0
692 #define ID_AA64DFR0_PMSVER_SHIFT 32
693 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28
694 #define ID_AA64DFR0_WRPS_SHIFT 20
695 #define ID_AA64DFR0_BRPS_SHIFT 12
696 #define ID_AA64DFR0_PMUVER_SHIFT 8
697 #define ID_AA64DFR0_TRACEVER_SHIFT 4
698 #define ID_AA64DFR0_DEBUGVER_SHIFT 0
700 #define ID_AA64DFR0_PMUVER_8_1 0x4
702 #define ID_DFR0_PERFMON_SHIFT 24
704 #define ID_DFR0_PERFMON_8_1 0x4
706 #define ID_ISAR5_RDM_SHIFT 24
707 #define ID_ISAR5_CRC32_SHIFT 16
708 #define ID_ISAR5_SHA2_SHIFT 12
709 #define ID_ISAR5_SHA1_SHIFT 8
710 #define ID_ISAR5_AES_SHIFT 4
711 #define ID_ISAR5_SEVL_SHIFT 0
713 #define MVFR0_FPROUND_SHIFT 28
714 #define MVFR0_FPSHVEC_SHIFT 24
715 #define MVFR0_FPSQRT_SHIFT 20
716 #define MVFR0_FPDIVIDE_SHIFT 16
717 #define MVFR0_FPTRAP_SHIFT 12
718 #define MVFR0_FPDP_SHIFT 8
719 #define MVFR0_FPSP_SHIFT 4
720 #define MVFR0_SIMD_SHIFT 0
722 #define MVFR1_SIMDFMAC_SHIFT 28
723 #define MVFR1_FPHP_SHIFT 24
724 #define MVFR1_SIMDHP_SHIFT 20
725 #define MVFR1_SIMDSP_SHIFT 16
726 #define MVFR1_SIMDINT_SHIFT 12
727 #define MVFR1_SIMDLS_SHIFT 8
728 #define MVFR1_FPDNAN_SHIFT 4
729 #define MVFR1_FPFTZ_SHIFT 0
732 #define ID_AA64MMFR0_TGRAN4_SHIFT 28
733 #define ID_AA64MMFR0_TGRAN64_SHIFT 24
734 #define ID_AA64MMFR0_TGRAN16_SHIFT 20
736 #define ID_AA64MMFR0_TGRAN4_NI 0xf
737 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
738 #define ID_AA64MMFR0_TGRAN64_NI 0xf
739 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
740 #define ID_AA64MMFR0_TGRAN16_NI 0x0
741 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
743 #if defined(CONFIG_ARM64_4K_PAGES)
744 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT
745 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED
746 #elif defined(CONFIG_ARM64_16K_PAGES)
747 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT
748 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED
749 #elif defined(CONFIG_ARM64_64K_PAGES)
750 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT
751 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED
756 * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which
757 * are reserved by the SVE architecture for future expansion of the LEN
758 * field, with compatible semantics.
760 #define ZCR_ELx_LEN_SHIFT 0
761 #define ZCR_ELx_LEN_SIZE 9
762 #define ZCR_ELx_LEN_MASK 0x1ff
764 #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */
765 #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */
766 #define CPACR_EL1_ZEN (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)
769 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
770 #define SYS_MPIDR_SAFE_VAL (BIT(31))
774 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
775 .equ .L__reg_num_x\num, \num
777 .equ .L__reg_num_xzr, 31
779 .macro mrs_s, rt, sreg
780 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt))
783 .macro msr_s, sreg, rt
784 __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt))
789 #include <linux/build_bug.h>
790 #include <linux/types.h>
792 #define __DEFINE_MRS_MSR_S_REGNUM \
793 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \
794 " .equ .L__reg_num_x\\num, \\num\n" \
796 " .equ .L__reg_num_xzr, 31\n"
798 #define DEFINE_MRS_S \
799 __DEFINE_MRS_MSR_S_REGNUM \
800 " .macro mrs_s, rt, sreg\n" \
801 __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt)) \
804 #define DEFINE_MSR_S \
805 __DEFINE_MRS_MSR_S_REGNUM \
806 " .macro msr_s, sreg, rt\n" \
807 __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt)) \
810 #define UNDEFINE_MRS_S \
813 #define UNDEFINE_MSR_S \
816 #define __mrs_s(v, r) \
818 " mrs_s " v ", " __stringify(r) "\n" \
821 #define __msr_s(r, v) \
823 " msr_s " __stringify(r) ", " v "\n" \
827 * Unlike read_cpuid, calls to read_sysreg are never expected to be
828 * optimized away or replaced with synthetic values.
830 #define read_sysreg(r) ({ \
832 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
837 * The "Z" constraint normally means a zero immediate, but when combined with
838 * the "%x0" template means XZR.
840 #define write_sysreg(v, r) do { \
841 u64 __val = (u64)(v); \
842 asm volatile("msr " __stringify(r) ", %x0" \
847 * For registers without architectural names, or simply unsupported by
850 #define read_sysreg_s(r) ({ \
852 asm volatile(__mrs_s("%0", r) : "=r" (__val)); \
856 #define write_sysreg_s(v, r) do { \
857 u64 __val = (u64)(v); \
858 asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); \
862 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the
863 * set mask are set. Other bits are left as-is.
865 #define sysreg_clear_set(sysreg, clear, set) do { \
866 u64 __scs_val = read_sysreg(sysreg); \
867 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \
868 if (__scs_new != __scs_val) \
869 write_sysreg(__scs_new, sysreg); \
874 #endif /* __ASM_SYSREG_H */