2 * Macros for accessing system registers with older binutils.
4 * Copyright (C) 2014 ARM Ltd.
5 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #ifndef __ASM_SYSREG_H
21 #define __ASM_SYSREG_H
23 #include <asm/compiler.h>
24 #include <linux/stringify.h>
27 * ARMv8 ARM reserves the following encoding for system registers:
28 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
29 * C5.2, version:ARM DDI 0487A.f)
47 #define sys_reg(op0, op1, crn, crm, op2) \
48 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \
49 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
52 #define sys_insn sys_reg
54 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask)
55 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask)
56 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask)
57 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask)
58 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask)
60 #ifndef CONFIG_BROKEN_GAS_INST
63 // The space separator is omitted so that __emit_inst(x) can be parsed as
64 // either an assembler directive or an assembler macro argument.
65 #define __emit_inst(x) .inst(x)
67 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t"
70 #else /* CONFIG_BROKEN_GAS_INST */
72 #ifndef CONFIG_CPU_BIG_ENDIAN
73 #define __INSTR_BSWAP(x) (x)
74 #else /* CONFIG_CPU_BIG_ENDIAN */
75 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \
76 (((x) << 8) & 0x00ff0000) | \
77 (((x) >> 8) & 0x0000ff00) | \
78 (((x) >> 24) & 0x000000ff))
79 #endif /* CONFIG_CPU_BIG_ENDIAN */
82 #define __emit_inst(x) .long __INSTR_BSWAP(x)
83 #else /* __ASSEMBLY__ */
84 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t"
85 #endif /* __ASSEMBLY__ */
87 #endif /* CONFIG_BROKEN_GAS_INST */
89 #define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4)
90 #define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3)
91 #define REG_PSTATE_SSBS_IMM sys_reg(0, 3, 4, 0, 1)
93 #define SET_PSTATE_PAN(x) __emit_inst(0xd5000000 | REG_PSTATE_PAN_IMM | \
95 #define SET_PSTATE_UAO(x) __emit_inst(0xd5000000 | REG_PSTATE_UAO_IMM | \
97 #define SET_PSTATE_SSBS(x) __emit_inst(0xd5000000 | REG_PSTATE_SSBS_IMM | \
100 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
101 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
102 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
104 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2)
105 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0)
106 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2)
107 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2)
108 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2)
109 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
110 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
111 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
112 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
113 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
114 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4)
115 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
116 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
117 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
118 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
119 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
120 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
121 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
122 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
123 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
124 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
125 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
127 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
128 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
129 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
131 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0)
132 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
133 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
134 #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
135 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4)
136 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
137 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
138 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)
140 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0)
141 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)
142 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2)
143 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
144 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
145 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5)
146 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)
148 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
149 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
150 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
152 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0)
153 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1)
154 #define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4)
156 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0)
157 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1)
159 #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4)
160 #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5)
162 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
163 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
165 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
166 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
167 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
169 #define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0)
170 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
171 #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2)
173 #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
175 #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
176 #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
177 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
179 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
181 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
182 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
183 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
185 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
186 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
187 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
188 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
189 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
190 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
191 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
192 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
194 #define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0)
195 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
197 /*** Statistical Profiling Extension ***/
199 #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7)
200 #define SYS_PMSIDR_EL1_FE_SHIFT 0
201 #define SYS_PMSIDR_EL1_FT_SHIFT 1
202 #define SYS_PMSIDR_EL1_FL_SHIFT 2
203 #define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3
204 #define SYS_PMSIDR_EL1_LDS_SHIFT 4
205 #define SYS_PMSIDR_EL1_ERND_SHIFT 5
206 #define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8
207 #define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL
208 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12
209 #define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL
210 #define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16
211 #define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL
213 #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7)
214 #define SYS_PMBIDR_EL1_ALIGN_SHIFT 0
215 #define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU
216 #define SYS_PMBIDR_EL1_P_SHIFT 4
217 #define SYS_PMBIDR_EL1_F_SHIFT 5
219 /* Sampling controls */
220 #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0)
221 #define SYS_PMSCR_EL1_E0SPE_SHIFT 0
222 #define SYS_PMSCR_EL1_E1SPE_SHIFT 1
223 #define SYS_PMSCR_EL1_CX_SHIFT 3
224 #define SYS_PMSCR_EL1_PA_SHIFT 4
225 #define SYS_PMSCR_EL1_TS_SHIFT 5
226 #define SYS_PMSCR_EL1_PCT_SHIFT 6
228 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0)
229 #define SYS_PMSCR_EL2_E0HSPE_SHIFT 0
230 #define SYS_PMSCR_EL2_E2SPE_SHIFT 1
231 #define SYS_PMSCR_EL2_CX_SHIFT 3
232 #define SYS_PMSCR_EL2_PA_SHIFT 4
233 #define SYS_PMSCR_EL2_TS_SHIFT 5
234 #define SYS_PMSCR_EL2_PCT_SHIFT 6
236 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2)
238 #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3)
239 #define SYS_PMSIRR_EL1_RND_SHIFT 0
240 #define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8
241 #define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL
243 /* Filtering controls */
244 #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4)
245 #define SYS_PMSFCR_EL1_FE_SHIFT 0
246 #define SYS_PMSFCR_EL1_FT_SHIFT 1
247 #define SYS_PMSFCR_EL1_FL_SHIFT 2
248 #define SYS_PMSFCR_EL1_B_SHIFT 16
249 #define SYS_PMSFCR_EL1_LD_SHIFT 17
250 #define SYS_PMSFCR_EL1_ST_SHIFT 18
252 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5)
253 #define SYS_PMSEVFR_EL1_RES0 0x0000ffff00ff0f55UL
255 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6)
256 #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0
258 /* Buffer controls */
259 #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0)
260 #define SYS_PMBLIMITR_EL1_E_SHIFT 0
261 #define SYS_PMBLIMITR_EL1_FM_SHIFT 1
262 #define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL
263 #define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT)
265 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1)
267 /* Buffer error reporting */
268 #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3)
269 #define SYS_PMBSR_EL1_COLL_SHIFT 16
270 #define SYS_PMBSR_EL1_S_SHIFT 17
271 #define SYS_PMBSR_EL1_EA_SHIFT 18
272 #define SYS_PMBSR_EL1_DL_SHIFT 19
273 #define SYS_PMBSR_EL1_EC_SHIFT 26
274 #define SYS_PMBSR_EL1_EC_MASK 0x3fUL
276 #define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT)
277 #define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT)
278 #define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT)
280 #define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0
281 #define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL
283 #define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0
284 #define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL
286 #define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT)
288 /*** End of Statistical Profiling Extension ***/
290 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
291 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
293 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
294 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
296 #define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0)
297 #define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1)
298 #define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2)
299 #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3)
300 #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7)
302 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
303 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
305 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
306 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
307 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
308 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
309 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
310 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0)
311 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1)
312 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2)
313 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3)
314 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
315 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0)
316 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1)
317 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2)
318 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3)
319 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
320 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
321 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
322 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
323 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
324 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
325 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
326 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
327 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
328 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
329 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
330 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
331 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
333 #define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1)
334 #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4)
336 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
338 #define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1)
339 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
341 #define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0)
343 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
344 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
346 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
347 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
348 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
349 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
350 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
351 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
352 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
353 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
354 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
355 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
356 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
357 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
358 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
360 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
361 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
363 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
365 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
366 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
367 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
369 #define __PMEV_op2(n) ((n) & 0x7)
370 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
371 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
372 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
373 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
375 #define SYS_PMCCFILTR_EL0 sys_reg (3, 3, 14, 15, 7)
377 #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0)
379 #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
380 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
381 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
382 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
384 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
385 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
386 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0)
387 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1)
388 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2)
389 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
391 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
392 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0)
393 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1)
394 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2)
395 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
397 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
398 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
399 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
400 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
401 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
402 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
403 #define SYS_ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5)
404 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
406 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
407 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0)
408 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1)
409 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2)
410 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
411 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4)
412 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5)
413 #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6)
414 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7)
416 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
417 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0)
418 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1)
419 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2)
420 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
421 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4)
422 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5)
423 #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6)
424 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
426 /* Common SCTLR_ELx flags. */
427 #define SCTLR_ELx_DSSBS (1UL << 44)
428 #define SCTLR_ELx_EE (1 << 25)
429 #define SCTLR_ELx_IESB (1 << 21)
430 #define SCTLR_ELx_WXN (1 << 19)
431 #define SCTLR_ELx_I (1 << 12)
432 #define SCTLR_ELx_SA (1 << 3)
433 #define SCTLR_ELx_C (1 << 2)
434 #define SCTLR_ELx_A (1 << 1)
435 #define SCTLR_ELx_M 1
437 #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \
438 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_IESB)
440 /* SCTLR_EL2 specific flags. */
441 #define SCTLR_EL2_RES1 ((1 << 4) | (1 << 5) | (1 << 11) | (1 << 16) | \
442 (1 << 18) | (1 << 22) | (1 << 23) | (1 << 28) | \
444 #define SCTLR_EL2_RES0 ((1 << 6) | (1 << 7) | (1 << 8) | (1 << 9) | \
445 (1 << 10) | (1 << 13) | (1 << 14) | (1 << 15) | \
446 (1 << 17) | (1 << 20) | (1 << 24) | (1 << 26) | \
447 (1 << 27) | (1 << 30) | (1 << 31) | \
448 (0xffffefffUL << 32))
450 #ifdef CONFIG_CPU_BIG_ENDIAN
451 #define ENDIAN_SET_EL2 SCTLR_ELx_EE
452 #define ENDIAN_CLEAR_EL2 0
454 #define ENDIAN_SET_EL2 0
455 #define ENDIAN_CLEAR_EL2 SCTLR_ELx_EE
458 /* SCTLR_EL2 value used for the hyp-stub */
459 #define SCTLR_EL2_SET (SCTLR_ELx_IESB | ENDIAN_SET_EL2 | SCTLR_EL2_RES1)
460 #define SCTLR_EL2_CLEAR (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \
461 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_WXN | \
462 SCTLR_ELx_DSSBS | ENDIAN_CLEAR_EL2 | SCTLR_EL2_RES0)
464 #if (SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != 0xffffffffffffffff
465 #error "Inconsistent SCTLR_EL2 set/clear bits"
468 /* SCTLR_EL1 specific flags. */
469 #define SCTLR_EL1_UCI (1 << 26)
470 #define SCTLR_EL1_E0E (1 << 24)
471 #define SCTLR_EL1_SPAN (1 << 23)
472 #define SCTLR_EL1_NTWE (1 << 18)
473 #define SCTLR_EL1_NTWI (1 << 16)
474 #define SCTLR_EL1_UCT (1 << 15)
475 #define SCTLR_EL1_DZE (1 << 14)
476 #define SCTLR_EL1_UMA (1 << 9)
477 #define SCTLR_EL1_SED (1 << 8)
478 #define SCTLR_EL1_ITD (1 << 7)
479 #define SCTLR_EL1_CP15BEN (1 << 5)
480 #define SCTLR_EL1_SA0 (1 << 4)
482 #define SCTLR_EL1_RES1 ((1 << 11) | (1 << 20) | (1 << 22) | (1 << 28) | \
484 #define SCTLR_EL1_RES0 ((1 << 6) | (1 << 10) | (1 << 13) | (1 << 17) | \
485 (1 << 27) | (1 << 30) | (1 << 31) | \
486 (0xffffefffUL << 32))
488 #ifdef CONFIG_CPU_BIG_ENDIAN
489 #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE)
490 #define ENDIAN_CLEAR_EL1 0
492 #define ENDIAN_SET_EL1 0
493 #define ENDIAN_CLEAR_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE)
496 #define SCTLR_EL1_SET (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA |\
497 SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I |\
498 SCTLR_EL1_DZE | SCTLR_EL1_UCT | SCTLR_EL1_NTWI |\
499 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN |\
500 ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_RES1)
501 #define SCTLR_EL1_CLEAR (SCTLR_ELx_A | SCTLR_EL1_CP15BEN | SCTLR_EL1_ITD |\
502 SCTLR_EL1_UMA | SCTLR_ELx_WXN | ENDIAN_CLEAR_EL1 |\
503 SCTLR_ELx_DSSBS | SCTLR_EL1_RES0)
505 #if (SCTLR_EL1_SET ^ SCTLR_EL1_CLEAR) != 0xffffffffffffffff
506 #error "Inconsistent SCTLR_EL1 set/clear bits"
510 #define ID_AA64ISAR0_TS_SHIFT 52
511 #define ID_AA64ISAR0_FHM_SHIFT 48
512 #define ID_AA64ISAR0_DP_SHIFT 44
513 #define ID_AA64ISAR0_SM4_SHIFT 40
514 #define ID_AA64ISAR0_SM3_SHIFT 36
515 #define ID_AA64ISAR0_SHA3_SHIFT 32
516 #define ID_AA64ISAR0_RDM_SHIFT 28
517 #define ID_AA64ISAR0_ATOMICS_SHIFT 20
518 #define ID_AA64ISAR0_CRC32_SHIFT 16
519 #define ID_AA64ISAR0_SHA2_SHIFT 12
520 #define ID_AA64ISAR0_SHA1_SHIFT 8
521 #define ID_AA64ISAR0_AES_SHIFT 4
524 #define ID_AA64ISAR1_LRCPC_SHIFT 20
525 #define ID_AA64ISAR1_FCMA_SHIFT 16
526 #define ID_AA64ISAR1_JSCVT_SHIFT 12
527 #define ID_AA64ISAR1_DPB_SHIFT 0
530 #define ID_AA64PFR0_CSV3_SHIFT 60
531 #define ID_AA64PFR0_CSV2_SHIFT 56
532 #define ID_AA64PFR0_DIT_SHIFT 48
533 #define ID_AA64PFR0_SVE_SHIFT 32
534 #define ID_AA64PFR0_RAS_SHIFT 28
535 #define ID_AA64PFR0_GIC_SHIFT 24
536 #define ID_AA64PFR0_ASIMD_SHIFT 20
537 #define ID_AA64PFR0_FP_SHIFT 16
538 #define ID_AA64PFR0_EL3_SHIFT 12
539 #define ID_AA64PFR0_EL2_SHIFT 8
540 #define ID_AA64PFR0_EL1_SHIFT 4
541 #define ID_AA64PFR0_EL0_SHIFT 0
543 #define ID_AA64PFR0_SVE 0x1
544 #define ID_AA64PFR0_RAS_V1 0x1
545 #define ID_AA64PFR0_FP_NI 0xf
546 #define ID_AA64PFR0_FP_SUPPORTED 0x0
547 #define ID_AA64PFR0_ASIMD_NI 0xf
548 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0
549 #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1
550 #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1
551 #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2
554 #define ID_AA64PFR1_SSBS_SHIFT 4
556 #define ID_AA64PFR1_SSBS_PSTATE_NI 0
557 #define ID_AA64PFR1_SSBS_PSTATE_ONLY 1
558 #define ID_AA64PFR1_SSBS_PSTATE_INSNS 2
561 #define ID_AA64MMFR0_TGRAN4_SHIFT 28
562 #define ID_AA64MMFR0_TGRAN64_SHIFT 24
563 #define ID_AA64MMFR0_TGRAN16_SHIFT 20
564 #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16
565 #define ID_AA64MMFR0_SNSMEM_SHIFT 12
566 #define ID_AA64MMFR0_BIGENDEL_SHIFT 8
567 #define ID_AA64MMFR0_ASID_SHIFT 4
568 #define ID_AA64MMFR0_PARANGE_SHIFT 0
570 #define ID_AA64MMFR0_TGRAN4_NI 0xf
571 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
572 #define ID_AA64MMFR0_TGRAN64_NI 0xf
573 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
574 #define ID_AA64MMFR0_TGRAN16_NI 0x0
575 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
576 #define ID_AA64MMFR0_PARANGE_48 0x5
577 #define ID_AA64MMFR0_PARANGE_52 0x6
579 #ifdef CONFIG_ARM64_PA_BITS_52
580 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_52
582 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_48
586 #define ID_AA64MMFR1_PAN_SHIFT 20
587 #define ID_AA64MMFR1_LOR_SHIFT 16
588 #define ID_AA64MMFR1_HPD_SHIFT 12
589 #define ID_AA64MMFR1_VHE_SHIFT 8
590 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4
591 #define ID_AA64MMFR1_HADBS_SHIFT 0
593 #define ID_AA64MMFR1_VMIDBITS_8 0
594 #define ID_AA64MMFR1_VMIDBITS_16 2
597 #define ID_AA64MMFR2_FWB_SHIFT 40
598 #define ID_AA64MMFR2_AT_SHIFT 32
599 #define ID_AA64MMFR2_LVA_SHIFT 16
600 #define ID_AA64MMFR2_IESB_SHIFT 12
601 #define ID_AA64MMFR2_LSM_SHIFT 8
602 #define ID_AA64MMFR2_UAO_SHIFT 4
603 #define ID_AA64MMFR2_CNP_SHIFT 0
606 #define ID_AA64DFR0_PMSVER_SHIFT 32
607 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28
608 #define ID_AA64DFR0_WRPS_SHIFT 20
609 #define ID_AA64DFR0_BRPS_SHIFT 12
610 #define ID_AA64DFR0_PMUVER_SHIFT 8
611 #define ID_AA64DFR0_TRACEVER_SHIFT 4
612 #define ID_AA64DFR0_DEBUGVER_SHIFT 0
614 #define ID_ISAR5_RDM_SHIFT 24
615 #define ID_ISAR5_CRC32_SHIFT 16
616 #define ID_ISAR5_SHA2_SHIFT 12
617 #define ID_ISAR5_SHA1_SHIFT 8
618 #define ID_ISAR5_AES_SHIFT 4
619 #define ID_ISAR5_SEVL_SHIFT 0
621 #define MVFR0_FPROUND_SHIFT 28
622 #define MVFR0_FPSHVEC_SHIFT 24
623 #define MVFR0_FPSQRT_SHIFT 20
624 #define MVFR0_FPDIVIDE_SHIFT 16
625 #define MVFR0_FPTRAP_SHIFT 12
626 #define MVFR0_FPDP_SHIFT 8
627 #define MVFR0_FPSP_SHIFT 4
628 #define MVFR0_SIMD_SHIFT 0
630 #define MVFR1_SIMDFMAC_SHIFT 28
631 #define MVFR1_FPHP_SHIFT 24
632 #define MVFR1_SIMDHP_SHIFT 20
633 #define MVFR1_SIMDSP_SHIFT 16
634 #define MVFR1_SIMDINT_SHIFT 12
635 #define MVFR1_SIMDLS_SHIFT 8
636 #define MVFR1_FPDNAN_SHIFT 4
637 #define MVFR1_FPFTZ_SHIFT 0
640 #define ID_AA64MMFR0_TGRAN4_SHIFT 28
641 #define ID_AA64MMFR0_TGRAN64_SHIFT 24
642 #define ID_AA64MMFR0_TGRAN16_SHIFT 20
644 #define ID_AA64MMFR0_TGRAN4_NI 0xf
645 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
646 #define ID_AA64MMFR0_TGRAN64_NI 0xf
647 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
648 #define ID_AA64MMFR0_TGRAN16_NI 0x0
649 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
651 #if defined(CONFIG_ARM64_4K_PAGES)
652 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT
653 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED
654 #elif defined(CONFIG_ARM64_16K_PAGES)
655 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT
656 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED
657 #elif defined(CONFIG_ARM64_64K_PAGES)
658 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT
659 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED
664 * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which
665 * are reserved by the SVE architecture for future expansion of the LEN
666 * field, with compatible semantics.
668 #define ZCR_ELx_LEN_SHIFT 0
669 #define ZCR_ELx_LEN_SIZE 9
670 #define ZCR_ELx_LEN_MASK 0x1ff
672 #define CPACR_EL1_ZEN_EL1EN (1 << 16) /* enable EL1 access */
673 #define CPACR_EL1_ZEN_EL0EN (1 << 17) /* enable EL0 access, if EL1EN set */
674 #define CPACR_EL1_ZEN (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)
677 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
678 #define SYS_MPIDR_SAFE_VAL (1UL << 31)
682 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
683 .equ .L__reg_num_x\num, \num
685 .equ .L__reg_num_xzr, 31
687 .macro mrs_s, rt, sreg
688 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt))
691 .macro msr_s, sreg, rt
692 __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt))
697 #include <linux/build_bug.h>
698 #include <linux/types.h>
701 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
702 " .equ .L__reg_num_x\\num, \\num\n"
704 " .equ .L__reg_num_xzr, 31\n"
706 " .macro mrs_s, rt, sreg\n"
707 __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt))
710 " .macro msr_s, sreg, rt\n"
711 __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt))
716 * Unlike read_cpuid, calls to read_sysreg are never expected to be
717 * optimized away or replaced with synthetic values.
719 #define read_sysreg(r) ({ \
721 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
726 * The "Z" constraint normally means a zero immediate, but when combined with
727 * the "%x0" template means XZR.
729 #define write_sysreg(v, r) do { \
730 u64 __val = (u64)(v); \
731 asm volatile("msr " __stringify(r) ", %x0" \
736 * For registers without architectural names, or simply unsupported by
739 #define read_sysreg_s(r) ({ \
741 asm volatile("mrs_s %0, " __stringify(r) : "=r" (__val)); \
745 #define write_sysreg_s(v, r) do { \
746 u64 __val = (u64)(v); \
747 asm volatile("msr_s " __stringify(r) ", %x0" : : "rZ" (__val)); \
751 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the
752 * set mask are set. Other bits are left as-is.
754 #define sysreg_clear_set(sysreg, clear, set) do { \
755 u64 __scs_val = read_sysreg(sysreg); \
756 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \
757 if (__scs_new != __scs_val) \
758 write_sysreg(__scs_new, sysreg); \
763 #endif /* __ASM_SYSREG_H */