2 * Macros for accessing system registers with older binutils.
4 * Copyright (C) 2014 ARM Ltd.
5 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #ifndef __ASM_SYSREG_H
21 #define __ASM_SYSREG_H
23 #include <asm/compiler.h>
24 #include <linux/stringify.h>
26 #include <asm/opcodes.h>
29 * ARMv8 ARM reserves the following encoding for system registers:
30 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
31 * C5.2, version:ARM DDI 0487A.f)
38 #define sys_reg(op0, op1, crn, crm, op2) \
39 ((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5))
41 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
42 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
43 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
45 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0)
46 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
47 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
48 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4)
49 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
50 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
51 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)
53 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0)
54 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)
55 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2)
56 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
57 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
58 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5)
59 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)
61 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
62 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
63 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
65 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0)
66 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1)
68 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0)
69 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1)
71 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
72 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
74 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
75 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
76 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
78 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
79 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
80 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
82 #define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4)
83 #define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3)
85 #define SET_PSTATE_PAN(x) __inst_arm(0xd5000000 | REG_PSTATE_PAN_IMM |\
87 #define SET_PSTATE_UAO(x) __inst_arm(0xd5000000 | REG_PSTATE_UAO_IMM |\
90 /* Common SCTLR_ELx flags. */
91 #define SCTLR_ELx_EE (1 << 25)
92 #define SCTLR_ELx_WXN (1 << 19)
93 #define SCTLR_ELx_I (1 << 12)
94 #define SCTLR_ELx_SA (1 << 3)
95 #define SCTLR_ELx_C (1 << 2)
96 #define SCTLR_ELx_A (1 << 1)
99 #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \
100 SCTLR_ELx_SA | SCTLR_ELx_I)
102 /* SCTLR_EL2 specific flags. */
103 #define SCTLR_EL2_RES1 ((1 << 4) | (1 << 5) | (1 << 11) | (1 << 16) | \
104 (1 << 18) | (1 << 22) | (1 << 23) | (1 << 28) | \
106 #define SCTLR_EL2_RES0 ((1 << 6) | (1 << 7) | (1 << 8) | (1 << 9) | \
107 (1 << 10) | (1 << 13) | (1 << 14) | (1 << 15) | \
108 (1 << 17) | (1 << 20) | (1 << 21) | (1 << 24) | \
109 (1 << 26) | (1 << 27) | (1 << 30) | (1 << 31))
111 #ifdef CONFIG_CPU_BIG_ENDIAN
112 #define ENDIAN_SET_EL2 SCTLR_ELx_EE
113 #define ENDIAN_CLEAR_EL2 0
115 #define ENDIAN_SET_EL2 0
116 #define ENDIAN_CLEAR_EL2 SCTLR_ELx_EE
119 /* SCTLR_EL2 value used for the hyp-stub */
120 #define SCTLR_EL2_SET (ENDIAN_SET_EL2 | SCTLR_EL2_RES1)
121 #define SCTLR_EL2_CLEAR (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \
122 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_WXN | \
123 ENDIAN_CLEAR_EL2 | SCTLR_EL2_RES0)
125 /* Check all the bits are accounted for */
126 #define SCTLR_EL2_BUILD_BUG_ON_MISSING_BITS BUILD_BUG_ON((SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != ~0)
129 /* SCTLR_EL1 specific flags. */
130 #define SCTLR_EL1_UCI (1 << 26)
131 #define SCTLR_EL1_E0E (1 << 24)
132 #define SCTLR_EL1_SPAN (1 << 23)
133 #define SCTLR_EL1_NTWE (1 << 18)
134 #define SCTLR_EL1_NTWI (1 << 16)
135 #define SCTLR_EL1_UCT (1 << 15)
136 #define SCTLR_EL1_DZE (1 << 14)
137 #define SCTLR_EL1_UMA (1 << 9)
138 #define SCTLR_EL1_SED (1 << 8)
139 #define SCTLR_EL1_ITD (1 << 7)
140 #define SCTLR_EL1_CP15BEN (1 << 5)
141 #define SCTLR_EL1_SA0 (1 << 4)
143 #define SCTLR_EL1_RES1 ((1 << 11) | (1 << 20) | (1 << 22) | (1 << 28) | \
145 #define SCTLR_EL1_RES0 ((1 << 6) | (1 << 10) | (1 << 13) | (1 << 17) | \
146 (1 << 21) | (1 << 27) | (1 << 30) | (1 << 31))
148 #ifdef CONFIG_CPU_BIG_ENDIAN
149 #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE)
150 #define ENDIAN_CLEAR_EL1 0
152 #define ENDIAN_SET_EL1 0
153 #define ENDIAN_CLEAR_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE)
156 #define SCTLR_EL1_SET (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA |\
157 SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I |\
158 SCTLR_EL1_DZE | SCTLR_EL1_UCT | SCTLR_EL1_NTWI |\
159 SCTLR_EL1_NTWE | SCTLR_EL1_SPAN | ENDIAN_SET_EL1 |\
160 SCTLR_EL1_UCI | SCTLR_EL1_RES1)
161 #define SCTLR_EL1_CLEAR (SCTLR_ELx_A | SCTLR_EL1_CP15BEN | SCTLR_EL1_ITD |\
162 SCTLR_EL1_UMA | SCTLR_ELx_WXN | ENDIAN_CLEAR_EL1 |\
165 /* Check all the bits are accounted for */
166 #define SCTLR_EL1_BUILD_BUG_ON_MISSING_BITS BUILD_BUG_ON((SCTLR_EL1_SET ^ SCTLR_EL1_CLEAR) != ~0)
169 #define ID_AA64ISAR0_RDM_SHIFT 28
170 #define ID_AA64ISAR0_ATOMICS_SHIFT 20
171 #define ID_AA64ISAR0_CRC32_SHIFT 16
172 #define ID_AA64ISAR0_SHA2_SHIFT 12
173 #define ID_AA64ISAR0_SHA1_SHIFT 8
174 #define ID_AA64ISAR0_AES_SHIFT 4
177 #define ID_AA64PFR0_CSV3_SHIFT 60
178 #define ID_AA64PFR0_CSV2_SHIFT 56
179 #define ID_AA64PFR0_SVE_SHIFT 32
180 #define ID_AA64PFR0_GIC_SHIFT 24
181 #define ID_AA64PFR0_ASIMD_SHIFT 20
182 #define ID_AA64PFR0_FP_SHIFT 16
183 #define ID_AA64PFR0_EL3_SHIFT 12
184 #define ID_AA64PFR0_EL2_SHIFT 8
185 #define ID_AA64PFR0_EL1_SHIFT 4
186 #define ID_AA64PFR0_EL0_SHIFT 0
188 #define ID_AA64PFR0_FP_NI 0xf
189 #define ID_AA64PFR0_FP_SUPPORTED 0x0
190 #define ID_AA64PFR0_ASIMD_NI 0xf
191 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0
192 #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1
193 #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1
194 #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2
197 #define ID_AA64MMFR0_TGRAN4_SHIFT 28
198 #define ID_AA64MMFR0_TGRAN64_SHIFT 24
199 #define ID_AA64MMFR0_TGRAN16_SHIFT 20
200 #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16
201 #define ID_AA64MMFR0_SNSMEM_SHIFT 12
202 #define ID_AA64MMFR0_BIGENDEL_SHIFT 8
203 #define ID_AA64MMFR0_ASID_SHIFT 4
204 #define ID_AA64MMFR0_PARANGE_SHIFT 0
206 #define ID_AA64MMFR0_TGRAN4_NI 0xf
207 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
208 #define ID_AA64MMFR0_TGRAN64_NI 0xf
209 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
210 #define ID_AA64MMFR0_TGRAN16_NI 0x0
211 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
214 #define ID_AA64MMFR1_PAN_SHIFT 20
215 #define ID_AA64MMFR1_LOR_SHIFT 16
216 #define ID_AA64MMFR1_HPD_SHIFT 12
217 #define ID_AA64MMFR1_VHE_SHIFT 8
218 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4
219 #define ID_AA64MMFR1_HADBS_SHIFT 0
221 #define ID_AA64MMFR1_VMIDBITS_8 0
222 #define ID_AA64MMFR1_VMIDBITS_16 2
225 #define ID_AA64MMFR2_LVA_SHIFT 16
226 #define ID_AA64MMFR2_IESB_SHIFT 12
227 #define ID_AA64MMFR2_LSM_SHIFT 8
228 #define ID_AA64MMFR2_UAO_SHIFT 4
229 #define ID_AA64MMFR2_CNP_SHIFT 0
232 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28
233 #define ID_AA64DFR0_WRPS_SHIFT 20
234 #define ID_AA64DFR0_BRPS_SHIFT 12
235 #define ID_AA64DFR0_PMUVER_SHIFT 8
236 #define ID_AA64DFR0_TRACEVER_SHIFT 4
237 #define ID_AA64DFR0_DEBUGVER_SHIFT 0
239 #define ID_ISAR5_RDM_SHIFT 24
240 #define ID_ISAR5_CRC32_SHIFT 16
241 #define ID_ISAR5_SHA2_SHIFT 12
242 #define ID_ISAR5_SHA1_SHIFT 8
243 #define ID_ISAR5_AES_SHIFT 4
244 #define ID_ISAR5_SEVL_SHIFT 0
246 #define MVFR0_FPROUND_SHIFT 28
247 #define MVFR0_FPSHVEC_SHIFT 24
248 #define MVFR0_FPSQRT_SHIFT 20
249 #define MVFR0_FPDIVIDE_SHIFT 16
250 #define MVFR0_FPTRAP_SHIFT 12
251 #define MVFR0_FPDP_SHIFT 8
252 #define MVFR0_FPSP_SHIFT 4
253 #define MVFR0_SIMD_SHIFT 0
255 #define MVFR1_SIMDFMAC_SHIFT 28
256 #define MVFR1_FPHP_SHIFT 24
257 #define MVFR1_SIMDHP_SHIFT 20
258 #define MVFR1_SIMDSP_SHIFT 16
259 #define MVFR1_SIMDINT_SHIFT 12
260 #define MVFR1_SIMDLS_SHIFT 8
261 #define MVFR1_FPDNAN_SHIFT 4
262 #define MVFR1_FPFTZ_SHIFT 0
265 #define ID_AA64MMFR0_TGRAN4_SHIFT 28
266 #define ID_AA64MMFR0_TGRAN64_SHIFT 24
267 #define ID_AA64MMFR0_TGRAN16_SHIFT 20
269 #define ID_AA64MMFR0_TGRAN4_NI 0xf
270 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
271 #define ID_AA64MMFR0_TGRAN64_NI 0xf
272 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
273 #define ID_AA64MMFR0_TGRAN16_NI 0x0
274 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
276 #if defined(CONFIG_ARM64_4K_PAGES)
277 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT
278 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED
279 #elif defined(CONFIG_ARM64_16K_PAGES)
280 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT
281 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED
282 #elif defined(CONFIG_ARM64_64K_PAGES)
283 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT
284 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED
289 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
290 .equ .L__reg_num_x\num, \num
292 .equ .L__reg_num_xzr, 31
294 .macro mrs_s, rt, sreg
295 .inst 0xd5200000|(\sreg)|(.L__reg_num_\rt)
298 .macro msr_s, sreg, rt
299 .inst 0xd5000000|(\sreg)|(.L__reg_num_\rt)
304 #include <linux/build_bug.h>
305 #include <linux/types.h>
308 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
309 " .equ .L__reg_num_x\\num, \\num\n"
311 " .equ .L__reg_num_xzr, 31\n"
313 " .macro mrs_s, rt, sreg\n"
314 " .inst 0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n"
317 " .macro msr_s, sreg, rt\n"
318 " .inst 0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n"
323 * Unlike read_cpuid, calls to read_sysreg are never expected to be
324 * optimized away or replaced with synthetic values.
326 #define read_sysreg(r) ({ \
328 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
333 * The "Z" constraint normally means a zero immediate, but when combined with
334 * the "%x0" template means XZR.
336 #define write_sysreg(v, r) do { \
337 u64 __val = (u64)v; \
338 asm volatile("msr " __stringify(r) ", %x0" \
343 * For registers without architectural names, or simply unsupported by
346 #define read_sysreg_s(r) ({ \
348 asm volatile("mrs_s %0, " __stringify(r) : "=r" (__val)); \
352 #define write_sysreg_s(v, r) do { \
353 u64 __val = (u64)v; \
354 asm volatile("msr_s " __stringify(r) ", %x0" : : "rZ" (__val)); \
357 static inline void config_sctlr_el1(u32 clear, u32 set)
361 SCTLR_EL2_BUILD_BUG_ON_MISSING_BITS;
362 SCTLR_EL1_BUILD_BUG_ON_MISSING_BITS;
364 val = read_sysreg(sctlr_el1);
367 write_sysreg(val, sctlr_el1);
372 #endif /* __ASM_SYSREG_H */