arch/arm64/include/asm/sysreg.h

   1 /*
   2  * Macros for accessing system registers with older binutils.
   3  *
   4  * Copyright (C) 2014 ARM Ltd.
   5  * Author: Catalin Marinas <catalin.marinas@arm.com>
   6  *
   7  * This program is free software: you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef __ASM_SYSREG_H
  21 #define __ASM_SYSREG_H
  22
  23 #include <asm/compiler.h>
  24 #include <linux/stringify.h>
  25
  26 #include <asm/opcodes.h>
  27
  28 /*
  29  * ARMv8 ARM reserves the following encoding for system registers:
  30  * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
  31  *  C5.2, version:ARM DDI 0487A.f)
  32  *      [20-19] : Op0
  33  *      [18-16] : Op1
  34  *      [15-12] : CRn
  35  *      [11-8]  : CRm
  36  *      [7-5]   : Op2
  37  */
  38 #define sys_reg(op0, op1, crn, crm, op2) \
  39         ((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5))
  40
  41 #define SYS_MIDR_EL1                    sys_reg(3, 0, 0, 0, 0)
  42 #define SYS_MPIDR_EL1                   sys_reg(3, 0, 0, 0, 5)
  43 #define SYS_REVIDR_EL1                  sys_reg(3, 0, 0, 0, 6)
  44
  45 #define SYS_ID_PFR0_EL1                 sys_reg(3, 0, 0, 1, 0)
  46 #define SYS_ID_PFR1_EL1                 sys_reg(3, 0, 0, 1, 1)
  47 #define SYS_ID_DFR0_EL1                 sys_reg(3, 0, 0, 1, 2)
  48 #define SYS_ID_MMFR0_EL1                sys_reg(3, 0, 0, 1, 4)
  49 #define SYS_ID_MMFR1_EL1                sys_reg(3, 0, 0, 1, 5)
  50 #define SYS_ID_MMFR2_EL1                sys_reg(3, 0, 0, 1, 6)
  51 #define SYS_ID_MMFR3_EL1                sys_reg(3, 0, 0, 1, 7)
  52
  53 #define SYS_ID_ISAR0_EL1                sys_reg(3, 0, 0, 2, 0)
  54 #define SYS_ID_ISAR1_EL1                sys_reg(3, 0, 0, 2, 1)
  55 #define SYS_ID_ISAR2_EL1                sys_reg(3, 0, 0, 2, 2)
  56 #define SYS_ID_ISAR3_EL1                sys_reg(3, 0, 0, 2, 3)
  57 #define SYS_ID_ISAR4_EL1                sys_reg(3, 0, 0, 2, 4)
  58 #define SYS_ID_ISAR5_EL1                sys_reg(3, 0, 0, 2, 5)
  59 #define SYS_ID_MMFR4_EL1                sys_reg(3, 0, 0, 2, 6)
  60
  61 #define SYS_MVFR0_EL1                   sys_reg(3, 0, 0, 3, 0)
  62 #define SYS_MVFR1_EL1                   sys_reg(3, 0, 0, 3, 1)
  63 #define SYS_MVFR2_EL1                   sys_reg(3, 0, 0, 3, 2)
  64
  65 #define SYS_ID_AA64PFR0_EL1             sys_reg(3, 0, 0, 4, 0)
  66 #define SYS_ID_AA64PFR1_EL1             sys_reg(3, 0, 0, 4, 1)
  67
  68 #define SYS_ID_AA64DFR0_EL1             sys_reg(3, 0, 0, 5, 0)
  69 #define SYS_ID_AA64DFR1_EL1             sys_reg(3, 0, 0, 5, 1)
  70
  71 #define SYS_ID_AA64ISAR0_EL1            sys_reg(3, 0, 0, 6, 0)
  72 #define SYS_ID_AA64ISAR1_EL1            sys_reg(3, 0, 0, 6, 1)
  73 #define SYS_ID_AA64ISAR2_EL1            sys_reg(3, 0, 0, 6, 2)
  74
  75 #define SYS_ID_AA64MMFR0_EL1            sys_reg(3, 0, 0, 7, 0)
  76 #define SYS_ID_AA64MMFR1_EL1            sys_reg(3, 0, 0, 7, 1)
  77 #define SYS_ID_AA64MMFR2_EL1            sys_reg(3, 0, 0, 7, 2)
  78
  79 #define SYS_CNTFRQ_EL0                  sys_reg(3, 3, 14, 0, 0)
  80 #define SYS_CTR_EL0                     sys_reg(3, 3, 0, 0, 1)
  81 #define SYS_DCZID_EL0                   sys_reg(3, 3, 0, 0, 7)
  82
  83 #define REG_PSTATE_PAN_IMM              sys_reg(0, 0, 4, 0, 4)
  84 #define REG_PSTATE_UAO_IMM              sys_reg(0, 0, 4, 0, 3)
  85
  86 #define SET_PSTATE_PAN(x) __inst_arm(0xd5000000 | REG_PSTATE_PAN_IMM |\
  87                                      (!!x)<<8 | 0x1f)
  88 #define SET_PSTATE_UAO(x) __inst_arm(0xd5000000 | REG_PSTATE_UAO_IMM |\
  89                                      (!!x)<<8 | 0x1f)
  90
  91 /* Common SCTLR_ELx flags. */
  92 #define SCTLR_ELx_EE    (1 << 25)
  93 #define SCTLR_ELx_WXN   (1 << 19)
  94 #define SCTLR_ELx_I     (1 << 12)
  95 #define SCTLR_ELx_SA    (1 << 3)
  96 #define SCTLR_ELx_C     (1 << 2)
  97 #define SCTLR_ELx_A     (1 << 1)
  98 #define SCTLR_ELx_M     1
  99
 100 #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \
 101                          SCTLR_ELx_SA | SCTLR_ELx_I)
 102
 103 /* SCTLR_EL2 specific flags. */
 104 #define SCTLR_EL2_RES1  ((1 << 4)  | (1 << 5)  | (1 << 11) | (1 << 16) | \
 105                          (1 << 18) | (1 << 22) | (1 << 23) | (1 << 28) | \
 106                          (1 << 29))
 107 #define SCTLR_EL2_RES0  ((1 << 6)  | (1 << 7)  | (1 << 8)  | (1 << 9)  | \
 108                          (1 << 10) | (1 << 13) | (1 << 14) | (1 << 15) | \
 109                          (1 << 17) | (1 << 20) | (1 << 21) | (1 << 24) | \
 110                          (1 << 26) | (1 << 27) | (1 << 30) | (1 << 31))
 111
 112 #ifdef CONFIG_CPU_BIG_ENDIAN
 113 #define ENDIAN_SET_EL2          SCTLR_ELx_EE
 114 #define ENDIAN_CLEAR_EL2        0
 115 #else
 116 #define ENDIAN_SET_EL2          0
 117 #define ENDIAN_CLEAR_EL2        SCTLR_ELx_EE
 118 #endif
 119
 120 /* SCTLR_EL2 value used for the hyp-stub */
 121 #define SCTLR_EL2_SET   (ENDIAN_SET_EL2   | SCTLR_EL2_RES1)
 122 #define SCTLR_EL2_CLEAR (SCTLR_ELx_M      | SCTLR_ELx_A    | SCTLR_ELx_C   | \
 123                          SCTLR_ELx_SA     | SCTLR_ELx_I    | SCTLR_ELx_WXN | \
 124                          ENDIAN_CLEAR_EL2 | SCTLR_EL2_RES0)
 125
 126 /* Check all the bits are accounted for */
 127 #define SCTLR_EL2_BUILD_BUG_ON_MISSING_BITS     BUILD_BUG_ON((SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != ~0)
 128
 129
 130 /* SCTLR_EL1 specific flags. */
 131 #define SCTLR_EL1_UCI           (1 << 26)
 132 #define SCTLR_EL1_E0E           (1 << 24)
 133 #define SCTLR_EL1_SPAN          (1 << 23)
 134 #define SCTLR_EL1_NTWE          (1 << 18)
 135 #define SCTLR_EL1_NTWI          (1 << 16)
 136 #define SCTLR_EL1_UCT           (1 << 15)
 137 #define SCTLR_EL1_DZE           (1 << 14)
 138 #define SCTLR_EL1_UMA           (1 << 9)
 139 #define SCTLR_EL1_SED           (1 << 8)
 140 #define SCTLR_EL1_ITD           (1 << 7)
 141 #define SCTLR_EL1_CP15BEN       (1 << 5)
 142 #define SCTLR_EL1_SA0           (1 << 4)
 143
 144 #define SCTLR_EL1_RES1  ((1 << 11) | (1 << 20) | (1 << 22) | (1 << 28) | \
 145                          (1 << 29))
 146 #define SCTLR_EL1_RES0  ((1 << 6)  | (1 << 10) | (1 << 13) | (1 << 17) | \
 147                          (1 << 21) | (1 << 27) | (1 << 30) | (1 << 31))
 148
 149 #ifdef CONFIG_CPU_BIG_ENDIAN
 150 #define ENDIAN_SET_EL1          (SCTLR_EL1_E0E | SCTLR_ELx_EE)
 151 #define ENDIAN_CLEAR_EL1        0
 152 #else
 153 #define ENDIAN_SET_EL1          0
 154 #define ENDIAN_CLEAR_EL1        (SCTLR_EL1_E0E | SCTLR_ELx_EE)
 155 #endif
 156
 157 #define SCTLR_EL1_SET   (SCTLR_ELx_M    | SCTLR_ELx_C    | SCTLR_ELx_SA   |\
 158                          SCTLR_EL1_SA0  | SCTLR_EL1_SED  | SCTLR_ELx_I    |\
 159                          SCTLR_EL1_DZE  | SCTLR_EL1_UCT  | SCTLR_EL1_NTWI |\
 160                          SCTLR_EL1_NTWE | SCTLR_EL1_SPAN | ENDIAN_SET_EL1 |\
 161                          SCTLR_EL1_UCI  | SCTLR_EL1_RES1)
 162 #define SCTLR_EL1_CLEAR (SCTLR_ELx_A   | SCTLR_EL1_CP15BEN | SCTLR_EL1_ITD    |\
 163                          SCTLR_EL1_UMA | SCTLR_ELx_WXN     | ENDIAN_CLEAR_EL1 |\
 164                          SCTLR_EL1_RES0)
 165
 166 /* Check all the bits are accounted for */
 167 #define SCTLR_EL1_BUILD_BUG_ON_MISSING_BITS     BUILD_BUG_ON((SCTLR_EL1_SET ^ SCTLR_EL1_CLEAR) != ~0)
 168
 169 /* id_aa64isar0 */
 170 #define ID_AA64ISAR0_RDM_SHIFT          28
 171 #define ID_AA64ISAR0_ATOMICS_SHIFT      20
 172 #define ID_AA64ISAR0_CRC32_SHIFT        16
 173 #define ID_AA64ISAR0_SHA2_SHIFT         12
 174 #define ID_AA64ISAR0_SHA1_SHIFT         8
 175 #define ID_AA64ISAR0_AES_SHIFT          4
 176
 177 /* id_aa64isar2 */
 178 #define ID_AA64ISAR2_CLEARBHB_SHIFT     28
 179
 180 /* id_aa64pfr0 */
 181 #define ID_AA64PFR0_CSV3_SHIFT          60
 182 #define ID_AA64PFR0_CSV2_SHIFT          56
 183 #define ID_AA64PFR0_SVE_SHIFT           32
 184 #define ID_AA64PFR0_GIC_SHIFT           24
 185 #define ID_AA64PFR0_ASIMD_SHIFT         20
 186 #define ID_AA64PFR0_FP_SHIFT            16
 187 #define ID_AA64PFR0_EL3_SHIFT           12
 188 #define ID_AA64PFR0_EL2_SHIFT           8
 189 #define ID_AA64PFR0_EL1_SHIFT           4
 190 #define ID_AA64PFR0_EL0_SHIFT           0
 191
 192 #define ID_AA64PFR0_FP_NI               0xf
 193 #define ID_AA64PFR0_FP_SUPPORTED        0x0
 194 #define ID_AA64PFR0_ASIMD_NI            0xf
 195 #define ID_AA64PFR0_ASIMD_SUPPORTED     0x0
 196 #define ID_AA64PFR0_EL1_64BIT_ONLY      0x1
 197 #define ID_AA64PFR0_EL0_64BIT_ONLY      0x1
 198 #define ID_AA64PFR0_EL0_32BIT_64BIT     0x2
 199
 200 /* id_aa64mmfr0 */
 201 #define ID_AA64MMFR0_TGRAN4_SHIFT       28
 202 #define ID_AA64MMFR0_TGRAN64_SHIFT      24
 203 #define ID_AA64MMFR0_TGRAN16_SHIFT      20
 204 #define ID_AA64MMFR0_BIGENDEL0_SHIFT    16
 205 #define ID_AA64MMFR0_SNSMEM_SHIFT       12
 206 #define ID_AA64MMFR0_BIGENDEL_SHIFT     8
 207 #define ID_AA64MMFR0_ASID_SHIFT         4
 208 #define ID_AA64MMFR0_PARANGE_SHIFT      0
 209
 210 #define ID_AA64MMFR0_TGRAN4_NI          0xf
 211 #define ID_AA64MMFR0_TGRAN4_SUPPORTED   0x0
 212 #define ID_AA64MMFR0_TGRAN64_NI         0xf
 213 #define ID_AA64MMFR0_TGRAN64_SUPPORTED  0x0
 214 #define ID_AA64MMFR0_TGRAN16_NI         0x0
 215 #define ID_AA64MMFR0_TGRAN16_SUPPORTED  0x1
 216
 217 /* id_aa64mmfr1 */
 218 #define ID_AA64MMFR1_ECBHB_SHIFT        60
 219 #define ID_AA64MMFR1_PAN_SHIFT          20
 220 #define ID_AA64MMFR1_LOR_SHIFT          16
 221 #define ID_AA64MMFR1_HPD_SHIFT          12
 222 #define ID_AA64MMFR1_VHE_SHIFT          8
 223 #define ID_AA64MMFR1_VMIDBITS_SHIFT     4
 224 #define ID_AA64MMFR1_HADBS_SHIFT        0
 225
 226 #define ID_AA64MMFR1_VMIDBITS_8         0
 227 #define ID_AA64MMFR1_VMIDBITS_16        2
 228
 229 /* id_aa64mmfr2 */
 230 #define ID_AA64MMFR2_LVA_SHIFT          16
 231 #define ID_AA64MMFR2_IESB_SHIFT         12
 232 #define ID_AA64MMFR2_LSM_SHIFT          8
 233 #define ID_AA64MMFR2_UAO_SHIFT          4
 234 #define ID_AA64MMFR2_CNP_SHIFT          0
 235
 236 /* id_aa64dfr0 */
 237 #define ID_AA64DFR0_CTX_CMPS_SHIFT      28
 238 #define ID_AA64DFR0_WRPS_SHIFT          20
 239 #define ID_AA64DFR0_BRPS_SHIFT          12
 240 #define ID_AA64DFR0_PMUVER_SHIFT        8
 241 #define ID_AA64DFR0_TRACEVER_SHIFT      4
 242 #define ID_AA64DFR0_DEBUGVER_SHIFT      0
 243
 244 #define ID_ISAR5_RDM_SHIFT              24
 245 #define ID_ISAR5_CRC32_SHIFT            16
 246 #define ID_ISAR5_SHA2_SHIFT             12
 247 #define ID_ISAR5_SHA1_SHIFT             8
 248 #define ID_ISAR5_AES_SHIFT              4
 249 #define ID_ISAR5_SEVL_SHIFT             0
 250
 251 #define MVFR0_FPROUND_SHIFT             28
 252 #define MVFR0_FPSHVEC_SHIFT             24
 253 #define MVFR0_FPSQRT_SHIFT              20
 254 #define MVFR0_FPDIVIDE_SHIFT            16
 255 #define MVFR0_FPTRAP_SHIFT              12
 256 #define MVFR0_FPDP_SHIFT                8
 257 #define MVFR0_FPSP_SHIFT                4
 258 #define MVFR0_SIMD_SHIFT                0
 259
 260 #define MVFR1_SIMDFMAC_SHIFT            28
 261 #define MVFR1_FPHP_SHIFT                24
 262 #define MVFR1_SIMDHP_SHIFT              20
 263 #define MVFR1_SIMDSP_SHIFT              16
 264 #define MVFR1_SIMDINT_SHIFT             12
 265 #define MVFR1_SIMDLS_SHIFT              8
 266 #define MVFR1_FPDNAN_SHIFT              4
 267 #define MVFR1_FPFTZ_SHIFT               0
 268
 269
 270 #define ID_AA64MMFR0_TGRAN4_SHIFT       28
 271 #define ID_AA64MMFR0_TGRAN64_SHIFT      24
 272 #define ID_AA64MMFR0_TGRAN16_SHIFT      20
 273
 274 #define ID_AA64MMFR0_TGRAN4_NI          0xf
 275 #define ID_AA64MMFR0_TGRAN4_SUPPORTED   0x0
 276 #define ID_AA64MMFR0_TGRAN64_NI         0xf
 277 #define ID_AA64MMFR0_TGRAN64_SUPPORTED  0x0
 278 #define ID_AA64MMFR0_TGRAN16_NI         0x0
 279 #define ID_AA64MMFR0_TGRAN16_SUPPORTED  0x1
 280
 281 #if defined(CONFIG_ARM64_4K_PAGES)
 282 #define ID_AA64MMFR0_TGRAN_SHIFT        ID_AA64MMFR0_TGRAN4_SHIFT
 283 #define ID_AA64MMFR0_TGRAN_SUPPORTED    ID_AA64MMFR0_TGRAN4_SUPPORTED
 284 #elif defined(CONFIG_ARM64_16K_PAGES)
 285 #define ID_AA64MMFR0_TGRAN_SHIFT        ID_AA64MMFR0_TGRAN16_SHIFT
 286 #define ID_AA64MMFR0_TGRAN_SUPPORTED    ID_AA64MMFR0_TGRAN16_SUPPORTED
 287 #elif defined(CONFIG_ARM64_64K_PAGES)
 288 #define ID_AA64MMFR0_TGRAN_SHIFT        ID_AA64MMFR0_TGRAN64_SHIFT
 289 #define ID_AA64MMFR0_TGRAN_SUPPORTED    ID_AA64MMFR0_TGRAN64_SUPPORTED
 290 #endif
 291
 292 #ifdef __ASSEMBLY__
 293
 294         .irp    num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
 295         .equ    .L__reg_num_x\num, \num
 296         .endr
 297         .equ    .L__reg_num_xzr, 31
 298
 299         .macro  mrs_s, rt, sreg
 300         .inst   0xd5200000|(\sreg)|(.L__reg_num_\rt)
 301         .endm
 302
 303         .macro  msr_s, sreg, rt
 304         .inst   0xd5000000|(\sreg)|(.L__reg_num_\rt)
 305         .endm
 306
 307 #else
 308
 309 #include <linux/build_bug.h>
 310 #include <linux/types.h>
 311
 312 asm(
 313 "       .irp    num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
 314 "       .equ    .L__reg_num_x\\num, \\num\n"
 315 "       .endr\n"
 316 "       .equ    .L__reg_num_xzr, 31\n"
 317 "\n"
 318 "       .macro  mrs_s, rt, sreg\n"
 319 "       .inst   0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n"
 320 "       .endm\n"
 321 "\n"
 322 "       .macro  msr_s, sreg, rt\n"
 323 "       .inst   0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n"
 324 "       .endm\n"
 325 );
 326
 327 /*
 328  * Unlike read_cpuid, calls to read_sysreg are never expected to be
 329  * optimized away or replaced with synthetic values.
 330  */
 331 #define read_sysreg(r) ({                                       \
 332         u64 __val;                                              \
 333         asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
 334         __val;                                                  \
 335 })
 336
 337 /*
 338  * The "Z" constraint normally means a zero immediate, but when combined with
 339  * the "%x0" template means XZR.
 340  */
 341 #define write_sysreg(v, r) do {                                 \
 342         u64 __val = (u64)v;                                     \
 343         asm volatile("msr " __stringify(r) ", %x0"              \
 344                      : : "rZ" (__val));                         \
 345 } while (0)
 346
 347 /*
 348  * For registers without architectural names, or simply unsupported by
 349  * GAS.
 350  */
 351 #define read_sysreg_s(r) ({                                             \
 352         u64 __val;                                                      \
 353         asm volatile("mrs_s %0, " __stringify(r) : "=r" (__val));       \
 354         __val;                                                          \
 355 })
 356
 357 #define write_sysreg_s(v, r) do {                                       \
 358         u64 __val = (u64)v;                                             \
 359         asm volatile("msr_s " __stringify(r) ", %x0" : : "rZ" (__val)); \
 360 } while (0)
 361
 362 static inline void config_sctlr_el1(u32 clear, u32 set)
 363 {
 364         u32 val;
 365
 366         SCTLR_EL2_BUILD_BUG_ON_MISSING_BITS;
 367         SCTLR_EL1_BUILD_BUG_ON_MISSING_BITS;
 368
 369         val = read_sysreg(sctlr_el1);
 370         val &= ~clear;
 371         val |= set;
 372         write_sysreg(val, sctlr_el1);
 373 }
 374
 375 #endif
 376
 377 #endif  /* __ASM_SYSREG_H */