2 * Macros for accessing system registers with older binutils.
4 * Copyright (C) 2014 ARM Ltd.
5 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #ifndef __ASM_SYSREG_H
21 #define __ASM_SYSREG_H
23 #include <asm/compiler.h>
24 #include <linux/stringify.h>
27 * ARMv8 ARM reserves the following encoding for system registers:
28 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
29 * C5.2, version:ARM DDI 0487A.f)
47 #define sys_reg(op0, op1, crn, crm, op2) \
48 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \
49 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
52 #define sys_insn sys_reg
54 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask)
55 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask)
56 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask)
57 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask)
58 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask)
60 #ifndef CONFIG_BROKEN_GAS_INST
63 // The space separator is omitted so that __emit_inst(x) can be parsed as
64 // either an assembler directive or an assembler macro argument.
65 #define __emit_inst(x) .inst(x)
67 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t"
70 #else /* CONFIG_BROKEN_GAS_INST */
72 #ifndef CONFIG_CPU_BIG_ENDIAN
73 #define __INSTR_BSWAP(x) (x)
74 #else /* CONFIG_CPU_BIG_ENDIAN */
75 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \
76 (((x) << 8) & 0x00ff0000) | \
77 (((x) >> 8) & 0x0000ff00) | \
78 (((x) >> 24) & 0x000000ff))
79 #endif /* CONFIG_CPU_BIG_ENDIAN */
82 #define __emit_inst(x) .long __INSTR_BSWAP(x)
83 #else /* __ASSEMBLY__ */
84 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t"
85 #endif /* __ASSEMBLY__ */
87 #endif /* CONFIG_BROKEN_GAS_INST */
89 #define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4)
90 #define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3)
91 #define REG_PSTATE_SSBS_IMM sys_reg(0, 3, 4, 0, 1)
93 #define SET_PSTATE_PAN(x) __emit_inst(0xd5000000 | REG_PSTATE_PAN_IMM | \
95 #define SET_PSTATE_UAO(x) __emit_inst(0xd5000000 | REG_PSTATE_UAO_IMM | \
97 #define SET_PSTATE_SSBS(x) __emit_inst(0xd5000000 | REG_PSTATE_SSBS_IMM | \
100 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
101 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
102 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
104 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2)
105 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0)
106 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2)
107 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2)
108 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2)
109 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
110 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
111 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
112 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
113 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
114 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4)
115 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
116 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
117 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
118 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
119 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
120 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
121 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
122 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
123 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
124 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
125 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
127 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
128 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
129 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
131 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0)
132 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
133 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
134 #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
135 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4)
136 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
137 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
138 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)
140 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0)
141 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)
142 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2)
143 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
144 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
145 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5)
146 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)
148 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
149 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
150 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
152 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0)
153 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1)
155 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0)
156 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1)
158 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
159 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
161 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
162 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
163 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
165 #define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0)
166 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
167 #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2)
169 #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
170 #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
171 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
173 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
175 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
176 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
177 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
178 #define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0)
179 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
181 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
182 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
184 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
185 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
187 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
189 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
190 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
191 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
192 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
193 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
194 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0)
195 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1)
196 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2)
197 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3)
198 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
199 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0)
200 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1)
201 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2)
202 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3)
203 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
204 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
205 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
206 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
207 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
208 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
209 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
210 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
211 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
212 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
213 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
215 #define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1)
216 #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4)
218 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
220 #define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1)
221 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
223 #define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0)
225 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
226 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
228 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
229 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
230 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
231 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
232 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
233 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
234 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
235 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
236 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
237 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
238 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
239 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
240 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
242 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
243 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
245 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
247 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
248 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
249 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
251 #define __PMEV_op2(n) ((n) & 0x7)
252 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
253 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
254 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
255 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
257 #define SYS_PMCCFILTR_EL0 sys_reg (3, 3, 14, 15, 7)
259 #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
260 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
261 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
263 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
264 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0)
265 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1)
266 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2)
267 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
269 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
270 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0)
271 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1)
272 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2)
273 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
275 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
276 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
277 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
278 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
279 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
280 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
281 #define SYS_ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5)
282 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
284 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
285 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0)
286 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1)
287 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2)
288 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
289 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4)
290 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5)
291 #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6)
292 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7)
294 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
295 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0)
296 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1)
297 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2)
298 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
299 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4)
300 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5)
301 #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6)
302 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
304 /* Common SCTLR_ELx flags. */
305 #define SCTLR_ELx_DSSBS (1UL << 44)
306 #define SCTLR_ELx_EE (1 << 25)
307 #define SCTLR_ELx_WXN (1 << 19)
308 #define SCTLR_ELx_I (1 << 12)
309 #define SCTLR_ELx_SA (1 << 3)
310 #define SCTLR_ELx_C (1 << 2)
311 #define SCTLR_ELx_A (1 << 1)
312 #define SCTLR_ELx_M 1
314 #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \
315 SCTLR_ELx_SA | SCTLR_ELx_I)
317 /* SCTLR_EL2 specific flags. */
318 #define SCTLR_EL2_RES1 ((1 << 4) | (1 << 5) | (1 << 11) | (1 << 16) | \
319 (1 << 18) | (1 << 22) | (1 << 23) | (1 << 28) | \
321 #define SCTLR_EL2_RES0 ((1 << 6) | (1 << 7) | (1 << 8) | (1 << 9) | \
322 (1 << 10) | (1 << 13) | (1 << 14) | (1 << 15) | \
323 (1 << 17) | (1 << 20) | (1 << 21) | (1 << 24) | \
324 (1 << 26) | (1 << 27) | (1 << 30) | (1 << 31) | \
325 (0xffffefffUL << 32))
327 #ifdef CONFIG_CPU_BIG_ENDIAN
328 #define ENDIAN_SET_EL2 SCTLR_ELx_EE
329 #define ENDIAN_CLEAR_EL2 0
331 #define ENDIAN_SET_EL2 0
332 #define ENDIAN_CLEAR_EL2 SCTLR_ELx_EE
335 /* SCTLR_EL2 value used for the hyp-stub */
336 #define SCTLR_EL2_SET (ENDIAN_SET_EL2 | SCTLR_EL2_RES1)
337 #define SCTLR_EL2_CLEAR (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \
338 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_WXN | \
339 SCTLR_ELx_DSSBS | ENDIAN_CLEAR_EL2 | SCTLR_EL2_RES0)
341 #if (SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != 0xffffffffffffffff
342 #error "Inconsistent SCTLR_EL2 set/clear bits"
345 /* SCTLR_EL1 specific flags. */
346 #define SCTLR_EL1_UCI (1 << 26)
347 #define SCTLR_EL1_E0E (1 << 24)
348 #define SCTLR_EL1_SPAN (1 << 23)
349 #define SCTLR_EL1_NTWE (1 << 18)
350 #define SCTLR_EL1_NTWI (1 << 16)
351 #define SCTLR_EL1_UCT (1 << 15)
352 #define SCTLR_EL1_DZE (1 << 14)
353 #define SCTLR_EL1_UMA (1 << 9)
354 #define SCTLR_EL1_SED (1 << 8)
355 #define SCTLR_EL1_ITD (1 << 7)
356 #define SCTLR_EL1_CP15BEN (1 << 5)
357 #define SCTLR_EL1_SA0 (1 << 4)
359 #define SCTLR_EL1_RES1 ((1 << 11) | (1 << 20) | (1 << 22) | (1 << 28) | \
361 #define SCTLR_EL1_RES0 ((1 << 6) | (1 << 10) | (1 << 13) | (1 << 17) | \
362 (1 << 21) | (1 << 27) | (1 << 30) | (1 << 31) | \
363 (0xffffefffUL << 32))
365 #ifdef CONFIG_CPU_BIG_ENDIAN
366 #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE)
367 #define ENDIAN_CLEAR_EL1 0
369 #define ENDIAN_SET_EL1 0
370 #define ENDIAN_CLEAR_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE)
373 #define SCTLR_EL1_SET (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA |\
374 SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I |\
375 SCTLR_EL1_DZE | SCTLR_EL1_UCT | SCTLR_EL1_NTWI |\
376 SCTLR_EL1_NTWE | SCTLR_EL1_SPAN | ENDIAN_SET_EL1 |\
377 SCTLR_EL1_UCI | SCTLR_EL1_RES1)
378 #define SCTLR_EL1_CLEAR (SCTLR_ELx_A | SCTLR_EL1_CP15BEN | SCTLR_EL1_ITD |\
379 SCTLR_EL1_UMA | SCTLR_ELx_WXN | ENDIAN_CLEAR_EL1 |\
380 SCTLR_ELx_DSSBS | SCTLR_EL1_RES0)
382 #if (SCTLR_EL1_SET ^ SCTLR_EL1_CLEAR) != 0xffffffffffffffff
383 #error "Inconsistent SCTLR_EL1 set/clear bits"
387 #define ID_AA64ISAR0_TS_SHIFT 52
388 #define ID_AA64ISAR0_FHM_SHIFT 48
389 #define ID_AA64ISAR0_DP_SHIFT 44
390 #define ID_AA64ISAR0_SM4_SHIFT 40
391 #define ID_AA64ISAR0_SM3_SHIFT 36
392 #define ID_AA64ISAR0_SHA3_SHIFT 32
393 #define ID_AA64ISAR0_RDM_SHIFT 28
394 #define ID_AA64ISAR0_ATOMICS_SHIFT 20
395 #define ID_AA64ISAR0_CRC32_SHIFT 16
396 #define ID_AA64ISAR0_SHA2_SHIFT 12
397 #define ID_AA64ISAR0_SHA1_SHIFT 8
398 #define ID_AA64ISAR0_AES_SHIFT 4
401 #define ID_AA64ISAR1_LRCPC_SHIFT 20
402 #define ID_AA64ISAR1_FCMA_SHIFT 16
403 #define ID_AA64ISAR1_JSCVT_SHIFT 12
404 #define ID_AA64ISAR1_DPB_SHIFT 0
407 #define ID_AA64PFR0_CSV3_SHIFT 60
408 #define ID_AA64PFR0_CSV2_SHIFT 56
409 #define ID_AA64PFR0_DIT_SHIFT 48
410 #define ID_AA64PFR0_GIC_SHIFT 24
411 #define ID_AA64PFR0_ASIMD_SHIFT 20
412 #define ID_AA64PFR0_FP_SHIFT 16
413 #define ID_AA64PFR0_EL3_SHIFT 12
414 #define ID_AA64PFR0_EL2_SHIFT 8
415 #define ID_AA64PFR0_EL1_SHIFT 4
416 #define ID_AA64PFR0_EL0_SHIFT 0
418 #define ID_AA64PFR0_FP_NI 0xf
419 #define ID_AA64PFR0_FP_SUPPORTED 0x0
420 #define ID_AA64PFR0_ASIMD_NI 0xf
421 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0
422 #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1
423 #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1
424 #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2
427 #define ID_AA64PFR1_SSBS_SHIFT 4
429 #define ID_AA64PFR1_SSBS_PSTATE_NI 0
430 #define ID_AA64PFR1_SSBS_PSTATE_ONLY 1
431 #define ID_AA64PFR1_SSBS_PSTATE_INSNS 2
434 #define ID_AA64MMFR0_TGRAN4_SHIFT 28
435 #define ID_AA64MMFR0_TGRAN64_SHIFT 24
436 #define ID_AA64MMFR0_TGRAN16_SHIFT 20
437 #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16
438 #define ID_AA64MMFR0_SNSMEM_SHIFT 12
439 #define ID_AA64MMFR0_BIGENDEL_SHIFT 8
440 #define ID_AA64MMFR0_ASID_SHIFT 4
441 #define ID_AA64MMFR0_PARANGE_SHIFT 0
443 #define ID_AA64MMFR0_TGRAN4_NI 0xf
444 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
445 #define ID_AA64MMFR0_TGRAN64_NI 0xf
446 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
447 #define ID_AA64MMFR0_TGRAN16_NI 0x0
448 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
451 #define ID_AA64MMFR1_PAN_SHIFT 20
452 #define ID_AA64MMFR1_LOR_SHIFT 16
453 #define ID_AA64MMFR1_HPD_SHIFT 12
454 #define ID_AA64MMFR1_VHE_SHIFT 8
455 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4
456 #define ID_AA64MMFR1_HADBS_SHIFT 0
458 #define ID_AA64MMFR1_VMIDBITS_8 0
459 #define ID_AA64MMFR1_VMIDBITS_16 2
462 #define ID_AA64MMFR2_AT_SHIFT 32
463 #define ID_AA64MMFR2_LVA_SHIFT 16
464 #define ID_AA64MMFR2_IESB_SHIFT 12
465 #define ID_AA64MMFR2_LSM_SHIFT 8
466 #define ID_AA64MMFR2_UAO_SHIFT 4
467 #define ID_AA64MMFR2_CNP_SHIFT 0
470 #define ID_AA64DFR0_PMSVER_SHIFT 32
471 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28
472 #define ID_AA64DFR0_WRPS_SHIFT 20
473 #define ID_AA64DFR0_BRPS_SHIFT 12
474 #define ID_AA64DFR0_PMUVER_SHIFT 8
475 #define ID_AA64DFR0_TRACEVER_SHIFT 4
476 #define ID_AA64DFR0_DEBUGVER_SHIFT 0
478 #define ID_ISAR5_RDM_SHIFT 24
479 #define ID_ISAR5_CRC32_SHIFT 16
480 #define ID_ISAR5_SHA2_SHIFT 12
481 #define ID_ISAR5_SHA1_SHIFT 8
482 #define ID_ISAR5_AES_SHIFT 4
483 #define ID_ISAR5_SEVL_SHIFT 0
485 #define MVFR0_FPROUND_SHIFT 28
486 #define MVFR0_FPSHVEC_SHIFT 24
487 #define MVFR0_FPSQRT_SHIFT 20
488 #define MVFR0_FPDIVIDE_SHIFT 16
489 #define MVFR0_FPTRAP_SHIFT 12
490 #define MVFR0_FPDP_SHIFT 8
491 #define MVFR0_FPSP_SHIFT 4
492 #define MVFR0_SIMD_SHIFT 0
494 #define MVFR1_SIMDFMAC_SHIFT 28
495 #define MVFR1_FPHP_SHIFT 24
496 #define MVFR1_SIMDHP_SHIFT 20
497 #define MVFR1_SIMDSP_SHIFT 16
498 #define MVFR1_SIMDINT_SHIFT 12
499 #define MVFR1_SIMDLS_SHIFT 8
500 #define MVFR1_FPDNAN_SHIFT 4
501 #define MVFR1_FPFTZ_SHIFT 0
504 #define ID_AA64MMFR0_TGRAN4_SHIFT 28
505 #define ID_AA64MMFR0_TGRAN64_SHIFT 24
506 #define ID_AA64MMFR0_TGRAN16_SHIFT 20
508 #define ID_AA64MMFR0_TGRAN4_NI 0xf
509 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
510 #define ID_AA64MMFR0_TGRAN64_NI 0xf
511 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
512 #define ID_AA64MMFR0_TGRAN16_NI 0x0
513 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
515 #if defined(CONFIG_ARM64_4K_PAGES)
516 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT
517 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED
518 #elif defined(CONFIG_ARM64_16K_PAGES)
519 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT
520 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED
521 #elif defined(CONFIG_ARM64_64K_PAGES)
522 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT
523 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED
527 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
528 #define SYS_MPIDR_SAFE_VAL (1UL << 31)
532 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
533 .equ .L__reg_num_x\num, \num
535 .equ .L__reg_num_xzr, 31
537 .macro mrs_s, rt, sreg
538 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt))
541 .macro msr_s, sreg, rt
542 __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt))
547 #include <linux/build_bug.h>
548 #include <linux/types.h>
551 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
552 " .equ .L__reg_num_x\\num, \\num\n"
554 " .equ .L__reg_num_xzr, 31\n"
556 " .macro mrs_s, rt, sreg\n"
557 __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt))
560 " .macro msr_s, sreg, rt\n"
561 __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt))
566 * Unlike read_cpuid, calls to read_sysreg are never expected to be
567 * optimized away or replaced with synthetic values.
569 #define read_sysreg(r) ({ \
571 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
576 * The "Z" constraint normally means a zero immediate, but when combined with
577 * the "%x0" template means XZR.
579 #define write_sysreg(v, r) do { \
580 u64 __val = (u64)(v); \
581 asm volatile("msr " __stringify(r) ", %x0" \
586 * For registers without architectural names, or simply unsupported by
589 #define read_sysreg_s(r) ({ \
591 asm volatile("mrs_s %0, " __stringify(r) : "=r" (__val)); \
595 #define write_sysreg_s(v, r) do { \
596 u64 __val = (u64)(v); \
597 asm volatile("msr_s " __stringify(r) ", %x0" : : "rZ" (__val)); \
601 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the
602 * set mask are set. Other bits are left as-is.
604 #define sysreg_clear_set(sysreg, clear, set) do { \
605 u64 __scs_val = read_sysreg(sysreg); \
606 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \
607 if (__scs_new != __scs_val) \
608 write_sysreg(__scs_new, sysreg); \
611 static inline void config_sctlr_el1(u32 clear, u32 set)
615 val = read_sysreg(sctlr_el1);
618 write_sysreg(val, sctlr_el1);
623 #endif /* __ASM_SYSREG_H */