arch/arm64/include/asm/processor.h

   1 /*
   2  * Based on arch/arm/include/asm/processor.h
   3  *
   4  * Copyright (C) 1995-1999 Russell King
   5  * Copyright (C) 2012 ARM Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef __ASM_PROCESSOR_H
  20 #define __ASM_PROCESSOR_H
  21
  22 #define TASK_SIZE_64            (UL(1) << VA_BITS)
  23
  24 #define KERNEL_DS       UL(-1)
  25 #define USER_DS         (TASK_SIZE_64 - 1)
  26
  27 #ifndef __ASSEMBLY__
  28
  29 /*
  30  * Default implementation of macro that returns current
  31  * instruction pointer ("program counter").
  32  */
  33 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
  34
  35 #ifdef __KERNEL__
  36
  37 #include <linux/string.h>
  38
  39 #include <asm/alternative.h>
  40 #include <asm/fpsimd.h>
  41 #include <asm/hw_breakpoint.h>
  42 #include <asm/lse.h>
  43 #include <asm/pgtable-hwdef.h>
  44 #include <asm/ptrace.h>
  45 #include <asm/types.h>
  46
  47 /*
  48  * TASK_SIZE - the maximum size of a user space task.
  49  * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area.
  50  */
  51 #ifdef CONFIG_COMPAT
  52 #ifdef CONFIG_ARM64_64K_PAGES
  53 /*
  54  * With CONFIG_ARM64_64K_PAGES enabled, the last page is occupied
  55  * by the compat vectors page.
  56  */
  57 #define TASK_SIZE_32            UL(0x100000000)
  58 #else
  59 #define TASK_SIZE_32            (UL(0x100000000) - PAGE_SIZE)
  60 #endif /* CONFIG_ARM64_64K_PAGES */
  61 #define TASK_SIZE               (test_thread_flag(TIF_32BIT) ? \
  62                                 TASK_SIZE_32 : TASK_SIZE_64)
  63 #define TASK_SIZE_OF(tsk)       (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
  64                                 TASK_SIZE_32 : TASK_SIZE_64)
  65 #else
  66 #define TASK_SIZE               TASK_SIZE_64
  67 #endif /* CONFIG_COMPAT */
  68
  69 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 4))
  70
  71 #define STACK_TOP_MAX           TASK_SIZE_64
  72 #ifdef CONFIG_COMPAT
  73 #define AARCH32_VECTORS_BASE    0xffff0000
  74 #define STACK_TOP               (test_thread_flag(TIF_32BIT) ? \
  75                                 AARCH32_VECTORS_BASE : STACK_TOP_MAX)
  76 #else
  77 #define STACK_TOP               STACK_TOP_MAX
  78 #endif /* CONFIG_COMPAT */
  79
  80 extern phys_addr_t arm64_dma_phys_limit;
  81 #define ARCH_LOW_ADDRESS_LIMIT  (arm64_dma_phys_limit - 1)
  82
  83 struct debug_info {
  84         /* Have we suspended stepping by a debugger? */
  85         int                     suspended_step;
  86         /* Allow breakpoints and watchpoints to be disabled for this thread. */
  87         int                     bps_disabled;
  88         int                     wps_disabled;
  89         /* Hardware breakpoints pinned to this task. */
  90         struct perf_event       *hbp_break[ARM_MAX_BRP];
  91         struct perf_event       *hbp_watch[ARM_MAX_WRP];
  92 };
  93
  94 struct cpu_context {
  95         unsigned long x19;
  96         unsigned long x20;
  97         unsigned long x21;
  98         unsigned long x22;
  99         unsigned long x23;
 100         unsigned long x24;
 101         unsigned long x25;
 102         unsigned long x26;
 103         unsigned long x27;
 104         unsigned long x28;
 105         unsigned long fp;
 106         unsigned long sp;
 107         unsigned long pc;
 108 };
 109
 110 struct thread_struct {
 111         struct cpu_context      cpu_context;    /* cpu context */
 112         unsigned long           tp_value;       /* TLS register */
 113 #ifdef CONFIG_COMPAT
 114         unsigned long           tp2_value;
 115 #endif
 116         struct fpsimd_state     fpsimd_state;
 117         unsigned long           fault_address;  /* fault info */
 118         unsigned long           fault_code;     /* ESR_EL1 value */
 119         struct debug_info       debug;          /* debugging */
 120 };
 121
 122 #ifdef CONFIG_COMPAT
 123 #define task_user_tls(t)                                                \
 124 ({                                                                      \
 125         unsigned long *__tls;                                           \
 126         if (is_compat_thread(task_thread_info(t)))                      \
 127                 __tls = &(t)->thread.tp2_value;                         \
 128         else                                                            \
 129                 __tls = &(t)->thread.tp_value;                          \
 130         __tls;                                                          \
 131  })
 132 #else
 133 #define task_user_tls(t)        (&(t)->thread.tp_value)
 134 #endif
 135
 136 #define INIT_THREAD  {  }
 137
 138 static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
 139 {
 140         memset(regs, 0, sizeof(*regs));
 141         regs->syscallno = ~0UL;
 142         regs->pc = pc;
 143 }
 144
 145 static inline void start_thread(struct pt_regs *regs, unsigned long pc,
 146                                 unsigned long sp)
 147 {
 148         start_thread_common(regs, pc);
 149         regs->pstate = PSR_MODE_EL0t;
 150         regs->sp = sp;
 151 }
 152
 153 #ifdef CONFIG_COMPAT
 154 static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
 155                                        unsigned long sp)
 156 {
 157         start_thread_common(regs, pc);
 158         regs->pstate = COMPAT_PSR_MODE_USR;
 159         if (pc & 1)
 160                 regs->pstate |= COMPAT_PSR_T_BIT;
 161
 162 #ifdef __AARCH64EB__
 163         regs->pstate |= COMPAT_PSR_E_BIT;
 164 #endif
 165
 166         regs->compat_sp = sp;
 167 }
 168 #endif
 169
 170 /* Forward declaration, a strange C thing */
 171 struct task_struct;
 172
 173 /* Free all resources held by a thread. */
 174 extern void release_thread(struct task_struct *);
 175
 176 unsigned long get_wchan(struct task_struct *p);
 177
 178 static inline void cpu_relax(void)
 179 {
 180         asm volatile("yield" ::: "memory");
 181 }
 182
 183 #define cpu_relax_lowlatency()                cpu_relax()
 184
 185 /* Thread switching */
 186 extern struct task_struct *cpu_switch_to(struct task_struct *prev,
 187                                          struct task_struct *next);
 188
 189 #define task_pt_regs(p) \
 190         ((struct pt_regs *)(THREAD_START_SP + task_stack_page(p)) - 1)
 191
 192 #define KSTK_EIP(tsk)   ((unsigned long)task_pt_regs(tsk)->pc)
 193 #define KSTK_ESP(tsk)   user_stack_pointer(task_pt_regs(tsk))
 194
 195 /*
 196  * Prefetching support
 197  */
 198 #define ARCH_HAS_PREFETCH
 199 static inline void prefetch(const void *ptr)
 200 {
 201         asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
 202 }
 203
 204 #define ARCH_HAS_PREFETCHW
 205 static inline void prefetchw(const void *ptr)
 206 {
 207         asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
 208 }
 209
 210 #define ARCH_HAS_SPINLOCK_PREFETCH
 211 static inline void spin_lock_prefetch(const void *ptr)
 212 {
 213         asm volatile(ARM64_LSE_ATOMIC_INSN(
 214                      "prfm pstl1strm, %a0",
 215                      "nop") : : "p" (ptr));
 216 }
 217
 218 #define HAVE_ARCH_PICK_MMAP_LAYOUT
 219
 220 #endif
 221
 222 int cpu_enable_pan(void *__unused);
 223 int cpu_enable_uao(void *__unused);
 224 int cpu_enable_cache_maint_trap(void *__unused);
 225
 226 #endif /* __ASSEMBLY__ */
 227 #endif /* __ASM_PROCESSOR_H */