1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012 ARM Ltd.
5 #ifndef __ASM_PGTABLE_H
6 #define __ASM_PGTABLE_H
9 #include <asm/proc-fns.h>
11 #include <asm/memory.h>
12 #include <asm/pgtable-hwdef.h>
13 #include <asm/pgtable-prot.h>
14 #include <asm/tlbflush.h>
19 * VMALLOC_START: beginning of the kernel vmalloc space
20 * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space
23 #define VMALLOC_START (MODULES_END)
24 #define VMALLOC_END (- PUD_SIZE - VMEMMAP_SIZE - SZ_64K)
26 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT))
28 #define FIRST_USER_ADDRESS 0UL
32 #include <asm/cmpxchg.h>
33 #include <asm/fixmap.h>
34 #include <linux/mmdebug.h>
35 #include <linux/mm_types.h>
36 #include <linux/sched.h>
38 extern void __pte_error(const char *file, int line, unsigned long val);
39 extern void __pmd_error(const char *file, int line, unsigned long val);
40 extern void __pud_error(const char *file, int line, unsigned long val);
41 extern void __pgd_error(const char *file, int line, unsigned long val);
44 * ZERO_PAGE is a global shared page that is always zero: used
45 * for zero-mapped memory areas etc..
47 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
48 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page))
50 #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
53 * Macros to convert between a physical address and its placement in a
54 * page table entry, taking care of 52-bit addresses.
56 #ifdef CONFIG_ARM64_PA_BITS_52
57 static inline phys_addr_t __pte_to_phys(pte_t pte)
59 return (pte_val(pte) & PTE_ADDR_LOW) |
60 ((pte_val(pte) & PTE_ADDR_HIGH) << 36);
62 static inline pteval_t __phys_to_pte_val(phys_addr_t phys)
64 return (phys | (phys >> 36)) & PTE_ADDR_MASK;
67 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK)
68 #define __phys_to_pte_val(phys) (phys)
71 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT)
72 #define pfn_pte(pfn,prot) \
73 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
75 #define pte_none(pte) (!pte_val(pte))
76 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
77 #define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
80 * The following only work if pte_present(). Undefined behaviour otherwise.
82 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
83 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
84 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
85 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
86 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN))
87 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT))
88 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP))
90 #define pte_cont_addr_end(addr, end) \
91 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \
92 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
95 #define pmd_cont_addr_end(addr, end) \
96 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \
97 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
100 #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))
101 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
102 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte))
104 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID))
105 #define pte_valid_not_user(pte) \
106 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID)
107 #define pte_valid_user(pte) \
108 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER))
111 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending
112 * so that we don't erroneously return false for pages that have been
113 * remapped as PROT_NONE but are yet to be flushed from the TLB.
114 * Note that we can't make any assumptions based on the state of the access
115 * flag, since ptep_clear_flush_young() elides a DSB when invalidating the
118 #define pte_accessible(mm, pte) \
119 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))
122 * p??_access_permitted() is true for valid user mappings (subject to the
123 * write permission check). PROT_NONE mappings do not have the PTE_VALID bit
126 #define pte_access_permitted(pte, write) \
127 (pte_valid_user(pte) && (!(write) || pte_write(pte)))
128 #define pmd_access_permitted(pmd, write) \
129 (pte_access_permitted(pmd_pte(pmd), (write)))
130 #define pud_access_permitted(pud, write) \
131 (pte_access_permitted(pud_pte(pud), (write)))
133 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
135 pte_val(pte) &= ~pgprot_val(prot);
139 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
141 pte_val(pte) |= pgprot_val(prot);
145 static inline pte_t pte_mkwrite(pte_t pte)
147 pte = set_pte_bit(pte, __pgprot(PTE_WRITE));
148 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
152 static inline pte_t pte_mkclean(pte_t pte)
154 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY));
155 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
160 static inline pte_t pte_mkdirty(pte_t pte)
162 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY));
165 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
170 static inline pte_t pte_wrprotect(pte_t pte)
173 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY
174 * clear), set the PTE_DIRTY bit.
176 if (pte_hw_dirty(pte))
177 pte = pte_mkdirty(pte);
179 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE));
180 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
184 static inline pte_t pte_mkold(pte_t pte)
186 return clear_pte_bit(pte, __pgprot(PTE_AF));
189 static inline pte_t pte_mkyoung(pte_t pte)
191 return set_pte_bit(pte, __pgprot(PTE_AF));
194 static inline pte_t pte_mkspecial(pte_t pte)
196 return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
199 static inline pte_t pte_mkcont(pte_t pte)
201 pte = set_pte_bit(pte, __pgprot(PTE_CONT));
202 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE));
205 static inline pte_t pte_mknoncont(pte_t pte)
207 return clear_pte_bit(pte, __pgprot(PTE_CONT));
210 static inline pte_t pte_mkpresent(pte_t pte)
212 return set_pte_bit(pte, __pgprot(PTE_VALID));
215 static inline pmd_t pmd_mkcont(pmd_t pmd)
217 return __pmd(pmd_val(pmd) | PMD_SECT_CONT);
220 static inline pte_t pte_mkdevmap(pte_t pte)
222 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL));
225 static inline void set_pte(pte_t *ptep, pte_t pte)
227 WRITE_ONCE(*ptep, pte);
230 * Only if the new pte is valid and kernel, otherwise TLB maintenance
231 * or update_mmu_cache() have the necessary barriers.
233 if (pte_valid_not_user(pte)) {
239 extern void __sync_icache_dcache(pte_t pteval);
242 * PTE bits configuration in the presence of hardware Dirty Bit Management
243 * (PTE_WRITE == PTE_DBM):
245 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw)
251 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
252 * the page fault mechanism. Checking the dirty status of a pte becomes:
254 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
257 static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep,
262 if (!IS_ENABLED(CONFIG_DEBUG_VM))
265 old_pte = READ_ONCE(*ptep);
267 if (!pte_valid(old_pte) || !pte_valid(pte))
269 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1)
273 * Check for potential race with hardware updates of the pte
274 * (ptep_set_access_flags safely changes valid ptes without going
275 * through an invalid entry).
277 VM_WARN_ONCE(!pte_young(pte),
278 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx",
279 __func__, pte_val(old_pte), pte_val(pte));
280 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte),
281 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx",
282 __func__, pte_val(old_pte), pte_val(pte));
285 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
286 pte_t *ptep, pte_t pte)
288 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte))
289 __sync_icache_dcache(pte);
291 __check_racy_pte_update(mm, ptep, pte);
297 * Huge pte definitions.
299 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
302 * Hugetlb definitions.
304 #define HUGE_MAX_HSTATE 4
305 #define HPAGE_SHIFT PMD_SHIFT
306 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
307 #define HPAGE_MASK (~(HPAGE_SIZE - 1))
308 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
310 static inline pte_t pgd_pte(pgd_t pgd)
312 return __pte(pgd_val(pgd));
315 static inline pte_t pud_pte(pud_t pud)
317 return __pte(pud_val(pud));
320 static inline pud_t pte_pud(pte_t pte)
322 return __pud(pte_val(pte));
325 static inline pmd_t pud_pmd(pud_t pud)
327 return __pmd(pud_val(pud));
330 static inline pte_t pmd_pte(pmd_t pmd)
332 return __pte(pmd_val(pmd));
335 static inline pmd_t pte_pmd(pte_t pte)
337 return __pmd(pte_val(pte));
340 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot)
342 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT);
345 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot)
347 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT);
350 #ifdef CONFIG_NUMA_BALANCING
352 * See the comment in include/asm-generic/pgtable.h
354 static inline int pte_protnone(pte_t pte)
356 return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE;
359 static inline int pmd_protnone(pmd_t pmd)
361 return pte_protnone(pmd_pte(pmd));
369 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
370 #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
371 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
373 #define pmd_present(pmd) pte_present(pmd_pte(pmd))
374 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
375 #define pmd_young(pmd) pte_young(pmd_pte(pmd))
376 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd))
377 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
378 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
379 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
380 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
381 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
382 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
383 #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_SECT_VALID))
385 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd))
387 #define pmd_write(pmd) pte_write(pmd_pte(pmd))
389 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
391 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
392 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd))
394 static inline pmd_t pmd_mkdevmap(pmd_t pmd)
396 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP)));
399 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd))
400 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys)
401 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT)
402 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
403 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
405 #define pud_young(pud) pte_young(pud_pte(pud))
406 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud)))
407 #define pud_write(pud) pte_write(pud_pte(pud))
409 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT))
411 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud))
412 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys)
413 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT)
414 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
416 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd))
418 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd))
419 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys)
421 #define __pgprot_modify(prot,mask,bits) \
422 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
425 * Mark the prot value as uncacheable and unbufferable.
427 #define pgprot_noncached(prot) \
428 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
429 #define pgprot_writecombine(prot) \
430 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
431 #define pgprot_device(prot) \
432 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
434 * DMA allocations for non-coherent devices use what the Arm architecture calls
435 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses
436 * and merging of writes. This is different from "Device-nGnR[nE]" memory which
437 * is intended for MMIO and thus forbids speculation, preserves access size,
438 * requires strict alignment and can also force write responses to come from the
441 #define pgprot_dmacoherent(prot) \
442 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \
443 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
445 #define __HAVE_PHYS_MEM_ACCESS_PROT
447 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
448 unsigned long size, pgprot_t vma_prot);
450 #define pmd_none(pmd) (!pmd_val(pmd))
452 #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT))
454 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
456 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
459 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3
460 static inline bool pud_sect(pud_t pud) { return false; }
461 static inline bool pud_table(pud_t pud) { return true; }
463 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
465 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
469 extern pgd_t init_pg_dir[PTRS_PER_PGD];
470 extern pgd_t init_pg_end[];
471 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
472 extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
473 extern pgd_t idmap_pg_end[];
474 extern pgd_t tramp_pg_dir[PTRS_PER_PGD];
475 extern pgd_t reserved_pg_dir[PTRS_PER_PGD];
477 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd);
479 static inline bool in_swapper_pgdir(void *addr)
481 return ((unsigned long)addr & PAGE_MASK) ==
482 ((unsigned long)swapper_pg_dir & PAGE_MASK);
485 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
487 #ifdef __PAGETABLE_PMD_FOLDED
488 if (in_swapper_pgdir(pmdp)) {
489 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd)));
492 #endif /* __PAGETABLE_PMD_FOLDED */
494 WRITE_ONCE(*pmdp, pmd);
496 if (pmd_valid(pmd)) {
502 static inline void pmd_clear(pmd_t *pmdp)
504 set_pmd(pmdp, __pmd(0));
507 static inline phys_addr_t pmd_page_paddr(pmd_t pmd)
509 return __pmd_to_phys(pmd);
512 static inline void pte_unmap(pte_t *pte) { }
514 /* Find an entry in the third-level page table. */
515 #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
517 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t))
518 #define pte_offset_kernel(dir,addr) ((pte_t *)__va(pte_offset_phys((dir), (addr))))
520 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
522 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr))
523 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr))
524 #define pte_clear_fixmap() clear_fixmap(FIX_PTE)
526 #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(__pmd_to_phys(pmd)))
528 /* use ONLY for statically allocated translation tables */
529 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr))))
532 * Conversion functions: convert a page and protection to a page entry,
533 * and a page entry and page directory to the page they refer to.
535 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
537 #if CONFIG_PGTABLE_LEVELS > 2
539 #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
541 #define pud_none(pud) (!pud_val(pud))
542 #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT))
543 #define pud_present(pud) pte_present(pud_pte(pud))
544 #define pud_valid(pud) pte_valid(pud_pte(pud))
546 static inline void set_pud(pud_t *pudp, pud_t pud)
548 #ifdef __PAGETABLE_PUD_FOLDED
549 if (in_swapper_pgdir(pudp)) {
550 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud)));
553 #endif /* __PAGETABLE_PUD_FOLDED */
555 WRITE_ONCE(*pudp, pud);
557 if (pud_valid(pud)) {
563 static inline void pud_clear(pud_t *pudp)
565 set_pud(pudp, __pud(0));
568 static inline phys_addr_t pud_page_paddr(pud_t pud)
570 return __pud_to_phys(pud);
573 /* Find an entry in the second-level page table. */
574 #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
576 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t))
577 #define pmd_offset(dir, addr) ((pmd_t *)__va(pmd_offset_phys((dir), (addr))))
579 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr))
580 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr))
581 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD)
583 #define pud_page(pud) pfn_to_page(__phys_to_pfn(__pud_to_phys(pud)))
585 /* use ONLY for statically allocated translation tables */
586 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr))))
590 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; })
592 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */
593 #define pmd_set_fixmap(addr) NULL
594 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp)
595 #define pmd_clear_fixmap()
597 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir)
599 #endif /* CONFIG_PGTABLE_LEVELS > 2 */
601 #if CONFIG_PGTABLE_LEVELS > 3
603 #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud))
605 #define pgd_none(pgd) (!pgd_val(pgd))
606 #define pgd_bad(pgd) (!(pgd_val(pgd) & 2))
607 #define pgd_present(pgd) (pgd_val(pgd))
609 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
611 if (in_swapper_pgdir(pgdp)) {
612 set_swapper_pgd(pgdp, pgd);
616 WRITE_ONCE(*pgdp, pgd);
621 static inline void pgd_clear(pgd_t *pgdp)
623 set_pgd(pgdp, __pgd(0));
626 static inline phys_addr_t pgd_page_paddr(pgd_t pgd)
628 return __pgd_to_phys(pgd);
631 /* Find an entry in the frst-level page table. */
632 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))
634 #define pud_offset_phys(dir, addr) (pgd_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t))
635 #define pud_offset(dir, addr) ((pud_t *)__va(pud_offset_phys((dir), (addr))))
637 #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr))
638 #define pud_set_fixmap_offset(pgd, addr) pud_set_fixmap(pud_offset_phys(pgd, addr))
639 #define pud_clear_fixmap() clear_fixmap(FIX_PUD)
641 #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd)))
643 /* use ONLY for statically allocated translation tables */
644 #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr))))
648 #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;})
650 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */
651 #define pud_set_fixmap(addr) NULL
652 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp)
653 #define pud_clear_fixmap()
655 #define pud_offset_kimg(dir,addr) ((pud_t *)dir)
657 #endif /* CONFIG_PGTABLE_LEVELS > 3 */
659 #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
661 /* to find an entry in a page-table-directory */
662 #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
664 #define pgd_offset_raw(pgd, addr) ((pgd) + pgd_index(addr))
666 #define pgd_offset(mm, addr) (pgd_offset_raw((mm)->pgd, (addr)))
668 /* to find an entry in a kernel page-table-directory */
669 #define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
671 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr))
672 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD)
674 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
676 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
677 PTE_PROT_NONE | PTE_VALID | PTE_WRITE;
678 /* preserve the hardware dirty information */
679 if (pte_hw_dirty(pte))
680 pte = pte_mkdirty(pte);
681 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
683 * If we end up clearing hw dirtiness for a sw-dirty PTE, set hardware
686 if (pte_sw_dirty(pte))
687 pte = pte_mkdirty(pte);
691 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
693 return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
696 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
697 extern int ptep_set_access_flags(struct vm_area_struct *vma,
698 unsigned long address, pte_t *ptep,
699 pte_t entry, int dirty);
701 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
702 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
703 static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
704 unsigned long address, pmd_t *pmdp,
705 pmd_t entry, int dirty)
707 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty);
710 static inline int pud_devmap(pud_t pud)
715 static inline int pgd_devmap(pgd_t pgd)
722 * Atomic pte/pmd modifications.
724 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
725 static inline int __ptep_test_and_clear_young(pte_t *ptep)
729 pte = READ_ONCE(*ptep);
732 pte = pte_mkold(pte);
733 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
734 pte_val(old_pte), pte_val(pte));
735 } while (pte_val(pte) != pte_val(old_pte));
737 return pte_young(pte);
740 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
741 unsigned long address,
744 return __ptep_test_and_clear_young(ptep);
747 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
748 static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
749 unsigned long address, pte_t *ptep)
751 int young = ptep_test_and_clear_young(vma, address, ptep);
755 * We can elide the trailing DSB here since the worst that can
756 * happen is that a CPU continues to use the young entry in its
757 * TLB and we mistakenly reclaim the associated page. The
758 * window for such an event is bounded by the next
759 * context-switch, which provides a DSB to complete the TLB
762 flush_tlb_page_nosync(vma, address);
768 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
769 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
770 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
771 unsigned long address,
774 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
776 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
778 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
779 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
780 unsigned long address, pte_t *ptep)
782 return __pte(xchg_relaxed(&pte_val(*ptep), 0));
785 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
786 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
787 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
788 unsigned long address, pmd_t *pmdp)
790 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp));
792 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
795 * ptep_set_wrprotect - mark read-only while trasferring potential hardware
796 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit.
798 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
799 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
803 pte = READ_ONCE(*ptep);
806 pte = pte_wrprotect(pte);
807 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
808 pte_val(old_pte), pte_val(pte));
809 } while (pte_val(pte) != pte_val(old_pte));
812 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
813 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
814 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
815 unsigned long address, pmd_t *pmdp)
817 ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
820 #define pmdp_establish pmdp_establish
821 static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
822 unsigned long address, pmd_t *pmdp, pmd_t pmd)
824 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd)));
829 * Encode and decode a swap entry:
830 * bits 0-1: present (must be zero)
831 * bits 2-7: swap type
832 * bits 8-57: swap offset
833 * bit 58: PTE_PROT_NONE (must be zero)
835 #define __SWP_TYPE_SHIFT 2
836 #define __SWP_TYPE_BITS 6
837 #define __SWP_OFFSET_BITS 50
838 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
839 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
840 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
842 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
843 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
844 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
846 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
847 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
850 * Ensure that there are not more swap files than can be encoded in the kernel
853 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
855 extern int kern_addr_valid(unsigned long addr);
857 #include <asm-generic/pgtable.h>
860 * On AArch64, the cache coherency is handled via the set_pte_at() function.
862 static inline void update_mmu_cache(struct vm_area_struct *vma,
863 unsigned long addr, pte_t *ptep)
866 * We don't do anything here, so there's a very small chance of
867 * us retaking a user fault which we just fixed up. The alternative
868 * is doing a dsb(ishst), but that penalises the fastpath.
872 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
874 #ifdef CONFIG_ARM64_PA_BITS_52
875 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52)
877 #define phys_to_ttbr(addr) (addr)
880 #endif /* !__ASSEMBLY__ */
882 #endif /* __ASM_PGTABLE_H */