2 * Copyright (C) 2012 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 #ifndef __ASM_PGTABLE_H
17 #define __ASM_PGTABLE_H
20 #include <asm/proc-fns.h>
22 #include <asm/memory.h>
23 #include <asm/pgtable-hwdef.h>
24 #include <asm/pgtable-prot.h>
29 * VMALLOC_START: beginning of the kernel vmalloc space
30 * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space
33 #define VMALLOC_START (MODULES_END)
34 #define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K)
36 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT))
38 #define FIRST_USER_ADDRESS 0UL
42 #include <asm/fixmap.h>
43 #include <linux/mmdebug.h>
45 extern void __pte_error(const char *file, int line, unsigned long val);
46 extern void __pmd_error(const char *file, int line, unsigned long val);
47 extern void __pud_error(const char *file, int line, unsigned long val);
48 extern void __pgd_error(const char *file, int line, unsigned long val);
51 * ZERO_PAGE is a global shared page that is always zero: used
52 * for zero-mapped memory areas etc..
54 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
55 #define ZERO_PAGE(vaddr) pfn_to_page(PHYS_PFN(__pa(empty_zero_page)))
57 #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
59 #define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT)
61 #define pfn_pte(pfn,prot) (__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
63 #define pte_none(pte) (!pte_val(pte))
64 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
65 #define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
68 * The following only work if pte_present(). Undefined behaviour otherwise.
70 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
71 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
72 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
73 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
74 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN))
75 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT))
77 #ifdef CONFIG_ARM64_HW_AFDBM
78 #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))
80 #define pte_hw_dirty(pte) (0)
82 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
83 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte))
85 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID))
86 #define pte_valid_not_user(pte) \
87 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID)
88 #define pte_valid_user(pte) \
89 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER))
92 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending
93 * so that we don't erroneously return false for pages that have been
94 * remapped as PROT_NONE but are yet to be flushed from the TLB.
95 * Note that we can't make any assumptions based on the state of the access
96 * flag, since ptep_clear_flush_young() elides a DSB when invalidating the
99 #define pte_accessible(mm, pte) \
100 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))
103 * p??_access_permitted() is true for valid user mappings (subject to the
104 * write permission check). PROT_NONE mappings do not have the PTE_VALID bit
107 #define pte_access_permitted(pte, write) \
108 (pte_valid_user(pte) && (!(write) || pte_write(pte)))
109 #define pmd_access_permitted(pmd, write) \
110 (pte_access_permitted(pmd_pte(pmd), (write)))
111 #define pud_access_permitted(pud, write) \
112 (pte_access_permitted(pud_pte(pud), (write)))
114 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
116 pte_val(pte) &= ~pgprot_val(prot);
120 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
122 pte_val(pte) |= pgprot_val(prot);
126 static inline pte_t pte_wrprotect(pte_t pte)
128 return clear_pte_bit(pte, __pgprot(PTE_WRITE));
131 static inline pte_t pte_mkwrite(pte_t pte)
133 return set_pte_bit(pte, __pgprot(PTE_WRITE));
136 static inline pte_t pte_mkclean(pte_t pte)
138 return clear_pte_bit(pte, __pgprot(PTE_DIRTY));
141 static inline pte_t pte_mkdirty(pte_t pte)
143 return set_pte_bit(pte, __pgprot(PTE_DIRTY));
146 static inline pte_t pte_mkold(pte_t pte)
148 return clear_pte_bit(pte, __pgprot(PTE_AF));
151 static inline pte_t pte_mkyoung(pte_t pte)
153 return set_pte_bit(pte, __pgprot(PTE_AF));
156 static inline pte_t pte_mkspecial(pte_t pte)
158 return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
161 static inline pte_t pte_mkcont(pte_t pte)
163 pte = set_pte_bit(pte, __pgprot(PTE_CONT));
164 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE));
167 static inline pte_t pte_mknoncont(pte_t pte)
169 return clear_pte_bit(pte, __pgprot(PTE_CONT));
172 static inline pte_t pte_clear_rdonly(pte_t pte)
174 return clear_pte_bit(pte, __pgprot(PTE_RDONLY));
177 static inline pte_t pte_mkpresent(pte_t pte)
179 return set_pte_bit(pte, __pgprot(PTE_VALID));
182 static inline pmd_t pmd_mkcont(pmd_t pmd)
184 return __pmd(pmd_val(pmd) | PMD_SECT_CONT);
187 static inline void set_pte(pte_t *ptep, pte_t pte)
192 * Only if the new pte is valid and kernel, otherwise TLB maintenance
193 * or update_mmu_cache() have the necessary barriers.
195 if (pte_valid_not_user(pte)) {
202 struct vm_area_struct;
204 extern void __sync_icache_dcache(pte_t pteval, unsigned long addr);
207 * PTE bits configuration in the presence of hardware Dirty Bit Management
208 * (PTE_WRITE == PTE_DBM):
210 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw)
216 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
217 * the page fault mechanism. Checking the dirty status of a pte becomes:
219 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
221 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
222 pte_t *ptep, pte_t pte)
224 if (pte_present(pte)) {
225 if (pte_sw_dirty(pte) && pte_write(pte))
226 pte_val(pte) &= ~PTE_RDONLY;
228 pte_val(pte) |= PTE_RDONLY;
229 if (pte_user_exec(pte) && !pte_special(pte))
230 __sync_icache_dcache(pte, addr);
234 * If the existing pte is valid, check for potential race with
235 * hardware updates of the pte (ptep_set_access_flags safely changes
236 * valid ptes without going through an invalid entry).
238 if (IS_ENABLED(CONFIG_ARM64_HW_AFDBM) &&
239 pte_valid(*ptep) && pte_valid(pte)) {
240 VM_WARN_ONCE(!pte_young(pte),
241 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx",
242 __func__, pte_val(*ptep), pte_val(pte));
243 VM_WARN_ONCE(pte_write(*ptep) && !pte_dirty(pte),
244 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx",
245 __func__, pte_val(*ptep), pte_val(pte));
251 #define __HAVE_ARCH_PTE_SAME
252 static inline int pte_same(pte_t pte_a, pte_t pte_b)
256 lhs = pte_val(pte_a);
257 rhs = pte_val(pte_b);
259 if (pte_present(pte_a))
262 if (pte_present(pte_b))
269 * Huge pte definitions.
271 #define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT))
272 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
275 * Hugetlb definitions.
277 #define HUGE_MAX_HSTATE 4
278 #define HPAGE_SHIFT PMD_SHIFT
279 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
280 #define HPAGE_MASK (~(HPAGE_SIZE - 1))
281 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
283 #define __HAVE_ARCH_PTE_SPECIAL
285 static inline pte_t pud_pte(pud_t pud)
287 return __pte(pud_val(pud));
290 static inline pmd_t pud_pmd(pud_t pud)
292 return __pmd(pud_val(pud));
295 static inline pte_t pmd_pte(pmd_t pmd)
297 return __pte(pmd_val(pmd));
300 static inline pmd_t pte_pmd(pte_t pte)
302 return __pmd(pte_val(pte));
305 static inline pgprot_t mk_sect_prot(pgprot_t prot)
307 return __pgprot(pgprot_val(prot) & ~PTE_TABLE_BIT);
310 #ifdef CONFIG_NUMA_BALANCING
312 * See the comment in include/asm-generic/pgtable.h
314 static inline int pte_protnone(pte_t pte)
316 return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE;
319 static inline int pmd_protnone(pmd_t pmd)
321 return pte_protnone(pmd_pte(pmd));
329 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
330 #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
331 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
333 #define pmd_present(pmd) pte_present(pmd_pte(pmd))
334 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
335 #define pmd_young(pmd) pte_young(pmd_pte(pmd))
336 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
337 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
338 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
339 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
340 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
341 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
342 #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_SECT_VALID))
344 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd))
346 #define __HAVE_ARCH_PMD_WRITE
347 #define pmd_write(pmd) pte_write(pmd_pte(pmd))
349 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
351 #define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
352 #define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
353 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
355 #define pud_write(pud) pte_write(pud_pte(pud))
356 #define pud_pfn(pud) (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
357 #define pfn_pud(pfn,prot) (__pud(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
359 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd))
361 #define __pgprot_modify(prot,mask,bits) \
362 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
365 * Mark the prot value as uncacheable and unbufferable.
367 #define pgprot_noncached(prot) \
368 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
369 #define pgprot_writecombine(prot) \
370 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
371 #define pgprot_device(prot) \
372 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
373 #define __HAVE_PHYS_MEM_ACCESS_PROT
375 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
376 unsigned long size, pgprot_t vma_prot);
378 #define pmd_none(pmd) (!pmd_val(pmd))
380 #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT))
382 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
384 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
387 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3
388 static inline bool pud_sect(pud_t pud) { return false; }
389 static inline bool pud_table(pud_t pud) { return true; }
391 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
393 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
397 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
404 static inline void pmd_clear(pmd_t *pmdp)
406 set_pmd(pmdp, __pmd(0));
409 static inline phys_addr_t pmd_page_paddr(pmd_t pmd)
411 return pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK;
414 static inline void pte_unmap(pte_t *pte) { }
416 /* Find an entry in the third-level page table. */
417 #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
419 #define pte_offset_phys(dir,addr) (pmd_page_paddr(*(dir)) + pte_index(addr) * sizeof(pte_t))
420 #define pte_offset_kernel(dir,addr) ((pte_t *)__va(pte_offset_phys((dir), (addr))))
422 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
423 #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
424 #define pte_unmap_nested(pte) do { } while (0)
426 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr))
427 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr))
428 #define pte_clear_fixmap() clear_fixmap(FIX_PTE)
430 #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
432 /* use ONLY for statically allocated translation tables */
433 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr))))
436 * Conversion functions: convert a page and protection to a page entry,
437 * and a page entry and page directory to the page they refer to.
439 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
441 #if CONFIG_PGTABLE_LEVELS > 2
443 #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
445 #define pud_none(pud) (!pud_val(pud))
446 #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT))
447 #define pud_present(pud) (pud_val(pud))
449 static inline void set_pud(pud_t *pudp, pud_t pud)
456 static inline void pud_clear(pud_t *pudp)
458 set_pud(pudp, __pud(0));
461 static inline phys_addr_t pud_page_paddr(pud_t pud)
463 return pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK;
466 /* Find an entry in the second-level page table. */
467 #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
469 #define pmd_offset_phys(dir, addr) (pud_page_paddr(*(dir)) + pmd_index(addr) * sizeof(pmd_t))
470 #define pmd_offset(dir, addr) ((pmd_t *)__va(pmd_offset_phys((dir), (addr))))
472 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr))
473 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr))
474 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD)
476 #define pud_page(pud) pfn_to_page(__phys_to_pfn(pud_val(pud) & PHYS_MASK))
478 /* use ONLY for statically allocated translation tables */
479 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr))))
483 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; })
485 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */
486 #define pmd_set_fixmap(addr) NULL
487 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp)
488 #define pmd_clear_fixmap()
490 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir)
492 #endif /* CONFIG_PGTABLE_LEVELS > 2 */
494 #if CONFIG_PGTABLE_LEVELS > 3
496 #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud))
498 #define pgd_none(pgd) (!pgd_val(pgd))
499 #define pgd_bad(pgd) (!(pgd_val(pgd) & 2))
500 #define pgd_present(pgd) (pgd_val(pgd))
502 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
508 static inline void pgd_clear(pgd_t *pgdp)
510 set_pgd(pgdp, __pgd(0));
513 static inline phys_addr_t pgd_page_paddr(pgd_t pgd)
515 return pgd_val(pgd) & PHYS_MASK & (s32)PAGE_MASK;
518 /* Find an entry in the frst-level page table. */
519 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))
521 #define pud_offset_phys(dir, addr) (pgd_page_paddr(*(dir)) + pud_index(addr) * sizeof(pud_t))
522 #define pud_offset(dir, addr) ((pud_t *)__va(pud_offset_phys((dir), (addr))))
524 #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr))
525 #define pud_set_fixmap_offset(pgd, addr) pud_set_fixmap(pud_offset_phys(pgd, addr))
526 #define pud_clear_fixmap() clear_fixmap(FIX_PUD)
528 #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(pgd_val(pgd) & PHYS_MASK))
530 /* use ONLY for statically allocated translation tables */
531 #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr))))
535 #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;})
537 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */
538 #define pud_set_fixmap(addr) NULL
539 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp)
540 #define pud_clear_fixmap()
542 #define pud_offset_kimg(dir,addr) ((pud_t *)dir)
544 #endif /* CONFIG_PGTABLE_LEVELS > 3 */
546 #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
548 /* to find an entry in a page-table-directory */
549 #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
551 #define pgd_offset_raw(pgd, addr) ((pgd) + pgd_index(addr))
553 #define pgd_offset(mm, addr) (pgd_offset_raw((mm)->pgd, (addr)))
555 /* to find an entry in a kernel page-table-directory */
556 #define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
558 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr))
559 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD)
561 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
563 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
564 PTE_PROT_NONE | PTE_VALID | PTE_WRITE;
565 /* preserve the hardware dirty information */
566 if (pte_hw_dirty(pte))
567 pte = pte_mkdirty(pte);
568 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
572 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
574 return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
577 #ifdef CONFIG_ARM64_HW_AFDBM
578 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
579 extern int ptep_set_access_flags(struct vm_area_struct *vma,
580 unsigned long address, pte_t *ptep,
581 pte_t entry, int dirty);
583 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
584 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
585 static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
586 unsigned long address, pmd_t *pmdp,
587 pmd_t entry, int dirty)
589 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty);
594 * Atomic pte/pmd modifications.
596 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
597 static inline int __ptep_test_and_clear_young(pte_t *ptep)
600 unsigned int tmp, res;
602 asm volatile("// __ptep_test_and_clear_young\n"
603 " prfm pstl1strm, %2\n"
605 " ubfx %w3, %w0, %5, #1 // extract PTE_AF (young)\n"
606 " and %0, %0, %4 // clear PTE_AF\n"
607 " stxr %w1, %0, %2\n"
609 : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)), "=&r" (res)
610 : "L" (~PTE_AF), "I" (ilog2(PTE_AF)));
615 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
616 unsigned long address,
619 return __ptep_test_and_clear_young(ptep);
622 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
623 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
624 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
625 unsigned long address,
628 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
630 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
632 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
633 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
634 unsigned long address, pte_t *ptep)
639 asm volatile("// ptep_get_and_clear\n"
640 " prfm pstl1strm, %2\n"
642 " stxr %w1, xzr, %2\n"
644 : "=&r" (old_pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)));
646 return __pte(old_pteval);
649 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
650 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
651 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
652 unsigned long address, pmd_t *pmdp)
654 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp));
656 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
659 * ptep_set_wrprotect - mark read-only while trasferring potential hardware
660 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit.
662 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
663 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
668 asm volatile("// ptep_set_wrprotect\n"
669 " prfm pstl1strm, %2\n"
671 " tst %0, %4 // check for hw dirty (!PTE_RDONLY)\n"
672 " csel %1, %3, xzr, eq // set PTE_DIRTY|PTE_RDONLY if dirty\n"
673 " orr %0, %0, %1 // if !dirty, PTE_RDONLY is already set\n"
674 " and %0, %0, %5 // clear PTE_WRITE/PTE_DBM\n"
675 " stxr %w1, %0, %2\n"
677 : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep))
678 : "r" (PTE_DIRTY|PTE_RDONLY), "L" (PTE_RDONLY), "L" (~PTE_WRITE)
682 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
683 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
684 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
685 unsigned long address, pmd_t *pmdp)
687 ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
690 #endif /* CONFIG_ARM64_HW_AFDBM */
692 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
693 extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
694 extern pgd_t tramp_pg_dir[PTRS_PER_PGD];
697 * Encode and decode a swap entry:
698 * bits 0-1: present (must be zero)
699 * bits 2-7: swap type
700 * bits 8-57: swap offset
701 * bit 58: PTE_PROT_NONE (must be zero)
703 #define __SWP_TYPE_SHIFT 2
704 #define __SWP_TYPE_BITS 6
705 #define __SWP_OFFSET_BITS 50
706 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
707 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
708 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
710 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
711 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
712 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
714 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
715 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
718 * Ensure that there are not more swap files than can be encoded in the kernel
721 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
723 extern int kern_addr_valid(unsigned long addr);
725 #include <asm-generic/pgtable.h>
727 void pgd_cache_init(void);
728 #define pgtable_cache_init pgd_cache_init
731 * On AArch64, the cache coherency is handled via the set_pte_at() function.
733 static inline void update_mmu_cache(struct vm_area_struct *vma,
734 unsigned long addr, pte_t *ptep)
737 * We don't do anything here, so there's a very small chance of
738 * us retaking a user fault which we just fixed up. The alternative
739 * is doing a dsb(ishst), but that penalises the fastpath.
743 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
745 #define kc_vaddr_to_offset(v) ((v) & ~VA_START)
746 #define kc_offset_to_vaddr(o) ((o) | VA_START)
748 #endif /* !__ASSEMBLY__ */
750 #endif /* __ASM_PGTABLE_H */