arch/arm64/include/asm/perf_event.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2012 ARM Ltd.
   4  */
   5
   6 #ifndef __ASM_PERF_EVENT_H
   7 #define __ASM_PERF_EVENT_H
   8
   9 #include <asm/stack_pointer.h>
  10 #include <asm/ptrace.h>
  11
  12 #define ARMV8_PMU_MAX_COUNTERS  32
  13 #define ARMV8_PMU_COUNTER_MASK  (ARMV8_PMU_MAX_COUNTERS - 1)
  14
  15 /*
  16  * Common architectural and microarchitectural event numbers.
  17  */
  18 #define ARMV8_PMUV3_PERFCTR_SW_INCR                             0x0000
  19 #define ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL                    0x0001
  20 #define ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL                      0x0002
  21 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL                    0x0003
  22 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE                           0x0004
  23 #define ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL                      0x0005
  24 #define ARMV8_PMUV3_PERFCTR_LD_RETIRED                          0x0006
  25 #define ARMV8_PMUV3_PERFCTR_ST_RETIRED                          0x0007
  26 #define ARMV8_PMUV3_PERFCTR_INST_RETIRED                        0x0008
  27 #define ARMV8_PMUV3_PERFCTR_EXC_TAKEN                           0x0009
  28 #define ARMV8_PMUV3_PERFCTR_EXC_RETURN                          0x000A
  29 #define ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED                   0x000B
  30 #define ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED                    0x000C
  31 #define ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED                    0x000D
  32 #define ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED                   0x000E
  33 #define ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED              0x000F
  34 #define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED                         0x0010
  35 #define ARMV8_PMUV3_PERFCTR_CPU_CYCLES                          0x0011
  36 #define ARMV8_PMUV3_PERFCTR_BR_PRED                             0x0012
  37 #define ARMV8_PMUV3_PERFCTR_MEM_ACCESS                          0x0013
  38 #define ARMV8_PMUV3_PERFCTR_L1I_CACHE                           0x0014
  39 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB                        0x0015
  40 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE                           0x0016
  41 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL                    0x0017
  42 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB                        0x0018
  43 #define ARMV8_PMUV3_PERFCTR_BUS_ACCESS                          0x0019
  44 #define ARMV8_PMUV3_PERFCTR_MEMORY_ERROR                        0x001A
  45 #define ARMV8_PMUV3_PERFCTR_INST_SPEC                           0x001B
  46 #define ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED                  0x001C
  47 #define ARMV8_PMUV3_PERFCTR_BUS_CYCLES                          0x001D
  48 #define ARMV8_PMUV3_PERFCTR_CHAIN                               0x001E
  49 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE                  0x001F
  50 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE                  0x0020
  51 #define ARMV8_PMUV3_PERFCTR_BR_RETIRED                          0x0021
  52 #define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED                 0x0022
  53 #define ARMV8_PMUV3_PERFCTR_STALL_FRONTEND                      0x0023
  54 #define ARMV8_PMUV3_PERFCTR_STALL_BACKEND                       0x0024
  55 #define ARMV8_PMUV3_PERFCTR_L1D_TLB                             0x0025
  56 #define ARMV8_PMUV3_PERFCTR_L1I_TLB                             0x0026
  57 #define ARMV8_PMUV3_PERFCTR_L2I_CACHE                           0x0027
  58 #define ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL                    0x0028
  59 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE                  0x0029
  60 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL                    0x002A
  61 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE                           0x002B
  62 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB                        0x002C
  63 #define ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL                      0x002D
  64 #define ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL                      0x002E
  65 #define ARMV8_PMUV3_PERFCTR_L2D_TLB                             0x002F
  66 #define ARMV8_PMUV3_PERFCTR_L2I_TLB                             0x0030
  67 #define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS                       0x0031
  68 #define ARMV8_PMUV3_PERFCTR_LL_CACHE                            0x0032
  69 #define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS                       0x0033
  70 #define ARMV8_PMUV3_PERFCTR_DTLB_WALK                           0x0034
  71 #define ARMV8_PMUV3_PERFCTR_ITLB_WALK                           0x0035
  72 #define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD                         0x0036
  73 #define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD                    0x0037
  74 #define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD                    0x0038
  75 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD                  0x0039
  76 #define ARMV8_PMUV3_PERFCTR_OP_RETIRED                          0x003A
  77 #define ARMV8_PMUV3_PERFCTR_OP_SPEC                             0x003B
  78 #define ARMV8_PMUV3_PERFCTR_STALL                               0x003C
  79 #define ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND                  0x003D
  80 #define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND                 0x003E
  81 #define ARMV8_PMUV3_PERFCTR_STALL_SLOT                          0x003F
  82
  83 /* Statistical profiling extension microarchitectural events */
  84 #define ARMV8_SPE_PERFCTR_SAMPLE_POP                            0x4000
  85 #define ARMV8_SPE_PERFCTR_SAMPLE_FEED                           0x4001
  86 #define ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE                       0x4002
  87 #define ARMV8_SPE_PERFCTR_SAMPLE_COLLISION                      0x4003
  88
  89 /* AMUv1 architecture events */
  90 #define ARMV8_AMU_PERFCTR_CNT_CYCLES                            0x4004
  91 #define ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM                     0x4005
  92
  93 /* long-latency read miss events */
  94 #define ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS                     0x4006
  95 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD                  0x4009
  96 #define ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS                     0x400A
  97 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD                  0x400B
  98
  99 /* Trace buffer events */
 100 #define ARMV8_PMUV3_PERFCTR_TRB_WRAP                            0x400C
 101 #define ARMV8_PMUV3_PERFCTR_TRB_TRIG                            0x400E
 102
 103 /* Trace unit events */
 104 #define ARMV8_PMUV3_PERFCTR_TRCEXTOUT0                          0x4010
 105 #define ARMV8_PMUV3_PERFCTR_TRCEXTOUT1                          0x4011
 106 #define ARMV8_PMUV3_PERFCTR_TRCEXTOUT2                          0x4012
 107 #define ARMV8_PMUV3_PERFCTR_TRCEXTOUT3                          0x4013
 108 #define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT4                        0x4018
 109 #define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT5                        0x4019
 110 #define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT6                        0x401A
 111 #define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT7                        0x401B
 112
 113 /* additional latency from alignment events */
 114 #define ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT                      0x4020
 115 #define ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT                        0x4021
 116 #define ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT                        0x4022
 117
 118 /* Armv8.5 Memory Tagging Extension events */
 119 #define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED                    0x4024
 120 #define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD                 0x4025
 121 #define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR                 0x4026
 122
 123 /* ARMv8 recommended implementation defined event types */
 124 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD                       0x0040
 125 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR                       0x0041
 126 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD                0x0042
 127 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR                0x0043
 128 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_INNER             0x0044
 129 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_OUTER             0x0045
 130 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_VICTIM                0x0046
 131 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_CLEAN                 0x0047
 132 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_INVAL                    0x0048
 133
 134 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD                  0x004C
 135 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR                  0x004D
 136 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD                         0x004E
 137 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR                         0x004F
 138 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_RD                       0x0050
 139 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WR                       0x0051
 140 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_RD                0x0052
 141 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_WR                0x0053
 142
 143 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_VICTIM                0x0056
 144 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_CLEAN                 0x0057
 145 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_INVAL                    0x0058
 146
 147 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_RD                  0x005C
 148 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_WR                  0x005D
 149 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_RD                         0x005E
 150 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_WR                         0x005F
 151 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD                      0x0060
 152 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR                      0x0061
 153 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_SHARED                  0x0062
 154 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NOT_SHARED              0x0063
 155 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NORMAL                  0x0064
 156 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_PERIPH                  0x0065
 157 #define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_RD                      0x0066
 158 #define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_WR                      0x0067
 159 #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LD_SPEC                  0x0068
 160 #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_ST_SPEC                  0x0069
 161 #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LDST_SPEC                0x006A
 162
 163 #define ARMV8_IMPDEF_PERFCTR_LDREX_SPEC                         0x006C
 164 #define ARMV8_IMPDEF_PERFCTR_STREX_PASS_SPEC                    0x006D
 165 #define ARMV8_IMPDEF_PERFCTR_STREX_FAIL_SPEC                    0x006E
 166 #define ARMV8_IMPDEF_PERFCTR_STREX_SPEC                         0x006F
 167 #define ARMV8_IMPDEF_PERFCTR_LD_SPEC                            0x0070
 168 #define ARMV8_IMPDEF_PERFCTR_ST_SPEC                            0x0071
 169 #define ARMV8_IMPDEF_PERFCTR_LDST_SPEC                          0x0072
 170 #define ARMV8_IMPDEF_PERFCTR_DP_SPEC                            0x0073
 171 #define ARMV8_IMPDEF_PERFCTR_ASE_SPEC                           0x0074
 172 #define ARMV8_IMPDEF_PERFCTR_VFP_SPEC                           0x0075
 173 #define ARMV8_IMPDEF_PERFCTR_PC_WRITE_SPEC                      0x0076
 174 #define ARMV8_IMPDEF_PERFCTR_CRYPTO_SPEC                        0x0077
 175 #define ARMV8_IMPDEF_PERFCTR_BR_IMMED_SPEC                      0x0078
 176 #define ARMV8_IMPDEF_PERFCTR_BR_RETURN_SPEC                     0x0079
 177 #define ARMV8_IMPDEF_PERFCTR_BR_INDIRECT_SPEC                   0x007A
 178
 179 #define ARMV8_IMPDEF_PERFCTR_ISB_SPEC                           0x007C
 180 #define ARMV8_IMPDEF_PERFCTR_DSB_SPEC                           0x007D
 181 #define ARMV8_IMPDEF_PERFCTR_DMB_SPEC                           0x007E
 182
 183 #define ARMV8_IMPDEF_PERFCTR_EXC_UNDEF                          0x0081
 184 #define ARMV8_IMPDEF_PERFCTR_EXC_SVC                            0x0082
 185 #define ARMV8_IMPDEF_PERFCTR_EXC_PABORT                         0x0083
 186 #define ARMV8_IMPDEF_PERFCTR_EXC_DABORT                         0x0084
 187
 188 #define ARMV8_IMPDEF_PERFCTR_EXC_IRQ                            0x0086
 189 #define ARMV8_IMPDEF_PERFCTR_EXC_FIQ                            0x0087
 190 #define ARMV8_IMPDEF_PERFCTR_EXC_SMC                            0x0088
 191
 192 #define ARMV8_IMPDEF_PERFCTR_EXC_HVC                            0x008A
 193 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_PABORT                    0x008B
 194 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_DABORT                    0x008C
 195 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_OTHER                     0x008D
 196 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_IRQ                       0x008E
 197 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_FIQ                       0x008F
 198 #define ARMV8_IMPDEF_PERFCTR_RC_LD_SPEC                         0x0090
 199 #define ARMV8_IMPDEF_PERFCTR_RC_ST_SPEC                         0x0091
 200
 201 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_RD                       0x00A0
 202 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WR                       0x00A1
 203 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_RD                0x00A2
 204 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_WR                0x00A3
 205
 206 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_VICTIM                0x00A6
 207 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_CLEAN                 0x00A7
 208 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_INVAL                    0x00A8
 209
 210 /*
 211  * Per-CPU PMCR: config reg
 212  */
 213 #define ARMV8_PMU_PMCR_E        (1 << 0) /* Enable all counters */
 214 #define ARMV8_PMU_PMCR_P        (1 << 1) /* Reset all counters */
 215 #define ARMV8_PMU_PMCR_C        (1 << 2) /* Cycle counter reset */
 216 #define ARMV8_PMU_PMCR_D        (1 << 3) /* CCNT counts every 64th cpu cycle */
 217 #define ARMV8_PMU_PMCR_X        (1 << 4) /* Export to ETM */
 218 #define ARMV8_PMU_PMCR_DP       (1 << 5) /* Disable CCNT if non-invasive debug*/
 219 #define ARMV8_PMU_PMCR_LC       (1 << 6) /* Overflow on 64 bit cycle counter */
 220 #define ARMV8_PMU_PMCR_LP       (1 << 7) /* Long event counter enable */
 221 #define ARMV8_PMU_PMCR_N_SHIFT  11       /* Number of counters supported */
 222 #define ARMV8_PMU_PMCR_N_MASK   0x1f
 223 #define ARMV8_PMU_PMCR_MASK     0xff     /* Mask for writable bits */
 224
 225 /*
 226  * PMOVSR: counters overflow flag status reg
 227  */
 228 #define ARMV8_PMU_OVSR_MASK             0xffffffff      /* Mask for writable bits */
 229 #define ARMV8_PMU_OVERFLOWED_MASK       ARMV8_PMU_OVSR_MASK
 230
 231 /*
 232  * PMXEVTYPER: Event selection reg
 233  */
 234 #define ARMV8_PMU_EVTYPE_MASK   0xc800ffff      /* Mask for writable bits */
 235 #define ARMV8_PMU_EVTYPE_EVENT  0xffff          /* Mask for EVENT bits */
 236
 237 /*
 238  * Event filters for PMUv3
 239  */
 240 #define ARMV8_PMU_EXCLUDE_EL1   (1U << 31)
 241 #define ARMV8_PMU_EXCLUDE_EL0   (1U << 30)
 242 #define ARMV8_PMU_INCLUDE_EL2   (1U << 27)
 243
 244 /*
 245  * PMUSERENR: user enable reg
 246  */
 247 #define ARMV8_PMU_USERENR_MASK  0xf             /* Mask for writable bits */
 248 #define ARMV8_PMU_USERENR_EN    (1 << 0) /* PMU regs can be accessed at EL0 */
 249 #define ARMV8_PMU_USERENR_SW    (1 << 1) /* PMSWINC can be written at EL0 */
 250 #define ARMV8_PMU_USERENR_CR    (1 << 2) /* Cycle counter can be read at EL0 */
 251 #define ARMV8_PMU_USERENR_ER    (1 << 3) /* Event counter can be read at EL0 */
 252
 253 /* PMMIR_EL1.SLOTS mask */
 254 #define ARMV8_PMU_SLOTS_MASK    0xff
 255
 256 #define ARMV8_PMU_BUS_SLOTS_SHIFT 8
 257 #define ARMV8_PMU_BUS_SLOTS_MASK 0xff
 258 #define ARMV8_PMU_BUS_WIDTH_SHIFT 16
 259 #define ARMV8_PMU_BUS_WIDTH_MASK 0xf
 260
 261 #ifdef CONFIG_PERF_EVENTS
 262 struct pt_regs;
 263 extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
 264 extern unsigned long perf_misc_flags(struct pt_regs *regs);
 265 #define perf_misc_flags(regs)   perf_misc_flags(regs)
 266 #define perf_arch_bpf_user_pt_regs(regs) &regs->user_regs
 267 #endif
 268
 269 #define perf_arch_fetch_caller_regs(regs, __ip) { \
 270         (regs)->pc = (__ip);    \
 271         (regs)->regs[29] = (unsigned long) __builtin_frame_address(0); \
 272         (regs)->sp = current_stack_pointer; \
 273         (regs)->pstate = PSR_MODE_EL1h; \
 274 }
 275
 276 #endif