arch/arm64/include/asm/percpu.h

   1 /*
   2  * Copyright (C) 2013 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16 #ifndef __ASM_PERCPU_H
  17 #define __ASM_PERCPU_H
  18
  19 #include <asm/alternative.h>
  20
  21 static inline void set_my_cpu_offset(unsigned long off)
  22 {
  23         asm volatile(ALTERNATIVE("msr tpidr_el1, %0",
  24                                  "msr tpidr_el2, %0",
  25                                  ARM64_HAS_VIRT_HOST_EXTN)
  26                         :: "r" (off) : "memory");
  27 }
  28
  29 static inline unsigned long __my_cpu_offset(void)
  30 {
  31         unsigned long off;
  32
  33         /*
  34          * We want to allow caching the value, so avoid using volatile and
  35          * instead use a fake stack read to hazard against barrier().
  36          */
  37         asm(ALTERNATIVE("mrs %0, tpidr_el1",
  38                         "mrs %0, tpidr_el2",
  39                         ARM64_HAS_VIRT_HOST_EXTN)
  40                 : "=r" (off) :
  41                 "Q" (*(const unsigned long *)current_stack_pointer));
  42
  43         return off;
  44 }
  45 #define __my_cpu_offset __my_cpu_offset()
  46
  47 #define PERCPU_OP(op, asm_op)                                           \
  48 static inline unsigned long __percpu_##op(void *ptr,                    \
  49                         unsigned long val, int size)                    \
  50 {                                                                       \
  51         unsigned long loop, ret;                                        \
  52                                                                         \
  53         switch (size) {                                                 \
  54         case 1:                                                         \
  55                 asm ("//__per_cpu_" #op "_1\n"                          \
  56                 "1:     ldxrb     %w[ret], %[ptr]\n"                    \
  57                         #asm_op " %w[ret], %w[ret], %w[val]\n"          \
  58                 "       stxrb     %w[loop], %w[ret], %[ptr]\n"          \
  59                 "       cbnz      %w[loop], 1b"                         \
  60                 : [loop] "=&r" (loop), [ret] "=&r" (ret),               \
  61                   [ptr] "+Q"(*(u8 *)ptr)                                \
  62                 : [val] "Ir" (val));                                    \
  63                 break;                                                  \
  64         case 2:                                                         \
  65                 asm ("//__per_cpu_" #op "_2\n"                          \
  66                 "1:     ldxrh     %w[ret], %[ptr]\n"                    \
  67                         #asm_op " %w[ret], %w[ret], %w[val]\n"          \
  68                 "       stxrh     %w[loop], %w[ret], %[ptr]\n"          \
  69                 "       cbnz      %w[loop], 1b"                         \
  70                 : [loop] "=&r" (loop), [ret] "=&r" (ret),               \
  71                   [ptr]  "+Q"(*(u16 *)ptr)                              \
  72                 : [val] "Ir" (val));                                    \
  73                 break;                                                  \
  74         case 4:                                                         \
  75                 asm ("//__per_cpu_" #op "_4\n"                          \
  76                 "1:     ldxr      %w[ret], %[ptr]\n"                    \
  77                         #asm_op " %w[ret], %w[ret], %w[val]\n"          \
  78                 "       stxr      %w[loop], %w[ret], %[ptr]\n"          \
  79                 "       cbnz      %w[loop], 1b"                         \
  80                 : [loop] "=&r" (loop), [ret] "=&r" (ret),               \
  81                   [ptr] "+Q"(*(u32 *)ptr)                               \
  82                 : [val] "Ir" (val));                                    \
  83                 break;                                                  \
  84         case 8:                                                         \
  85                 asm ("//__per_cpu_" #op "_8\n"                          \
  86                 "1:     ldxr      %[ret], %[ptr]\n"                     \
  87                         #asm_op " %[ret], %[ret], %[val]\n"             \
  88                 "       stxr      %w[loop], %[ret], %[ptr]\n"           \
  89                 "       cbnz      %w[loop], 1b"                         \
  90                 : [loop] "=&r" (loop), [ret] "=&r" (ret),               \
  91                   [ptr] "+Q"(*(u64 *)ptr)                               \
  92                 : [val] "Ir" (val));                                    \
  93                 break;                                                  \
  94         default:                                                        \
  95                 ret = 0;                                                \
  96                 BUILD_BUG();                                            \
  97         }                                                               \
  98                                                                         \
  99         return ret;                                                     \
 100 }
 101
 102 PERCPU_OP(add, add)
 103 PERCPU_OP(and, and)
 104 PERCPU_OP(or, orr)
 105 #undef PERCPU_OP
 106
 107 static inline unsigned long __percpu_read(void *ptr, int size)
 108 {
 109         unsigned long ret;
 110
 111         switch (size) {
 112         case 1:
 113                 ret = ACCESS_ONCE(*(u8 *)ptr);
 114                 break;
 115         case 2:
 116                 ret = ACCESS_ONCE(*(u16 *)ptr);
 117                 break;
 118         case 4:
 119                 ret = ACCESS_ONCE(*(u32 *)ptr);
 120                 break;
 121         case 8:
 122                 ret = ACCESS_ONCE(*(u64 *)ptr);
 123                 break;
 124         default:
 125                 ret = 0;
 126                 BUILD_BUG();
 127         }
 128
 129         return ret;
 130 }
 131
 132 static inline void __percpu_write(void *ptr, unsigned long val, int size)
 133 {
 134         switch (size) {
 135         case 1:
 136                 ACCESS_ONCE(*(u8 *)ptr) = (u8)val;
 137                 break;
 138         case 2:
 139                 ACCESS_ONCE(*(u16 *)ptr) = (u16)val;
 140                 break;
 141         case 4:
 142                 ACCESS_ONCE(*(u32 *)ptr) = (u32)val;
 143                 break;
 144         case 8:
 145                 ACCESS_ONCE(*(u64 *)ptr) = (u64)val;
 146                 break;
 147         default:
 148                 BUILD_BUG();
 149         }
 150 }
 151
 152 static inline unsigned long __percpu_xchg(void *ptr, unsigned long val,
 153                                                 int size)
 154 {
 155         unsigned long ret, loop;
 156
 157         switch (size) {
 158         case 1:
 159                 asm ("//__percpu_xchg_1\n"
 160                 "1:     ldxrb   %w[ret], %[ptr]\n"
 161                 "       stxrb   %w[loop], %w[val], %[ptr]\n"
 162                 "       cbnz    %w[loop], 1b"
 163                 : [loop] "=&r"(loop), [ret] "=&r"(ret),
 164                   [ptr] "+Q"(*(u8 *)ptr)
 165                 : [val] "r" (val));
 166                 break;
 167         case 2:
 168                 asm ("//__percpu_xchg_2\n"
 169                 "1:     ldxrh   %w[ret], %[ptr]\n"
 170                 "       stxrh   %w[loop], %w[val], %[ptr]\n"
 171                 "       cbnz    %w[loop], 1b"
 172                 : [loop] "=&r"(loop), [ret] "=&r"(ret),
 173                   [ptr] "+Q"(*(u16 *)ptr)
 174                 : [val] "r" (val));
 175                 break;
 176         case 4:
 177                 asm ("//__percpu_xchg_4\n"
 178                 "1:     ldxr    %w[ret], %[ptr]\n"
 179                 "       stxr    %w[loop], %w[val], %[ptr]\n"
 180                 "       cbnz    %w[loop], 1b"
 181                 : [loop] "=&r"(loop), [ret] "=&r"(ret),
 182                   [ptr] "+Q"(*(u32 *)ptr)
 183                 : [val] "r" (val));
 184                 break;
 185         case 8:
 186                 asm ("//__percpu_xchg_8\n"
 187                 "1:     ldxr    %[ret], %[ptr]\n"
 188                 "       stxr    %w[loop], %[val], %[ptr]\n"
 189                 "       cbnz    %w[loop], 1b"
 190                 : [loop] "=&r"(loop), [ret] "=&r"(ret),
 191                   [ptr] "+Q"(*(u64 *)ptr)
 192                 : [val] "r" (val));
 193                 break;
 194         default:
 195                 ret = 0;
 196                 BUILD_BUG();
 197         }
 198
 199         return ret;
 200 }
 201
 202 #define _percpu_read(pcp)                                               \
 203 ({                                                                      \
 204         typeof(pcp) __retval;                                           \
 205         preempt_disable_notrace();                                      \
 206         __retval = (typeof(pcp))__percpu_read(raw_cpu_ptr(&(pcp)),      \
 207                                               sizeof(pcp));             \
 208         preempt_enable_notrace();                                       \
 209         __retval;                                                       \
 210 })
 211
 212 #define _percpu_write(pcp, val)                                         \
 213 do {                                                                    \
 214         preempt_disable_notrace();                                      \
 215         __percpu_write(raw_cpu_ptr(&(pcp)), (unsigned long)(val),       \
 216                                 sizeof(pcp));                           \
 217         preempt_enable_notrace();                                       \
 218 } while(0)                                                              \
 219
 220 #define _pcp_protect(operation, pcp, val)                       \
 221 ({                                                              \
 222         typeof(pcp) __retval;                                   \
 223         preempt_disable();                                      \
 224         __retval = (typeof(pcp))operation(raw_cpu_ptr(&(pcp)),  \
 225                                           (val), sizeof(pcp));  \
 226         preempt_enable();                                       \
 227         __retval;                                               \
 228 })
 229
 230 #define _percpu_add(pcp, val) \
 231         _pcp_protect(__percpu_add, pcp, val)
 232
 233 #define _percpu_add_return(pcp, val) _percpu_add(pcp, val)
 234
 235 #define _percpu_and(pcp, val) \
 236         _pcp_protect(__percpu_and, pcp, val)
 237
 238 #define _percpu_or(pcp, val) \
 239         _pcp_protect(__percpu_or, pcp, val)
 240
 241 #define _percpu_xchg(pcp, val) (typeof(pcp)) \
 242         _pcp_protect(__percpu_xchg, pcp, (unsigned long)(val))
 243
 244 #define this_cpu_add_1(pcp, val) _percpu_add(pcp, val)
 245 #define this_cpu_add_2(pcp, val) _percpu_add(pcp, val)
 246 #define this_cpu_add_4(pcp, val) _percpu_add(pcp, val)
 247 #define this_cpu_add_8(pcp, val) _percpu_add(pcp, val)
 248
 249 #define this_cpu_add_return_1(pcp, val) _percpu_add_return(pcp, val)
 250 #define this_cpu_add_return_2(pcp, val) _percpu_add_return(pcp, val)
 251 #define this_cpu_add_return_4(pcp, val) _percpu_add_return(pcp, val)
 252 #define this_cpu_add_return_8(pcp, val) _percpu_add_return(pcp, val)
 253
 254 #define this_cpu_and_1(pcp, val) _percpu_and(pcp, val)
 255 #define this_cpu_and_2(pcp, val) _percpu_and(pcp, val)
 256 #define this_cpu_and_4(pcp, val) _percpu_and(pcp, val)
 257 #define this_cpu_and_8(pcp, val) _percpu_and(pcp, val)
 258
 259 #define this_cpu_or_1(pcp, val) _percpu_or(pcp, val)
 260 #define this_cpu_or_2(pcp, val) _percpu_or(pcp, val)
 261 #define this_cpu_or_4(pcp, val) _percpu_or(pcp, val)
 262 #define this_cpu_or_8(pcp, val) _percpu_or(pcp, val)
 263
 264 #define this_cpu_read_1(pcp) _percpu_read(pcp)
 265 #define this_cpu_read_2(pcp) _percpu_read(pcp)
 266 #define this_cpu_read_4(pcp) _percpu_read(pcp)
 267 #define this_cpu_read_8(pcp) _percpu_read(pcp)
 268
 269 #define this_cpu_write_1(pcp, val) _percpu_write(pcp, val)
 270 #define this_cpu_write_2(pcp, val) _percpu_write(pcp, val)
 271 #define this_cpu_write_4(pcp, val) _percpu_write(pcp, val)
 272 #define this_cpu_write_8(pcp, val) _percpu_write(pcp, val)
 273
 274 #define this_cpu_xchg_1(pcp, val) _percpu_xchg(pcp, val)
 275 #define this_cpu_xchg_2(pcp, val) _percpu_xchg(pcp, val)
 276 #define this_cpu_xchg_4(pcp, val) _percpu_xchg(pcp, val)
 277 #define this_cpu_xchg_8(pcp, val) _percpu_xchg(pcp, val)
 278
 279 #include <asm-generic/percpu.h>
 280
 281 #endif /* __ASM_PERCPU_H */