2 * Based on arch/arm/include/asm/mmu_context.h
4 * Copyright (C) 1996 Russell King.
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #ifndef __ASM_MMU_CONTEXT_H
20 #define __ASM_MMU_CONTEXT_H
24 #include <linux/compiler.h>
25 #include <linux/sched.h>
26 #include <linux/sched/hotplug.h>
27 #include <linux/mm_types.h>
29 #include <asm/cacheflush.h>
30 #include <asm/cpufeature.h>
31 #include <asm/proc-fns.h>
32 #include <asm-generic/mm_hooks.h>
33 #include <asm/cputype.h>
34 #include <asm/pgtable.h>
35 #include <asm/sysreg.h>
36 #include <asm/tlbflush.h>
38 static inline void contextidr_thread_switch(struct task_struct *next)
40 if (!IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR))
43 write_sysreg(task_pid_nr(next), contextidr_el1);
48 * Set TTBR0 to empty_zero_page. No translations will be possible via TTBR0.
50 static inline void cpu_set_reserved_ttbr0(void)
52 unsigned long ttbr = __pa_symbol(empty_zero_page);
54 write_sysreg(ttbr, ttbr0_el1);
58 static inline void cpu_switch_mm(pgd_t *pgd, struct mm_struct *mm)
60 BUG_ON(pgd == swapper_pg_dir);
61 cpu_set_reserved_ttbr0();
62 cpu_do_switch_mm(virt_to_phys(pgd),mm);
66 * TCR.T0SZ value to use when the ID map is active. Usually equals
67 * TCR_T0SZ(VA_BITS), unless system RAM is positioned very high in
68 * physical memory, in which case it will be smaller.
70 extern u64 idmap_t0sz;
72 static inline bool __cpu_uses_extended_idmap(void)
74 return (!IS_ENABLED(CONFIG_ARM64_VA_BITS_48) &&
75 unlikely(idmap_t0sz != TCR_T0SZ(VA_BITS)));
79 * Set TCR.T0SZ to its default value (based on VA_BITS)
81 static inline void __cpu_set_tcr_t0sz(unsigned long t0sz)
85 if (!__cpu_uses_extended_idmap())
88 tcr = read_sysreg(tcr_el1);
89 tcr &= ~TCR_T0SZ_MASK;
90 tcr |= t0sz << TCR_T0SZ_OFFSET;
91 write_sysreg(tcr, tcr_el1);
95 #define cpu_set_default_tcr_t0sz() __cpu_set_tcr_t0sz(TCR_T0SZ(VA_BITS))
96 #define cpu_set_idmap_tcr_t0sz() __cpu_set_tcr_t0sz(idmap_t0sz)
99 * Remove the idmap from TTBR0_EL1 and install the pgd of the active mm.
101 * The idmap lives in the same VA range as userspace, but uses global entries
102 * and may use a different TCR_EL1.T0SZ. To avoid issues resulting from
103 * speculative TLB fetches, we must temporarily install the reserved page
104 * tables while we invalidate the TLBs and set up the correct TCR_EL1.T0SZ.
106 * If current is a not a user task, the mm covers the TTBR1_EL1 page tables,
107 * which should not be installed in TTBR0_EL1. In this case we can leave the
108 * reserved page tables in place.
110 static inline void cpu_uninstall_idmap(void)
112 struct mm_struct *mm = current->active_mm;
114 cpu_set_reserved_ttbr0();
115 local_flush_tlb_all();
116 cpu_set_default_tcr_t0sz();
118 if (mm != &init_mm && !system_uses_ttbr0_pan())
119 cpu_switch_mm(mm->pgd, mm);
122 static inline void cpu_install_idmap(void)
124 cpu_set_reserved_ttbr0();
125 local_flush_tlb_all();
126 cpu_set_idmap_tcr_t0sz();
128 cpu_switch_mm(lm_alias(idmap_pg_dir), &init_mm);
132 * Atomically replaces the active TTBR1_EL1 PGD with a new VA-compatible PGD,
133 * avoiding the possibility of conflicting TLB entries being allocated.
135 static inline void cpu_replace_ttbr1(pgd_t *pgd)
137 typedef void (ttbr_replace_func)(phys_addr_t);
138 extern ttbr_replace_func idmap_cpu_replace_ttbr1;
139 ttbr_replace_func *replace_phys;
141 phys_addr_t pgd_phys = virt_to_phys(pgd);
143 replace_phys = (void *)__pa_symbol(idmap_cpu_replace_ttbr1);
146 replace_phys(pgd_phys);
147 cpu_uninstall_idmap();
151 * It would be nice to return ASIDs back to the allocator, but unfortunately
152 * that introduces a race with a generation rollover where we could erroneously
153 * free an ASID allocated in a future generation. We could workaround this by
154 * freeing the ASID from the context of the dying mm (e.g. in arch_exit_mmap),
155 * but we'd then need to make sure that we didn't dirty any TLBs afterwards.
156 * Setting a reserved TTBR0 or EPD0 would work, but it all gets ugly when you
157 * take CPU migration into account.
159 #define destroy_context(mm) do { } while(0)
160 void check_and_switch_context(struct mm_struct *mm, unsigned int cpu);
162 #define init_new_context(tsk,mm) ({ atomic64_set(&(mm)->context.id, 0); 0; })
164 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
165 static inline void update_saved_ttbr0(struct task_struct *tsk,
166 struct mm_struct *mm)
170 if (!system_uses_ttbr0_pan())
174 ttbr = __pa_symbol(empty_zero_page);
176 ttbr = virt_to_phys(mm->pgd) | ASID(mm) << 48;
178 WRITE_ONCE(task_thread_info(tsk)->ttbr0, ttbr);
181 static inline void update_saved_ttbr0(struct task_struct *tsk,
182 struct mm_struct *mm)
188 enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
191 * We don't actually care about the ttbr0 mapping, so point it at the
194 update_saved_ttbr0(tsk, &init_mm);
197 static inline void __switch_mm(struct mm_struct *next)
199 unsigned int cpu = smp_processor_id();
202 * init_mm.pgd does not contain any user mappings and it is always
203 * active for kernel addresses in TTBR1. Just set the reserved TTBR0.
205 if (next == &init_mm) {
206 cpu_set_reserved_ttbr0();
210 check_and_switch_context(next, cpu);
214 switch_mm(struct mm_struct *prev, struct mm_struct *next,
215 struct task_struct *tsk)
221 * Update the saved TTBR0_EL1 of the scheduled-in task as the previous
222 * value may have not been initialised yet (activate_mm caller) or the
223 * ASID has changed since the last run (following the context switch
224 * of another thread of the same process).
226 update_saved_ttbr0(tsk, next);
229 #define deactivate_mm(tsk,mm) do { } while (0)
230 #define activate_mm(prev,next) switch_mm(prev, next, current)
232 void verify_cpu_asid_bits(void);
233 void post_ttbr_update_workaround(void);
235 #endif /* !__ASSEMBLY__ */
237 #endif /* !__ASM_MMU_CONTEXT_H */