1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
6 * Derived from arch/arm/include/kvm_emulate.h
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
11 #ifndef __ARM64_KVM_EMULATE_H__
12 #define __ARM64_KVM_EMULATE_H__
14 #include <linux/kvm_host.h>
16 #include <asm/debug-monitors.h>
18 #include <asm/kvm_arm.h>
19 #include <asm/kvm_hyp.h>
20 #include <asm/ptrace.h>
21 #include <asm/cputype.h>
24 #define CURRENT_EL_SP_EL0_VECTOR 0x0
25 #define CURRENT_EL_SP_ELx_VECTOR 0x200
26 #define LOWER_EL_AArch64_VECTOR 0x400
27 #define LOWER_EL_AArch32_VECTOR 0x600
31 except_type_irq = 0x80,
32 except_type_fiq = 0x100,
33 except_type_serror = 0x180,
36 #define kvm_exception_type_names \
37 { except_type_sync, "SYNC" }, \
38 { except_type_irq, "IRQ" }, \
39 { except_type_fiq, "FIQ" }, \
40 { except_type_serror, "SERROR" }
42 bool kvm_condition_valid32(const struct kvm_vcpu *vcpu);
43 void kvm_skip_instr32(struct kvm_vcpu *vcpu);
45 void kvm_inject_undefined(struct kvm_vcpu *vcpu);
46 void kvm_inject_vabt(struct kvm_vcpu *vcpu);
47 void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
48 void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
49 void kvm_inject_size_fault(struct kvm_vcpu *vcpu);
51 void kvm_vcpu_wfi(struct kvm_vcpu *vcpu);
53 void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu);
54 int kvm_inject_nested_sync(struct kvm_vcpu *vcpu, u64 esr_el2);
55 int kvm_inject_nested_irq(struct kvm_vcpu *vcpu);
57 static inline bool vcpu_has_feature(const struct kvm_vcpu *vcpu, int feature)
59 return test_bit(feature, vcpu->kvm->arch.vcpu_features);
62 #if defined(__KVM_VHE_HYPERVISOR__) || defined(__KVM_NVHE_HYPERVISOR__)
63 static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu)
65 return !(vcpu->arch.hcr_el2 & HCR_RW);
68 static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu)
70 return vcpu_has_feature(vcpu, KVM_ARM_VCPU_EL1_32BIT);
74 static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
76 vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS;
77 if (has_vhe() || has_hvhe())
78 vcpu->arch.hcr_el2 |= HCR_E2H;
79 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) {
80 /* route synchronous external abort exceptions to EL2 */
81 vcpu->arch.hcr_el2 |= HCR_TEA;
82 /* trap error record accesses */
83 vcpu->arch.hcr_el2 |= HCR_TERR;
86 if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) {
87 vcpu->arch.hcr_el2 |= HCR_FWB;
90 * For non-FWB CPUs, we trap VM ops (HCR_EL2.TVM) until M+C
91 * get set in SCTLR_EL1 such that we can detect when the guest
92 * MMU gets turned on and do the necessary cache maintenance
95 vcpu->arch.hcr_el2 |= HCR_TVM;
98 if (cpus_have_final_cap(ARM64_HAS_EVT) &&
99 !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE))
100 vcpu->arch.hcr_el2 |= HCR_TID4;
102 vcpu->arch.hcr_el2 |= HCR_TID2;
104 if (vcpu_el1_is_32bit(vcpu))
105 vcpu->arch.hcr_el2 &= ~HCR_RW;
107 if (kvm_has_mte(vcpu->kvm))
108 vcpu->arch.hcr_el2 |= HCR_ATA;
111 static inline unsigned long *vcpu_hcr(struct kvm_vcpu *vcpu)
113 return (unsigned long *)&vcpu->arch.hcr_el2;
116 static inline void vcpu_clear_wfx_traps(struct kvm_vcpu *vcpu)
118 vcpu->arch.hcr_el2 &= ~HCR_TWE;
119 if (atomic_read(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe.vlpi_count) ||
120 vcpu->kvm->arch.vgic.nassgireq)
121 vcpu->arch.hcr_el2 &= ~HCR_TWI;
123 vcpu->arch.hcr_el2 |= HCR_TWI;
126 static inline void vcpu_set_wfx_traps(struct kvm_vcpu *vcpu)
128 vcpu->arch.hcr_el2 |= HCR_TWE;
129 vcpu->arch.hcr_el2 |= HCR_TWI;
132 static inline void vcpu_ptrauth_enable(struct kvm_vcpu *vcpu)
134 vcpu->arch.hcr_el2 |= (HCR_API | HCR_APK);
137 static inline void vcpu_ptrauth_disable(struct kvm_vcpu *vcpu)
139 vcpu->arch.hcr_el2 &= ~(HCR_API | HCR_APK);
142 static inline unsigned long vcpu_get_vsesr(struct kvm_vcpu *vcpu)
144 return vcpu->arch.vsesr_el2;
147 static inline void vcpu_set_vsesr(struct kvm_vcpu *vcpu, u64 vsesr)
149 vcpu->arch.vsesr_el2 = vsesr;
152 static __always_inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu)
154 return (unsigned long *)&vcpu_gp_regs(vcpu)->pc;
157 static __always_inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu)
159 return (unsigned long *)&vcpu_gp_regs(vcpu)->pstate;
162 static __always_inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu)
164 return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT);
167 static __always_inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu)
169 if (vcpu_mode_is_32bit(vcpu))
170 return kvm_condition_valid32(vcpu);
175 static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
177 *vcpu_cpsr(vcpu) |= PSR_AA32_T_BIT;
181 * vcpu_get_reg and vcpu_set_reg should always be passed a register number
182 * coming from a read of ESR_EL2. Otherwise, it may give the wrong result on
183 * AArch32 with banked registers.
185 static __always_inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu,
188 return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
191 static __always_inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num,
195 vcpu_gp_regs(vcpu)->regs[reg_num] = val;
198 static inline bool vcpu_is_el2_ctxt(const struct kvm_cpu_context *ctxt)
200 switch (ctxt->regs.pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) {
209 static inline bool vcpu_is_el2(const struct kvm_vcpu *vcpu)
211 return vcpu_is_el2_ctxt(&vcpu->arch.ctxt);
214 static inline bool __vcpu_el2_e2h_is_set(const struct kvm_cpu_context *ctxt)
216 return ctxt_sys_reg(ctxt, HCR_EL2) & HCR_E2H;
219 static inline bool vcpu_el2_e2h_is_set(const struct kvm_vcpu *vcpu)
221 return __vcpu_el2_e2h_is_set(&vcpu->arch.ctxt);
224 static inline bool __vcpu_el2_tge_is_set(const struct kvm_cpu_context *ctxt)
226 return ctxt_sys_reg(ctxt, HCR_EL2) & HCR_TGE;
229 static inline bool vcpu_el2_tge_is_set(const struct kvm_vcpu *vcpu)
231 return __vcpu_el2_tge_is_set(&vcpu->arch.ctxt);
234 static inline bool __is_hyp_ctxt(const struct kvm_cpu_context *ctxt)
237 * We are in a hypervisor context if the vcpu mode is EL2 or
238 * E2H and TGE bits are set. The latter means we are in the user space
239 * of the VHE kernel. ARMv8.1 ARM describes this as 'InHost'
241 * Note that the HCR_EL2.{E2H,TGE}={0,1} isn't really handled in the
242 * rest of the KVM code, and will result in a misbehaving guest.
244 return vcpu_is_el2_ctxt(ctxt) ||
245 (__vcpu_el2_e2h_is_set(ctxt) && __vcpu_el2_tge_is_set(ctxt)) ||
246 __vcpu_el2_tge_is_set(ctxt);
249 static inline bool is_hyp_ctxt(const struct kvm_vcpu *vcpu)
251 return __is_hyp_ctxt(&vcpu->arch.ctxt);
255 * The layout of SPSR for an AArch32 state is different when observed from an
256 * AArch64 SPSR_ELx or an AArch32 SPSR_*. This function generates the AArch32
257 * view given an AArch64 view.
259 * In ARM DDI 0487E.a see:
261 * - The AArch64 view (SPSR_EL2) in section C5.2.18, page C5-426
262 * - The AArch32 view (SPSR_abt) in section G8.2.126, page G8-6256
263 * - The AArch32 view (SPSR_und) in section G8.2.132, page G8-6280
265 * Which show the following differences:
267 * | Bit | AA64 | AA32 | Notes |
268 * +-----+------+------+-----------------------------|
269 * | 24 | DIT | J | J is RES0 in ARMv8 |
270 * | 21 | SS | DIT | SS doesn't exist in AArch32 |
272 * ... and all other bits are (currently) common.
274 static inline unsigned long host_spsr_to_spsr32(unsigned long spsr)
276 const unsigned long overlap = BIT(24) | BIT(21);
277 unsigned long dit = !!(spsr & PSR_AA32_DIT_BIT);
286 static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu)
290 if (vcpu_mode_is_32bit(vcpu)) {
291 mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK;
292 return mode > PSR_AA32_MODE_USR;
295 mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK;
297 return mode != PSR_MODE_EL0t;
300 static __always_inline u64 kvm_vcpu_get_esr(const struct kvm_vcpu *vcpu)
302 return vcpu->arch.fault.esr_el2;
305 static __always_inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu)
307 u64 esr = kvm_vcpu_get_esr(vcpu);
309 if (esr & ESR_ELx_CV)
310 return (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT;
315 static __always_inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu)
317 return vcpu->arch.fault.far_el2;
320 static __always_inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu)
322 return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8;
325 static inline u64 kvm_vcpu_get_disr(const struct kvm_vcpu *vcpu)
327 return vcpu->arch.fault.disr_el1;
330 static inline u32 kvm_vcpu_hvc_get_imm(const struct kvm_vcpu *vcpu)
332 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_xVC_IMM_MASK;
335 static __always_inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu)
337 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_ISV);
340 static inline unsigned long kvm_vcpu_dabt_iss_nisv_sanitized(const struct kvm_vcpu *vcpu)
342 return kvm_vcpu_get_esr(vcpu) & (ESR_ELx_CM | ESR_ELx_WNR | ESR_ELx_FSC);
345 static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu)
347 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SSE);
350 static inline bool kvm_vcpu_dabt_issf(const struct kvm_vcpu *vcpu)
352 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SF);
355 static __always_inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu)
357 return (kvm_vcpu_get_esr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT;
360 static __always_inline bool kvm_vcpu_abt_iss1tw(const struct kvm_vcpu *vcpu)
362 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_S1PTW);
365 /* Always check for S1PTW *before* using this. */
366 static __always_inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu)
368 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_WNR;
371 static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu)
373 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_CM);
376 static __always_inline unsigned int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu)
378 return 1 << ((kvm_vcpu_get_esr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT);
381 /* This one is not specific to Data Abort */
382 static __always_inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu)
384 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_IL);
387 static __always_inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu)
389 return ESR_ELx_EC(kvm_vcpu_get_esr(vcpu));
392 static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu)
394 return kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_IABT_LOW;
397 static inline bool kvm_vcpu_trap_is_exec_fault(const struct kvm_vcpu *vcpu)
399 return kvm_vcpu_trap_is_iabt(vcpu) && !kvm_vcpu_abt_iss1tw(vcpu);
402 static __always_inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu)
404 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC;
407 static __always_inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vcpu)
409 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC_TYPE;
412 static __always_inline u8 kvm_vcpu_trap_get_fault_level(const struct kvm_vcpu *vcpu)
414 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC_LEVEL;
417 static __always_inline bool kvm_vcpu_abt_issea(const struct kvm_vcpu *vcpu)
419 switch (kvm_vcpu_trap_get_fault(vcpu)) {
420 case ESR_ELx_FSC_EXTABT:
421 case ESR_ELx_FSC_SEA_TTW0:
422 case ESR_ELx_FSC_SEA_TTW1:
423 case ESR_ELx_FSC_SEA_TTW2:
424 case ESR_ELx_FSC_SEA_TTW3:
425 case ESR_ELx_FSC_SECC:
426 case ESR_ELx_FSC_SECC_TTW0:
427 case ESR_ELx_FSC_SECC_TTW1:
428 case ESR_ELx_FSC_SECC_TTW2:
429 case ESR_ELx_FSC_SECC_TTW3:
436 static __always_inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu)
438 u64 esr = kvm_vcpu_get_esr(vcpu);
439 return ESR_ELx_SYS64_ISS_RT(esr);
442 static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu)
444 if (kvm_vcpu_abt_iss1tw(vcpu)) {
446 * Only a permission fault on a S1PTW should be
447 * considered as a write. Otherwise, page tables baked
448 * in a read-only memslot will result in an exception
449 * being delivered in the guest.
451 * The drawback is that we end-up faulting twice if the
452 * guest is using any of HW AF/DB: a translation fault
453 * to map the page containing the PT (read only at
454 * first), then a permission fault to allow the flags
457 switch (kvm_vcpu_trap_get_fault_type(vcpu)) {
458 case ESR_ELx_FSC_PERM:
465 if (kvm_vcpu_trap_is_iabt(vcpu))
468 return kvm_vcpu_dabt_iswrite(vcpu);
471 static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu)
473 return __vcpu_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK;
476 static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu)
478 if (vcpu_mode_is_32bit(vcpu)) {
479 *vcpu_cpsr(vcpu) |= PSR_AA32_E_BIT;
481 u64 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1);
482 sctlr |= SCTLR_ELx_EE;
483 vcpu_write_sys_reg(vcpu, sctlr, SCTLR_EL1);
487 static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu)
489 if (vcpu_mode_is_32bit(vcpu))
490 return !!(*vcpu_cpsr(vcpu) & PSR_AA32_E_BIT);
492 if (vcpu_mode_priv(vcpu))
493 return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_ELx_EE);
495 return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_EL1_E0E);
498 static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu,
502 if (kvm_vcpu_is_be(vcpu)) {
507 return be16_to_cpu(data & 0xffff);
509 return be32_to_cpu(data & 0xffffffff);
511 return be64_to_cpu(data);
518 return le16_to_cpu(data & 0xffff);
520 return le32_to_cpu(data & 0xffffffff);
522 return le64_to_cpu(data);
526 return data; /* Leave LE untouched */
529 static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu,
533 if (kvm_vcpu_is_be(vcpu)) {
538 return cpu_to_be16(data & 0xffff);
540 return cpu_to_be32(data & 0xffffffff);
542 return cpu_to_be64(data);
549 return cpu_to_le16(data & 0xffff);
551 return cpu_to_le32(data & 0xffffffff);
553 return cpu_to_le64(data);
557 return data; /* Leave LE untouched */
560 static __always_inline void kvm_incr_pc(struct kvm_vcpu *vcpu)
562 WARN_ON(vcpu_get_flag(vcpu, PENDING_EXCEPTION));
563 vcpu_set_flag(vcpu, INCREMENT_PC);
566 #define kvm_pend_exception(v, e) \
568 WARN_ON(vcpu_get_flag((v), INCREMENT_PC)); \
569 vcpu_set_flag((v), PENDING_EXCEPTION); \
570 vcpu_set_flag((v), e); \
573 static __always_inline void kvm_write_cptr_el2(u64 val)
575 if (has_vhe() || has_hvhe())
576 write_sysreg(val, cpacr_el1);
578 write_sysreg(val, cptr_el2);
581 static __always_inline u64 kvm_get_reset_cptr_el2(struct kvm_vcpu *vcpu)
586 val = (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN |
587 CPACR_EL1_ZEN_EL1EN);
588 if (cpus_have_final_cap(ARM64_SME))
589 val |= CPACR_EL1_SMEN_EL1EN;
590 } else if (has_hvhe()) {
591 val = (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN);
593 if (!vcpu_has_sve(vcpu) ||
594 (vcpu->arch.fp_state != FP_STATE_GUEST_OWNED))
595 val |= CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN;
596 if (cpus_have_final_cap(ARM64_SME))
597 val |= CPACR_EL1_SMEN_EL1EN | CPACR_EL1_SMEN_EL0EN;
599 val = CPTR_NVHE_EL2_RES1;
601 if (vcpu_has_sve(vcpu) &&
602 (vcpu->arch.fp_state == FP_STATE_GUEST_OWNED))
604 if (cpus_have_final_cap(ARM64_SME))
605 val &= ~CPTR_EL2_TSM;
611 static __always_inline void kvm_reset_cptr_el2(struct kvm_vcpu *vcpu)
613 u64 val = kvm_get_reset_cptr_el2(vcpu);
615 kvm_write_cptr_el2(val);
617 #endif /* __ARM64_KVM_EMULATE_H__ */