1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
6 * Derived from arch/arm/include/kvm_emulate.h
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
11 #ifndef __ARM64_KVM_EMULATE_H__
12 #define __ARM64_KVM_EMULATE_H__
14 #include <linux/kvm_host.h>
16 #include <asm/debug-monitors.h>
18 #include <asm/kvm_arm.h>
19 #include <asm/kvm_hyp.h>
20 #include <asm/ptrace.h>
21 #include <asm/cputype.h>
24 #define CURRENT_EL_SP_EL0_VECTOR 0x0
25 #define CURRENT_EL_SP_ELx_VECTOR 0x200
26 #define LOWER_EL_AArch64_VECTOR 0x400
27 #define LOWER_EL_AArch32_VECTOR 0x600
31 except_type_irq = 0x80,
32 except_type_fiq = 0x100,
33 except_type_serror = 0x180,
36 bool kvm_condition_valid32(const struct kvm_vcpu *vcpu);
37 void kvm_skip_instr32(struct kvm_vcpu *vcpu);
39 void kvm_inject_undefined(struct kvm_vcpu *vcpu);
40 void kvm_inject_vabt(struct kvm_vcpu *vcpu);
41 void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
42 void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
43 void kvm_inject_size_fault(struct kvm_vcpu *vcpu);
45 void kvm_vcpu_wfi(struct kvm_vcpu *vcpu);
47 #if defined(__KVM_VHE_HYPERVISOR__) || defined(__KVM_NVHE_HYPERVISOR__)
48 static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu)
50 return !(vcpu->arch.hcr_el2 & HCR_RW);
53 static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu)
55 struct kvm *kvm = vcpu->kvm;
57 WARN_ON_ONCE(!test_bit(KVM_ARCH_FLAG_REG_WIDTH_CONFIGURED,
60 return test_bit(KVM_ARCH_FLAG_EL1_32BIT, &kvm->arch.flags);
64 static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
66 vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS;
67 if (is_kernel_in_hyp_mode())
68 vcpu->arch.hcr_el2 |= HCR_E2H;
69 if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN)) {
70 /* route synchronous external abort exceptions to EL2 */
71 vcpu->arch.hcr_el2 |= HCR_TEA;
72 /* trap error record accesses */
73 vcpu->arch.hcr_el2 |= HCR_TERR;
76 if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) {
77 vcpu->arch.hcr_el2 |= HCR_FWB;
80 * For non-FWB CPUs, we trap VM ops (HCR_EL2.TVM) until M+C
81 * get set in SCTLR_EL1 such that we can detect when the guest
82 * MMU gets turned on and do the necessary cache maintenance
85 vcpu->arch.hcr_el2 |= HCR_TVM;
88 if (vcpu_el1_is_32bit(vcpu))
89 vcpu->arch.hcr_el2 &= ~HCR_RW;
91 if (cpus_have_const_cap(ARM64_MISMATCHED_CACHE_TYPE) ||
92 vcpu_el1_is_32bit(vcpu))
93 vcpu->arch.hcr_el2 |= HCR_TID2;
95 if (kvm_has_mte(vcpu->kvm))
96 vcpu->arch.hcr_el2 |= HCR_ATA;
99 static inline unsigned long *vcpu_hcr(struct kvm_vcpu *vcpu)
101 return (unsigned long *)&vcpu->arch.hcr_el2;
104 static inline void vcpu_clear_wfx_traps(struct kvm_vcpu *vcpu)
106 vcpu->arch.hcr_el2 &= ~HCR_TWE;
107 if (atomic_read(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe.vlpi_count) ||
108 vcpu->kvm->arch.vgic.nassgireq)
109 vcpu->arch.hcr_el2 &= ~HCR_TWI;
111 vcpu->arch.hcr_el2 |= HCR_TWI;
114 static inline void vcpu_set_wfx_traps(struct kvm_vcpu *vcpu)
116 vcpu->arch.hcr_el2 |= HCR_TWE;
117 vcpu->arch.hcr_el2 |= HCR_TWI;
120 static inline void vcpu_ptrauth_enable(struct kvm_vcpu *vcpu)
122 vcpu->arch.hcr_el2 |= (HCR_API | HCR_APK);
125 static inline void vcpu_ptrauth_disable(struct kvm_vcpu *vcpu)
127 vcpu->arch.hcr_el2 &= ~(HCR_API | HCR_APK);
130 static inline unsigned long vcpu_get_vsesr(struct kvm_vcpu *vcpu)
132 return vcpu->arch.vsesr_el2;
135 static inline void vcpu_set_vsesr(struct kvm_vcpu *vcpu, u64 vsesr)
137 vcpu->arch.vsesr_el2 = vsesr;
140 static __always_inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu)
142 return (unsigned long *)&vcpu_gp_regs(vcpu)->pc;
145 static __always_inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu)
147 return (unsigned long *)&vcpu_gp_regs(vcpu)->pstate;
150 static __always_inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu)
152 return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT);
155 static __always_inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu)
157 if (vcpu_mode_is_32bit(vcpu))
158 return kvm_condition_valid32(vcpu);
163 static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
165 *vcpu_cpsr(vcpu) |= PSR_AA32_T_BIT;
169 * vcpu_get_reg and vcpu_set_reg should always be passed a register number
170 * coming from a read of ESR_EL2. Otherwise, it may give the wrong result on
171 * AArch32 with banked registers.
173 static __always_inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu,
176 return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
179 static __always_inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num,
183 vcpu_gp_regs(vcpu)->regs[reg_num] = val;
187 * The layout of SPSR for an AArch32 state is different when observed from an
188 * AArch64 SPSR_ELx or an AArch32 SPSR_*. This function generates the AArch32
189 * view given an AArch64 view.
191 * In ARM DDI 0487E.a see:
193 * - The AArch64 view (SPSR_EL2) in section C5.2.18, page C5-426
194 * - The AArch32 view (SPSR_abt) in section G8.2.126, page G8-6256
195 * - The AArch32 view (SPSR_und) in section G8.2.132, page G8-6280
197 * Which show the following differences:
199 * | Bit | AA64 | AA32 | Notes |
200 * +-----+------+------+-----------------------------|
201 * | 24 | DIT | J | J is RES0 in ARMv8 |
202 * | 21 | SS | DIT | SS doesn't exist in AArch32 |
204 * ... and all other bits are (currently) common.
206 static inline unsigned long host_spsr_to_spsr32(unsigned long spsr)
208 const unsigned long overlap = BIT(24) | BIT(21);
209 unsigned long dit = !!(spsr & PSR_AA32_DIT_BIT);
218 static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu)
222 if (vcpu_mode_is_32bit(vcpu)) {
223 mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK;
224 return mode > PSR_AA32_MODE_USR;
227 mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK;
229 return mode != PSR_MODE_EL0t;
232 static __always_inline u64 kvm_vcpu_get_esr(const struct kvm_vcpu *vcpu)
234 return vcpu->arch.fault.esr_el2;
237 static __always_inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu)
239 u64 esr = kvm_vcpu_get_esr(vcpu);
241 if (esr & ESR_ELx_CV)
242 return (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT;
247 static __always_inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu)
249 return vcpu->arch.fault.far_el2;
252 static __always_inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu)
254 return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8;
257 static inline u64 kvm_vcpu_get_disr(const struct kvm_vcpu *vcpu)
259 return vcpu->arch.fault.disr_el1;
262 static inline u32 kvm_vcpu_hvc_get_imm(const struct kvm_vcpu *vcpu)
264 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_xVC_IMM_MASK;
267 static __always_inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu)
269 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_ISV);
272 static inline unsigned long kvm_vcpu_dabt_iss_nisv_sanitized(const struct kvm_vcpu *vcpu)
274 return kvm_vcpu_get_esr(vcpu) & (ESR_ELx_CM | ESR_ELx_WNR | ESR_ELx_FSC);
277 static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu)
279 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SSE);
282 static inline bool kvm_vcpu_dabt_issf(const struct kvm_vcpu *vcpu)
284 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SF);
287 static __always_inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu)
289 return (kvm_vcpu_get_esr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT;
292 static __always_inline bool kvm_vcpu_abt_iss1tw(const struct kvm_vcpu *vcpu)
294 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_S1PTW);
297 /* Always check for S1PTW *before* using this. */
298 static __always_inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu)
300 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_WNR;
303 static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu)
305 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_CM);
308 static __always_inline unsigned int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu)
310 return 1 << ((kvm_vcpu_get_esr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT);
313 /* This one is not specific to Data Abort */
314 static __always_inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu)
316 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_IL);
319 static __always_inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu)
321 return ESR_ELx_EC(kvm_vcpu_get_esr(vcpu));
324 static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu)
326 return kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_IABT_LOW;
329 static inline bool kvm_vcpu_trap_is_exec_fault(const struct kvm_vcpu *vcpu)
331 return kvm_vcpu_trap_is_iabt(vcpu) && !kvm_vcpu_abt_iss1tw(vcpu);
334 static __always_inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu)
336 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC;
339 static __always_inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vcpu)
341 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC_TYPE;
344 static __always_inline u8 kvm_vcpu_trap_get_fault_level(const struct kvm_vcpu *vcpu)
346 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC_LEVEL;
349 static __always_inline bool kvm_vcpu_abt_issea(const struct kvm_vcpu *vcpu)
351 switch (kvm_vcpu_trap_get_fault(vcpu)) {
368 static __always_inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu)
370 u64 esr = kvm_vcpu_get_esr(vcpu);
371 return ESR_ELx_SYS64_ISS_RT(esr);
374 static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu)
376 if (kvm_vcpu_abt_iss1tw(vcpu))
379 if (kvm_vcpu_trap_is_iabt(vcpu))
382 return kvm_vcpu_dabt_iswrite(vcpu);
385 static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu)
387 return vcpu_read_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK;
390 static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu)
392 if (vcpu_mode_is_32bit(vcpu)) {
393 *vcpu_cpsr(vcpu) |= PSR_AA32_E_BIT;
395 u64 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1);
396 sctlr |= SCTLR_ELx_EE;
397 vcpu_write_sys_reg(vcpu, sctlr, SCTLR_EL1);
401 static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu)
403 if (vcpu_mode_is_32bit(vcpu))
404 return !!(*vcpu_cpsr(vcpu) & PSR_AA32_E_BIT);
406 if (vcpu_mode_priv(vcpu))
407 return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_ELx_EE);
409 return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_EL1_E0E);
412 static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu,
416 if (kvm_vcpu_is_be(vcpu)) {
421 return be16_to_cpu(data & 0xffff);
423 return be32_to_cpu(data & 0xffffffff);
425 return be64_to_cpu(data);
432 return le16_to_cpu(data & 0xffff);
434 return le32_to_cpu(data & 0xffffffff);
436 return le64_to_cpu(data);
440 return data; /* Leave LE untouched */
443 static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu,
447 if (kvm_vcpu_is_be(vcpu)) {
452 return cpu_to_be16(data & 0xffff);
454 return cpu_to_be32(data & 0xffffffff);
456 return cpu_to_be64(data);
463 return cpu_to_le16(data & 0xffff);
465 return cpu_to_le32(data & 0xffffffff);
467 return cpu_to_le64(data);
471 return data; /* Leave LE untouched */
474 static __always_inline void kvm_incr_pc(struct kvm_vcpu *vcpu)
476 vcpu->arch.flags |= KVM_ARM64_INCREMENT_PC;
479 static inline bool vcpu_has_feature(struct kvm_vcpu *vcpu, int feature)
481 return test_bit(feature, vcpu->arch.features);
484 #endif /* __ARM64_KVM_EMULATE_H__ */