2 * Copyright (C) 2012 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 #ifndef __ASM_HW_BREAKPOINT_H
17 #define __ASM_HW_BREAKPOINT_H
19 #include <asm/cputype.h>
20 #include <asm/cpufeature.h>
21 #include <asm/sysreg.h>
26 struct arch_hw_breakpoint_ctrl {
34 struct arch_hw_breakpoint {
37 struct arch_hw_breakpoint_ctrl ctrl;
40 /* Privilege Levels */
41 #define AARCH64_BREAKPOINT_EL1 1
42 #define AARCH64_BREAKPOINT_EL0 2
44 #define DBG_HMC_HYP (1 << 13)
46 static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
48 u32 val = (ctrl.len << 5) | (ctrl.type << 3) | (ctrl.privilege << 1) |
51 if (is_kernel_in_hyp_mode() && ctrl.privilege == AARCH64_BREAKPOINT_EL1)
57 static inline void decode_ctrl_reg(u32 reg,
58 struct arch_hw_breakpoint_ctrl *ctrl)
60 ctrl->enabled = reg & 0x1;
62 ctrl->privilege = reg & 0x3;
64 ctrl->type = reg & 0x3;
66 ctrl->len = reg & 0xff;
70 #define ARM_BREAKPOINT_EXECUTE 0
73 #define ARM_BREAKPOINT_LOAD 1
74 #define ARM_BREAKPOINT_STORE 2
75 #define AARCH64_ESR_ACCESS_MASK (1 << 6)
78 #define ARM_BREAKPOINT_LEN_1 0x1
79 #define ARM_BREAKPOINT_LEN_2 0x3
80 #define ARM_BREAKPOINT_LEN_3 0x7
81 #define ARM_BREAKPOINT_LEN_4 0xf
82 #define ARM_BREAKPOINT_LEN_5 0x1f
83 #define ARM_BREAKPOINT_LEN_6 0x3f
84 #define ARM_BREAKPOINT_LEN_7 0x7f
85 #define ARM_BREAKPOINT_LEN_8 0xff
88 #define ARM_KERNEL_STEP_NONE 0
89 #define ARM_KERNEL_STEP_ACTIVE 1
90 #define ARM_KERNEL_STEP_SUSPEND 2
94 * Changing these will require modifications to the register accessors.
96 #define ARM_MAX_BRP 16
97 #define ARM_MAX_WRP 16
99 /* Virtual debug register bases. */
100 #define AARCH64_DBG_REG_BVR 0
101 #define AARCH64_DBG_REG_BCR (AARCH64_DBG_REG_BVR + ARM_MAX_BRP)
102 #define AARCH64_DBG_REG_WVR (AARCH64_DBG_REG_BCR + ARM_MAX_BRP)
103 #define AARCH64_DBG_REG_WCR (AARCH64_DBG_REG_WVR + ARM_MAX_WRP)
105 /* Debug register names. */
106 #define AARCH64_DBG_REG_NAME_BVR bvr
107 #define AARCH64_DBG_REG_NAME_BCR bcr
108 #define AARCH64_DBG_REG_NAME_WVR wvr
109 #define AARCH64_DBG_REG_NAME_WCR wcr
111 /* Accessor macros for the debug registers. */
112 #define AARCH64_DBG_READ(N, REG, VAL) do {\
113 VAL = read_sysreg(dbg##REG##N##_el1);\
116 #define AARCH64_DBG_WRITE(N, REG, VAL) do {\
117 write_sysreg(VAL, dbg##REG##N##_el1);\
121 struct notifier_block;
125 extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
126 int *gen_len, int *gen_type, int *offset);
127 extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
128 extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
129 extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
130 unsigned long val, void *data);
132 extern int arch_install_hw_breakpoint(struct perf_event *bp);
133 extern void arch_uninstall_hw_breakpoint(struct perf_event *bp);
134 extern void hw_breakpoint_pmu_read(struct perf_event *bp);
135 extern int hw_breakpoint_slots(int type);
137 #ifdef CONFIG_HAVE_HW_BREAKPOINT
138 extern void hw_breakpoint_thread_switch(struct task_struct *next);
139 extern void ptrace_hw_copy_thread(struct task_struct *task);
141 static inline void hw_breakpoint_thread_switch(struct task_struct *next)
144 static inline void ptrace_hw_copy_thread(struct task_struct *task)
149 /* Determine number of BRP registers available. */
150 static inline int get_num_brps(void)
152 u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
154 cpuid_feature_extract_unsigned_field(dfr0,
155 ID_AA64DFR0_BRPS_SHIFT);
158 /* Determine number of WRP registers available. */
159 static inline int get_num_wrps(void)
161 u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
163 cpuid_feature_extract_unsigned_field(dfr0,
164 ID_AA64DFR0_WRPS_SHIFT);
167 #endif /* __KERNEL__ */
168 #endif /* __ASM_BREAKPOINT_H */