1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
6 #ifndef __ASM_CPUFEATURE_H
7 #define __ASM_CPUFEATURE_H
9 #include <asm/alternative-macros.h>
10 #include <asm/cpucaps.h>
11 #include <asm/cputype.h>
12 #include <asm/hwcap.h>
13 #include <asm/sysreg.h>
15 #define MAX_CPU_FEATURES 128
16 #define cpu_feature(x) KERNEL_HWCAP_ ## x
18 #define ARM64_SW_FEATURE_OVERRIDE_NOKASLR 0
19 #define ARM64_SW_FEATURE_OVERRIDE_HVHE 4
23 #include <linux/bug.h>
24 #include <linux/jump_label.h>
25 #include <linux/kernel.h>
26 #include <linux/cpumask.h>
29 * CPU feature register tracking
31 * The safe value of a CPUID feature field is dependent on the implications
32 * of the values assigned to it by the architecture. Based on the relationship
33 * between the values, the features are classified into 3 types - LOWER_SAFE,
34 * HIGHER_SAFE and EXACT.
36 * The lowest value of all the CPUs is chosen for LOWER_SAFE and highest
37 * for HIGHER_SAFE. It is expected that all CPUs have the same value for
38 * a field when EXACT is specified, failing which, the safe value specified
39 * in the table is chosen.
43 FTR_EXACT, /* Use a predefined safe value */
44 FTR_LOWER_SAFE, /* Smaller value is safe */
45 FTR_HIGHER_SAFE, /* Bigger value is safe */
46 FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */
49 #define FTR_STRICT true /* SANITY check strict matching required */
50 #define FTR_NONSTRICT false /* SANITY check ignored */
52 #define FTR_SIGNED true /* Value should be treated as signed */
53 #define FTR_UNSIGNED false /* Value should be treated as unsigned */
55 #define FTR_VISIBLE true /* Feature visible to the user space */
56 #define FTR_HIDDEN false /* Feature is hidden from the user */
58 #define FTR_VISIBLE_IF_IS_ENABLED(config) \
59 (IS_ENABLED(config) ? FTR_VISIBLE : FTR_HIDDEN)
61 struct arm64_ftr_bits {
62 bool sign; /* Value is signed ? */
64 bool strict; /* CPU Sanity check: strict matching required ? */
68 s64 safe_val; /* safe value for FTR_EXACT features */
72 * Describe the early feature override to the core override code:
74 * @val Values that are to be merged into the final
75 * sanitised value of the register. Only the bitfields
76 * set to 1 in @mask are valid
77 * @mask Mask of the features that are overridden by @val
79 * A @mask field set to full-1 indicates that the corresponding field
80 * in @val is a valid override.
82 * A @mask field set to full-0 with the corresponding @val field set
83 * to full-0 denotes that this field has no override
85 * A @mask field set to full-0 with the corresponding @val field set
86 * to full-1 denotes thath this field has an invalid override.
88 struct arm64_ftr_override {
94 * @arm64_ftr_reg - Feature register
95 * @strict_mask Bits which should match across all CPUs for sanity.
96 * @sys_val Safe value across the CPUs (system view)
98 struct arm64_ftr_reg {
104 struct arm64_ftr_override *override;
105 const struct arm64_ftr_bits *ftr_bits;
108 extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0;
113 * We use arm64_cpu_capabilities to represent system features, errata work
114 * arounds (both used internally by kernel and tracked in system_cpucaps) and
115 * ELF HWCAPs (which are exposed to user).
117 * To support systems with heterogeneous CPUs, we need to make sure that we
118 * detect the capabilities correctly on the system and take appropriate
119 * measures to ensure there are no incompatibilities.
121 * This comment tries to explain how we treat the capabilities.
122 * Each capability has the following list of attributes :
124 * 1) Scope of Detection : The system detects a given capability by
125 * performing some checks at runtime. This could be, e.g, checking the
126 * value of a field in CPU ID feature register or checking the cpu
127 * model. The capability provides a call back ( @matches() ) to
128 * perform the check. Scope defines how the checks should be performed.
129 * There are three cases:
131 * a) SCOPE_LOCAL_CPU: check all the CPUs and "detect" if at least one
132 * matches. This implies, we have to run the check on all the
133 * booting CPUs, until the system decides that state of the
134 * capability is finalised. (See section 2 below)
136 * b) SCOPE_SYSTEM: check all the CPUs and "detect" if all the CPUs
137 * matches. This implies, we run the check only once, when the
138 * system decides to finalise the state of the capability. If the
139 * capability relies on a field in one of the CPU ID feature
140 * registers, we use the sanitised value of the register from the
141 * CPU feature infrastructure to make the decision.
143 * c) SCOPE_BOOT_CPU: Check only on the primary boot CPU to detect the
144 * feature. This category is for features that are "finalised"
145 * (or used) by the kernel very early even before the SMP cpus
148 * The process of detection is usually denoted by "update" capability
151 * 2) Finalise the state : The kernel should finalise the state of a
152 * capability at some point during its execution and take necessary
153 * actions if any. Usually, this is done, after all the boot-time
154 * enabled CPUs are brought up by the kernel, so that it can make
155 * better decision based on the available set of CPUs. However, there
156 * are some special cases, where the action is taken during the early
157 * boot by the primary boot CPU. (e.g, running the kernel at EL2 with
158 * Virtualisation Host Extensions). The kernel usually disallows any
159 * changes to the state of a capability once it finalises the capability
160 * and takes any action, as it may be impossible to execute the actions
161 * safely. A CPU brought up after a capability is "finalised" is
162 * referred to as "Late CPU" w.r.t the capability. e.g, all secondary
163 * CPUs are treated "late CPUs" for capabilities determined by the boot
166 * At the moment there are two passes of finalising the capabilities.
167 * a) Boot CPU scope capabilities - Finalised by primary boot CPU via
168 * setup_boot_cpu_capabilities().
169 * b) Everything except (a) - Run via setup_system_capabilities().
171 * 3) Verification: When a CPU is brought online (e.g, by user or by the
172 * kernel), the kernel should make sure that it is safe to use the CPU,
173 * by verifying that the CPU is compliant with the state of the
174 * capabilities finalised already. This happens via :
176 * secondary_start_kernel()-> check_local_cpu_capabilities()
178 * As explained in (2) above, capabilities could be finalised at
179 * different points in the execution. Each newly booted CPU is verified
180 * against the capabilities that have been finalised by the time it
183 * a) SCOPE_BOOT_CPU : All CPUs are verified against the capability
184 * except for the primary boot CPU.
186 * b) SCOPE_LOCAL_CPU, SCOPE_SYSTEM: All CPUs hotplugged on by the
187 * user after the kernel boot are verified against the capability.
189 * If there is a conflict, the kernel takes an action, based on the
190 * severity (e.g, a CPU could be prevented from booting or cause a
191 * kernel panic). The CPU is allowed to "affect" the state of the
192 * capability, if it has not been finalised already. See section 5
193 * for more details on conflicts.
195 * 4) Action: As mentioned in (2), the kernel can take an action for each
196 * detected capability, on all CPUs on the system. Appropriate actions
197 * include, turning on an architectural feature, modifying the control
198 * registers (e.g, SCTLR, TCR etc.) or patching the kernel via
199 * alternatives. The kernel patching is batched and performed at later
200 * point. The actions are always initiated only after the capability
201 * is finalised. This is usally denoted by "enabling" the capability.
202 * The actions are initiated as follows :
203 * a) Action is triggered on all online CPUs, after the capability is
204 * finalised, invoked within the stop_machine() context from
205 * enable_cpu_capabilitie().
207 * b) Any late CPU, brought up after (1), the action is triggered via:
209 * check_local_cpu_capabilities() -> verify_local_cpu_capabilities()
211 * 5) Conflicts: Based on the state of the capability on a late CPU vs.
212 * the system state, we could have the following combinations :
214 * x-----------------------------x
215 * | Type | System | Late CPU |
216 * |-----------------------------|
218 * |-----------------------------|
220 * x-----------------------------x
222 * Two separate flag bits are defined to indicate whether each kind of
223 * conflict can be allowed:
224 * ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU - Case(a) is allowed
225 * ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU - Case(b) is allowed
227 * Case (a) is not permitted for a capability that the system requires
228 * all CPUs to have in order for the capability to be enabled. This is
229 * typical for capabilities that represent enhanced functionality.
231 * Case (b) is not permitted for a capability that must be enabled
232 * during boot if any CPU in the system requires it in order to run
233 * safely. This is typical for erratum work arounds that cannot be
234 * enabled after the corresponding capability is finalised.
236 * In some non-typical cases either both (a) and (b), or neither,
237 * should be permitted. This can be described by including neither
238 * or both flags in the capability's type field.
240 * In case of a conflict, the CPU is prevented from booting. If the
241 * ARM64_CPUCAP_PANIC_ON_CONFLICT flag is specified for the capability,
242 * then a kernel panic is triggered.
247 * Decide how the capability is detected.
248 * On any local CPU vs System wide vs the primary boot CPU
250 #define ARM64_CPUCAP_SCOPE_LOCAL_CPU ((u16)BIT(0))
251 #define ARM64_CPUCAP_SCOPE_SYSTEM ((u16)BIT(1))
253 * The capabilitiy is detected on the Boot CPU and is used by kernel
254 * during early boot. i.e, the capability should be "detected" and
255 * "enabled" as early as possibly on all booting CPUs.
257 #define ARM64_CPUCAP_SCOPE_BOOT_CPU ((u16)BIT(2))
258 #define ARM64_CPUCAP_SCOPE_MASK \
259 (ARM64_CPUCAP_SCOPE_SYSTEM | \
260 ARM64_CPUCAP_SCOPE_LOCAL_CPU | \
261 ARM64_CPUCAP_SCOPE_BOOT_CPU)
263 #define SCOPE_SYSTEM ARM64_CPUCAP_SCOPE_SYSTEM
264 #define SCOPE_LOCAL_CPU ARM64_CPUCAP_SCOPE_LOCAL_CPU
265 #define SCOPE_BOOT_CPU ARM64_CPUCAP_SCOPE_BOOT_CPU
266 #define SCOPE_ALL ARM64_CPUCAP_SCOPE_MASK
269 * Is it permitted for a late CPU to have this capability when system
270 * hasn't already enabled it ?
272 #define ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU ((u16)BIT(4))
273 /* Is it safe for a late CPU to miss this capability when system has it */
274 #define ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU ((u16)BIT(5))
275 /* Panic when a conflict is detected */
276 #define ARM64_CPUCAP_PANIC_ON_CONFLICT ((u16)BIT(6))
279 * CPU errata workarounds that need to be enabled at boot time if one or
280 * more CPUs in the system requires it. When one of these capabilities
281 * has been enabled, it is safe to allow any CPU to boot that doesn't
282 * require the workaround. However, it is not safe if a "late" CPU
283 * requires a workaround and the system hasn't enabled it already.
285 #define ARM64_CPUCAP_LOCAL_CPU_ERRATUM \
286 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU)
288 * CPU feature detected at boot time based on system-wide value of a
289 * feature. It is safe for a late CPU to have this feature even though
290 * the system hasn't enabled it, although the feature will not be used
291 * by Linux in this case. If the system has enabled this feature already,
292 * then every late CPU must have it.
294 #define ARM64_CPUCAP_SYSTEM_FEATURE \
295 (ARM64_CPUCAP_SCOPE_SYSTEM | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
297 * CPU feature detected at boot time based on feature of one or more CPUs.
298 * All possible conflicts for a late CPU are ignored.
299 * NOTE: this means that a late CPU with the feature will *not* cause the
300 * capability to be advertised by cpus_have_*cap()!
302 #define ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE \
303 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | \
304 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU | \
305 ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
308 * CPU feature detected at boot time, on one or more CPUs. A late CPU
309 * is not allowed to have the capability when the system doesn't have it.
310 * It is Ok for a late CPU to miss the feature.
312 #define ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE \
313 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | \
314 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU)
317 * CPU feature used early in the boot based on the boot CPU. All secondary
318 * CPUs must match the state of the capability as detected by the boot CPU. In
319 * case of a conflict, a kernel panic is triggered.
321 #define ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE \
322 (ARM64_CPUCAP_SCOPE_BOOT_CPU | ARM64_CPUCAP_PANIC_ON_CONFLICT)
325 * CPU feature used early in the boot based on the boot CPU. It is safe for a
326 * late CPU to have this feature even though the boot CPU hasn't enabled it,
327 * although the feature will not be used by Linux in this case. If the boot CPU
328 * has enabled this feature already, then every late CPU must have it.
330 #define ARM64_CPUCAP_BOOT_CPU_FEATURE \
331 (ARM64_CPUCAP_SCOPE_BOOT_CPU | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
333 struct arm64_cpu_capabilities {
337 bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope);
339 * Take the appropriate actions to configure this capability
340 * for this CPU. If the capability is detected by the kernel
341 * this will be called on all the CPUs in the system,
342 * including the hotplugged CPUs, regardless of whether the
343 * capability is available on that specific CPU. This is
344 * useful for some capabilities (e.g, working around CPU
345 * errata), where all the CPUs must take some action (e.g,
346 * changing system control/configuration). Thus, if an action
347 * is required only if the CPU has the capability, then the
348 * routine must check it before taking any action.
350 void (*cpu_enable)(const struct arm64_cpu_capabilities *cap);
352 struct { /* To be used for erratum handling only */
353 struct midr_range midr_range;
354 const struct arm64_midr_revidr {
355 u32 midr_rv; /* revision/variant */
357 } * const fixed_revs;
360 const struct midr_range *midr_range_list;
361 struct { /* Feature register checking */
373 * An optional list of "matches/cpu_enable" pair for the same
374 * "capability" of the same "type" as described by the parent.
375 * Only matches(), cpu_enable() and fields relevant to these
376 * methods are significant in the list. The cpu_enable is
377 * invoked only if the corresponding entry "matches()".
378 * However, if a cpu_enable() method is associated
379 * with multiple matches(), care should be taken that either
380 * the match criteria are mutually exclusive, or that the
381 * method is robust against being called multiple times.
383 const struct arm64_cpu_capabilities *match_list;
384 const struct cpumask *cpus;
387 static inline int cpucap_default_scope(const struct arm64_cpu_capabilities *cap)
389 return cap->type & ARM64_CPUCAP_SCOPE_MASK;
393 * Generic helper for handling capabilities with multiple (match,enable) pairs
394 * of call backs, sharing the same capability bit.
395 * Iterate over each entry to see if at least one matches.
398 cpucap_multi_entry_cap_matches(const struct arm64_cpu_capabilities *entry,
401 const struct arm64_cpu_capabilities *caps;
403 for (caps = entry->match_list; caps->matches; caps++)
404 if (caps->matches(caps, scope))
410 static __always_inline bool is_vhe_hyp_code(void)
412 /* Only defined for code run in VHE hyp context */
413 return __is_defined(__KVM_VHE_HYPERVISOR__);
416 static __always_inline bool is_nvhe_hyp_code(void)
418 /* Only defined for code run in NVHE hyp context */
419 return __is_defined(__KVM_NVHE_HYPERVISOR__);
422 static __always_inline bool is_hyp_code(void)
424 return is_vhe_hyp_code() || is_nvhe_hyp_code();
427 extern DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS);
429 extern DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS);
431 #define for_each_available_cap(cap) \
432 for_each_set_bit(cap, system_cpucaps, ARM64_NCAPS)
434 bool this_cpu_has_cap(unsigned int cap);
435 void cpu_set_feature(unsigned int num);
436 bool cpu_have_feature(unsigned int num);
437 unsigned long cpu_get_elf_hwcap(void);
438 unsigned long cpu_get_elf_hwcap2(void);
440 #define cpu_set_named_feature(name) cpu_set_feature(cpu_feature(name))
441 #define cpu_have_named_feature(name) cpu_have_feature(cpu_feature(name))
443 static __always_inline bool boot_capabilities_finalized(void)
445 return alternative_has_cap_likely(ARM64_ALWAYS_BOOT);
448 static __always_inline bool system_capabilities_finalized(void)
450 return alternative_has_cap_likely(ARM64_ALWAYS_SYSTEM);
454 * Test for a capability with a runtime check.
456 * Before the capability is detected, this returns false.
458 static __always_inline bool cpus_have_cap(unsigned int num)
460 if (__builtin_constant_p(num) && !cpucap_is_possible(num))
462 if (num >= ARM64_NCAPS)
464 return arch_test_bit(num, system_cpucaps);
468 * Test for a capability without a runtime check.
470 * Before boot capabilities are finalized, this will BUG().
471 * After boot capabilities are finalized, this is patched to avoid a runtime
474 * @num must be a compile-time constant.
476 static __always_inline bool cpus_have_final_boot_cap(int num)
478 if (boot_capabilities_finalized())
479 return alternative_has_cap_unlikely(num);
485 * Test for a capability without a runtime check.
487 * Before system capabilities are finalized, this will BUG().
488 * After system capabilities are finalized, this is patched to avoid a runtime
491 * @num must be a compile-time constant.
493 static __always_inline bool cpus_have_final_cap(int num)
495 if (system_capabilities_finalized())
496 return alternative_has_cap_unlikely(num);
501 static inline int __attribute_const__
502 cpuid_feature_extract_signed_field_width(u64 features, int field, int width)
504 return (s64)(features << (64 - width - field)) >> (64 - width);
507 static inline int __attribute_const__
508 cpuid_feature_extract_signed_field(u64 features, int field)
510 return cpuid_feature_extract_signed_field_width(features, field, 4);
513 static __always_inline unsigned int __attribute_const__
514 cpuid_feature_extract_unsigned_field_width(u64 features, int field, int width)
516 return (u64)(features << (64 - width - field)) >> (64 - width);
519 static __always_inline unsigned int __attribute_const__
520 cpuid_feature_extract_unsigned_field(u64 features, int field)
522 return cpuid_feature_extract_unsigned_field_width(features, field, 4);
526 * Fields that identify the version of the Performance Monitors Extension do
527 * not follow the standard ID scheme. See ARM DDI 0487E.a page D13-2825,
528 * "Alternative ID scheme used for the Performance Monitors Extension version".
530 static inline u64 __attribute_const__
531 cpuid_feature_cap_perfmon_field(u64 features, int field, u64 cap)
533 u64 val = cpuid_feature_extract_unsigned_field(features, field);
534 u64 mask = GENMASK_ULL(field + 3, field);
536 /* Treat IMPLEMENTATION DEFINED functionality as unimplemented */
537 if (val == ID_AA64DFR0_EL1_PMUVer_IMP_DEF)
542 features |= (cap << field) & mask;
548 static inline u64 arm64_ftr_mask(const struct arm64_ftr_bits *ftrp)
550 return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);
553 static inline u64 arm64_ftr_reg_user_value(const struct arm64_ftr_reg *reg)
555 return (reg->user_val | (reg->sys_val & reg->user_mask));
558 static inline int __attribute_const__
559 cpuid_feature_extract_field_width(u64 features, int field, int width, bool sign)
561 if (WARN_ON_ONCE(!width))
564 cpuid_feature_extract_signed_field_width(features, field, width) :
565 cpuid_feature_extract_unsigned_field_width(features, field, width);
568 static inline int __attribute_const__
569 cpuid_feature_extract_field(u64 features, int field, bool sign)
571 return cpuid_feature_extract_field_width(features, field, 4, sign);
574 static inline s64 arm64_ftr_value(const struct arm64_ftr_bits *ftrp, u64 val)
576 return (s64)cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width, ftrp->sign);
579 static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
581 return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_EL1_BIGEND_SHIFT) == 0x1 ||
582 cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT) == 0x1;
585 static inline bool id_aa64pfr0_32bit_el1(u64 pfr0)
587 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_EL1_SHIFT);
589 return val == ID_AA64PFR0_EL1_ELx_32BIT_64BIT;
592 static inline bool id_aa64pfr0_32bit_el0(u64 pfr0)
594 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_EL0_SHIFT);
596 return val == ID_AA64PFR0_EL1_ELx_32BIT_64BIT;
599 static inline bool id_aa64pfr0_sve(u64 pfr0)
601 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_SVE_SHIFT);
606 static inline bool id_aa64pfr1_sme(u64 pfr1)
608 u32 val = cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_EL1_SME_SHIFT);
613 static inline bool id_aa64pfr1_mte(u64 pfr1)
615 u32 val = cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_EL1_MTE_SHIFT);
617 return val >= ID_AA64PFR1_EL1_MTE_MTE2;
620 void __init setup_system_features(void);
621 void __init setup_user_features(void);
623 void check_local_cpu_capabilities(void);
625 u64 read_sanitised_ftr_reg(u32 id);
626 u64 __read_sysreg_by_encoding(u32 sys_id);
628 static inline bool cpu_supports_mixed_endian_el0(void)
630 return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));
634 static inline bool supports_csv2p3(int scope)
639 if (scope == SCOPE_LOCAL_CPU)
640 pfr0 = read_sysreg_s(SYS_ID_AA64PFR0_EL1);
642 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
644 csv2_val = cpuid_feature_extract_unsigned_field(pfr0,
645 ID_AA64PFR0_EL1_CSV2_SHIFT);
646 return csv2_val == 3;
649 static inline bool supports_clearbhb(int scope)
653 if (scope == SCOPE_LOCAL_CPU)
654 isar2 = read_sysreg_s(SYS_ID_AA64ISAR2_EL1);
656 isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1);
658 return cpuid_feature_extract_unsigned_field(isar2,
659 ID_AA64ISAR2_EL1_CLRBHB_SHIFT);
662 const struct cpumask *system_32bit_el0_cpumask(void);
663 DECLARE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0);
665 static inline bool system_supports_32bit_el0(void)
667 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
669 return static_branch_unlikely(&arm64_mismatched_32bit_el0) ||
670 id_aa64pfr0_32bit_el0(pfr0);
673 static inline bool system_supports_4kb_granule(void)
678 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
679 val = cpuid_feature_extract_unsigned_field(mmfr0,
680 ID_AA64MMFR0_EL1_TGRAN4_SHIFT);
682 return (val >= ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN) &&
683 (val <= ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX);
686 static inline bool system_supports_64kb_granule(void)
691 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
692 val = cpuid_feature_extract_unsigned_field(mmfr0,
693 ID_AA64MMFR0_EL1_TGRAN64_SHIFT);
695 return (val >= ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN) &&
696 (val <= ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX);
699 static inline bool system_supports_16kb_granule(void)
704 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
705 val = cpuid_feature_extract_unsigned_field(mmfr0,
706 ID_AA64MMFR0_EL1_TGRAN16_SHIFT);
708 return (val >= ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN) &&
709 (val <= ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX);
712 static inline bool system_supports_mixed_endian_el0(void)
714 return id_aa64mmfr0_mixed_endian_el0(read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1));
717 static inline bool system_supports_mixed_endian(void)
722 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
723 val = cpuid_feature_extract_unsigned_field(mmfr0,
724 ID_AA64MMFR0_EL1_BIGEND_SHIFT);
729 static __always_inline bool system_supports_fpsimd(void)
731 return alternative_has_cap_likely(ARM64_HAS_FPSIMD);
734 static inline bool system_uses_hw_pan(void)
736 return alternative_has_cap_unlikely(ARM64_HAS_PAN);
739 static inline bool system_uses_ttbr0_pan(void)
741 return IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN) &&
742 !system_uses_hw_pan();
745 static __always_inline bool system_supports_sve(void)
747 return alternative_has_cap_unlikely(ARM64_SVE);
750 static __always_inline bool system_supports_sme(void)
752 return alternative_has_cap_unlikely(ARM64_SME);
755 static __always_inline bool system_supports_sme2(void)
757 return alternative_has_cap_unlikely(ARM64_SME2);
760 static __always_inline bool system_supports_fa64(void)
762 return alternative_has_cap_unlikely(ARM64_SME_FA64);
765 static __always_inline bool system_supports_tpidr2(void)
767 return system_supports_sme();
770 static __always_inline bool system_supports_cnp(void)
772 return alternative_has_cap_unlikely(ARM64_HAS_CNP);
775 static inline bool system_supports_address_auth(void)
777 return cpus_have_final_boot_cap(ARM64_HAS_ADDRESS_AUTH);
780 static inline bool system_supports_generic_auth(void)
782 return alternative_has_cap_unlikely(ARM64_HAS_GENERIC_AUTH);
785 static inline bool system_has_full_ptr_auth(void)
787 return system_supports_address_auth() && system_supports_generic_auth();
790 static __always_inline bool system_uses_irq_prio_masking(void)
792 return alternative_has_cap_unlikely(ARM64_HAS_GIC_PRIO_MASKING);
795 static inline bool system_supports_mte(void)
797 return alternative_has_cap_unlikely(ARM64_MTE);
800 static inline bool system_has_prio_mask_debugging(void)
802 return IS_ENABLED(CONFIG_ARM64_DEBUG_PRIORITY_MASKING) &&
803 system_uses_irq_prio_masking();
806 static inline bool system_supports_bti(void)
808 return cpus_have_final_cap(ARM64_BTI);
811 static inline bool system_supports_bti_kernel(void)
813 return IS_ENABLED(CONFIG_ARM64_BTI_KERNEL) &&
814 cpus_have_final_boot_cap(ARM64_BTI);
817 static inline bool system_supports_tlb_range(void)
819 return alternative_has_cap_unlikely(ARM64_HAS_TLB_RANGE);
822 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt);
823 bool try_emulate_mrs(struct pt_regs *regs, u32 isn);
825 static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange)
828 case ID_AA64MMFR0_EL1_PARANGE_32: return 32;
829 case ID_AA64MMFR0_EL1_PARANGE_36: return 36;
830 case ID_AA64MMFR0_EL1_PARANGE_40: return 40;
831 case ID_AA64MMFR0_EL1_PARANGE_42: return 42;
832 case ID_AA64MMFR0_EL1_PARANGE_44: return 44;
833 case ID_AA64MMFR0_EL1_PARANGE_48: return 48;
834 case ID_AA64MMFR0_EL1_PARANGE_52: return 52;
836 * A future PE could use a value unknown to the kernel.
837 * However, by the "D10.1.4 Principles of the ID scheme
838 * for fields in ID registers", ARM DDI 0487C.a, any new
839 * value is guaranteed to be higher than what we know already.
840 * As a safe limit, we return the limit supported by the kernel.
842 default: return CONFIG_ARM64_PA_BITS;
846 /* Check whether hardware update of the Access flag is supported */
847 static inline bool cpu_has_hw_af(void)
851 if (!IS_ENABLED(CONFIG_ARM64_HW_AFDBM))
855 * Use cached version to avoid emulated msr operation on KVM
858 mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
859 return cpuid_feature_extract_unsigned_field(mmfr1,
860 ID_AA64MMFR1_EL1_HAFDBS_SHIFT);
863 static inline bool cpu_has_pan(void)
865 u64 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
866 return cpuid_feature_extract_unsigned_field(mmfr1,
867 ID_AA64MMFR1_EL1_PAN_SHIFT);
870 #ifdef CONFIG_ARM64_AMU_EXTN
871 /* Check whether the cpu supports the Activity Monitors Unit (AMU) */
872 extern bool cpu_has_amu_feat(int cpu);
874 static inline bool cpu_has_amu_feat(int cpu)
880 /* Get a cpu that supports the Activity Monitors Unit (AMU) */
881 extern int get_cpu_with_amu_feat(void);
883 static inline unsigned int get_vmid_bits(u64 mmfr1)
887 vmid_bits = cpuid_feature_extract_unsigned_field(mmfr1,
888 ID_AA64MMFR1_EL1_VMIDBits_SHIFT);
889 if (vmid_bits == ID_AA64MMFR1_EL1_VMIDBits_16)
893 * Return the default here even if any reserved
894 * value is fetched from the system register.
899 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, s64 cur);
900 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id);
902 extern struct arm64_ftr_override id_aa64mmfr1_override;
903 extern struct arm64_ftr_override id_aa64pfr0_override;
904 extern struct arm64_ftr_override id_aa64pfr1_override;
905 extern struct arm64_ftr_override id_aa64zfr0_override;
906 extern struct arm64_ftr_override id_aa64smfr0_override;
907 extern struct arm64_ftr_override id_aa64isar1_override;
908 extern struct arm64_ftr_override id_aa64isar2_override;
910 extern struct arm64_ftr_override arm64_sw_feature_override;
912 u32 get_kvm_ipa_limit(void);
913 void dump_cpu_features(void);
915 #endif /* __ASSEMBLY__ */