2 * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #ifndef __ASM_CPUFEATURE_H
10 #define __ASM_CPUFEATURE_H
12 #include <asm/cpucaps.h>
13 #include <asm/cputype.h>
14 #include <asm/hwcap.h>
15 #include <asm/sysreg.h>
18 * In the arm64 world (as in the ARM world), elf_hwcap is used both internally
19 * in the kernel and for user space to keep track of which optional features
20 * are supported by the current system. So let's map feature 'x' to HWCAP_x.
21 * Note that HWCAP_x constants are bit fields so we need to take the log.
24 #define MAX_CPU_FEATURES (8 * sizeof(elf_hwcap))
25 #define cpu_feature(x) ilog2(HWCAP_ ## x)
29 #include <linux/bug.h>
30 #include <linux/jump_label.h>
31 #include <linux/kernel.h>
34 * CPU feature register tracking
36 * The safe value of a CPUID feature field is dependent on the implications
37 * of the values assigned to it by the architecture. Based on the relationship
38 * between the values, the features are classified into 3 types - LOWER_SAFE,
39 * HIGHER_SAFE and EXACT.
41 * The lowest value of all the CPUs is chosen for LOWER_SAFE and highest
42 * for HIGHER_SAFE. It is expected that all CPUs have the same value for
43 * a field when EXACT is specified, failing which, the safe value specified
44 * in the table is chosen.
48 FTR_EXACT, /* Use a predefined safe value */
49 FTR_LOWER_SAFE, /* Smaller value is safe */
50 FTR_HIGHER_SAFE, /* Bigger value is safe */
51 FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */
54 #define FTR_STRICT true /* SANITY check strict matching required */
55 #define FTR_NONSTRICT false /* SANITY check ignored */
57 #define FTR_SIGNED true /* Value should be treated as signed */
58 #define FTR_UNSIGNED false /* Value should be treated as unsigned */
60 #define FTR_VISIBLE true /* Feature visible to the user space */
61 #define FTR_HIDDEN false /* Feature is hidden from the user */
63 struct arm64_ftr_bits {
64 bool sign; /* Value is signed ? */
66 bool strict; /* CPU Sanity check: strict matching required ? */
70 s64 safe_val; /* safe value for FTR_EXACT features */
74 * @arm64_ftr_reg - Feature register
75 * @strict_mask Bits which should match across all CPUs for sanity.
76 * @sys_val Safe value across the CPUs (system view)
78 struct arm64_ftr_reg {
84 const struct arm64_ftr_bits *ftr_bits;
87 extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0;
92 * We use arm64_cpu_capabilities to represent system features, errata work
93 * arounds (both used internally by kernel and tracked in cpu_hwcaps) and
94 * ELF HWCAPs (which are exposed to user).
96 * To support systems with heterogeneous CPUs, we need to make sure that we
97 * detect the capabilities correctly on the system and take appropriate
98 * measures to ensure there are no incompatibilities.
100 * This comment tries to explain how we treat the capabilities.
101 * Each capability has the following list of attributes :
103 * 1) Scope of Detection : The system detects a given capability by
104 * performing some checks at runtime. This could be, e.g, checking the
105 * value of a field in CPU ID feature register or checking the cpu
106 * model. The capability provides a call back ( @matches() ) to
107 * perform the check. Scope defines how the checks should be performed.
108 * There are three cases:
110 * a) SCOPE_LOCAL_CPU: check all the CPUs and "detect" if at least one
111 * matches. This implies, we have to run the check on all the
112 * booting CPUs, until the system decides that state of the
113 * capability is finalised. (See section 2 below)
115 * b) SCOPE_SYSTEM: check all the CPUs and "detect" if all the CPUs
116 * matches. This implies, we run the check only once, when the
117 * system decides to finalise the state of the capability. If the
118 * capability relies on a field in one of the CPU ID feature
119 * registers, we use the sanitised value of the register from the
120 * CPU feature infrastructure to make the decision.
122 * c) SCOPE_BOOT_CPU: Check only on the primary boot CPU to detect the
123 * feature. This category is for features that are "finalised"
124 * (or used) by the kernel very early even before the SMP cpus
127 * The process of detection is usually denoted by "update" capability
130 * 2) Finalise the state : The kernel should finalise the state of a
131 * capability at some point during its execution and take necessary
132 * actions if any. Usually, this is done, after all the boot-time
133 * enabled CPUs are brought up by the kernel, so that it can make
134 * better decision based on the available set of CPUs. However, there
135 * are some special cases, where the action is taken during the early
136 * boot by the primary boot CPU. (e.g, running the kernel at EL2 with
137 * Virtualisation Host Extensions). The kernel usually disallows any
138 * changes to the state of a capability once it finalises the capability
139 * and takes any action, as it may be impossible to execute the actions
140 * safely. A CPU brought up after a capability is "finalised" is
141 * referred to as "Late CPU" w.r.t the capability. e.g, all secondary
142 * CPUs are treated "late CPUs" for capabilities determined by the boot
145 * At the moment there are two passes of finalising the capabilities.
146 * a) Boot CPU scope capabilities - Finalised by primary boot CPU via
147 * setup_boot_cpu_capabilities().
148 * b) Everything except (a) - Run via setup_system_capabilities().
150 * 3) Verification: When a CPU is brought online (e.g, by user or by the
151 * kernel), the kernel should make sure that it is safe to use the CPU,
152 * by verifying that the CPU is compliant with the state of the
153 * capabilities finalised already. This happens via :
155 * secondary_start_kernel()-> check_local_cpu_capabilities()
157 * As explained in (2) above, capabilities could be finalised at
158 * different points in the execution. Each newly booted CPU is verified
159 * against the capabilities that have been finalised by the time it
162 * a) SCOPE_BOOT_CPU : All CPUs are verified against the capability
163 * except for the primary boot CPU.
165 * b) SCOPE_LOCAL_CPU, SCOPE_SYSTEM: All CPUs hotplugged on by the
166 * user after the kernel boot are verified against the capability.
168 * If there is a conflict, the kernel takes an action, based on the
169 * severity (e.g, a CPU could be prevented from booting or cause a
170 * kernel panic). The CPU is allowed to "affect" the state of the
171 * capability, if it has not been finalised already. See section 5
172 * for more details on conflicts.
174 * 4) Action: As mentioned in (2), the kernel can take an action for each
175 * detected capability, on all CPUs on the system. Appropriate actions
176 * include, turning on an architectural feature, modifying the control
177 * registers (e.g, SCTLR, TCR etc.) or patching the kernel via
178 * alternatives. The kernel patching is batched and performed at later
179 * point. The actions are always initiated only after the capability
180 * is finalised. This is usally denoted by "enabling" the capability.
181 * The actions are initiated as follows :
182 * a) Action is triggered on all online CPUs, after the capability is
183 * finalised, invoked within the stop_machine() context from
184 * enable_cpu_capabilitie().
186 * b) Any late CPU, brought up after (1), the action is triggered via:
188 * check_local_cpu_capabilities() -> verify_local_cpu_capabilities()
190 * 5) Conflicts: Based on the state of the capability on a late CPU vs.
191 * the system state, we could have the following combinations :
193 * x-----------------------------x
194 * | Type | System | Late CPU |
195 * |-----------------------------|
197 * |-----------------------------|
199 * x-----------------------------x
201 * Two separate flag bits are defined to indicate whether each kind of
202 * conflict can be allowed:
203 * ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU - Case(a) is allowed
204 * ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU - Case(b) is allowed
206 * Case (a) is not permitted for a capability that the system requires
207 * all CPUs to have in order for the capability to be enabled. This is
208 * typical for capabilities that represent enhanced functionality.
210 * Case (b) is not permitted for a capability that must be enabled
211 * during boot if any CPU in the system requires it in order to run
212 * safely. This is typical for erratum work arounds that cannot be
213 * enabled after the corresponding capability is finalised.
215 * In some non-typical cases either both (a) and (b), or neither,
216 * should be permitted. This can be described by including neither
217 * or both flags in the capability's type field.
222 * Decide how the capability is detected.
223 * On any local CPU vs System wide vs the primary boot CPU
225 #define ARM64_CPUCAP_SCOPE_LOCAL_CPU ((u16)BIT(0))
226 #define ARM64_CPUCAP_SCOPE_SYSTEM ((u16)BIT(1))
228 * The capabilitiy is detected on the Boot CPU and is used by kernel
229 * during early boot. i.e, the capability should be "detected" and
230 * "enabled" as early as possibly on all booting CPUs.
232 #define ARM64_CPUCAP_SCOPE_BOOT_CPU ((u16)BIT(2))
233 #define ARM64_CPUCAP_SCOPE_MASK \
234 (ARM64_CPUCAP_SCOPE_SYSTEM | \
235 ARM64_CPUCAP_SCOPE_LOCAL_CPU | \
236 ARM64_CPUCAP_SCOPE_BOOT_CPU)
238 #define SCOPE_SYSTEM ARM64_CPUCAP_SCOPE_SYSTEM
239 #define SCOPE_LOCAL_CPU ARM64_CPUCAP_SCOPE_LOCAL_CPU
240 #define SCOPE_BOOT_CPU ARM64_CPUCAP_SCOPE_BOOT_CPU
241 #define SCOPE_ALL ARM64_CPUCAP_SCOPE_MASK
244 * Is it permitted for a late CPU to have this capability when system
245 * hasn't already enabled it ?
247 #define ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU ((u16)BIT(4))
248 /* Is it safe for a late CPU to miss this capability when system has it */
249 #define ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU ((u16)BIT(5))
252 * CPU errata workarounds that need to be enabled at boot time if one or
253 * more CPUs in the system requires it. When one of these capabilities
254 * has been enabled, it is safe to allow any CPU to boot that doesn't
255 * require the workaround. However, it is not safe if a "late" CPU
256 * requires a workaround and the system hasn't enabled it already.
258 #define ARM64_CPUCAP_LOCAL_CPU_ERRATUM \
259 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU)
261 * CPU feature detected at boot time based on system-wide value of a
262 * feature. It is safe for a late CPU to have this feature even though
263 * the system hasn't enabled it, although the featuer will not be used
264 * by Linux in this case. If the system has enabled this feature already,
265 * then every late CPU must have it.
267 #define ARM64_CPUCAP_SYSTEM_FEATURE \
268 (ARM64_CPUCAP_SCOPE_SYSTEM | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
270 * CPU feature detected at boot time based on feature of one or more CPUs.
271 * All possible conflicts for a late CPU are ignored.
273 #define ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE \
274 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | \
275 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU | \
276 ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
279 * CPU feature detected at boot time, on one or more CPUs. A late CPU
280 * is not allowed to have the capability when the system doesn't have it.
281 * It is Ok for a late CPU to miss the feature.
283 #define ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE \
284 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | \
285 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU)
288 * CPU feature used early in the boot based on the boot CPU. All secondary
289 * CPUs must match the state of the capability as detected by the boot CPU.
291 #define ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE ARM64_CPUCAP_SCOPE_BOOT_CPU
293 struct arm64_cpu_capabilities {
297 bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope);
299 * Take the appropriate actions to enable this capability for this CPU.
300 * For each successfully booted CPU, this method is called for each
301 * globally detected capability.
303 void (*cpu_enable)(const struct arm64_cpu_capabilities *cap);
305 struct { /* To be used for erratum handling only */
306 struct midr_range midr_range;
309 const struct midr_range *midr_range_list;
310 struct { /* Feature register checking */
321 static inline int cpucap_default_scope(const struct arm64_cpu_capabilities *cap)
323 return cap->type & ARM64_CPUCAP_SCOPE_MASK;
327 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
329 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
333 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
335 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
338 extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
339 extern struct static_key_false cpu_hwcap_keys[ARM64_NCAPS];
340 extern struct static_key_false arm64_const_caps_ready;
342 bool this_cpu_has_cap(unsigned int cap);
344 static inline bool cpu_have_feature(unsigned int num)
346 return elf_hwcap & (1UL << num);
349 /* System capability check for constant caps */
350 static inline bool __cpus_have_const_cap(int num)
352 if (num >= ARM64_NCAPS)
354 return static_branch_unlikely(&cpu_hwcap_keys[num]);
357 static inline bool cpus_have_cap(unsigned int num)
359 if (num >= ARM64_NCAPS)
361 return test_bit(num, cpu_hwcaps);
364 static inline bool cpus_have_const_cap(int num)
366 if (static_branch_likely(&arm64_const_caps_ready))
367 return __cpus_have_const_cap(num);
369 return cpus_have_cap(num);
372 static inline void cpus_set_cap(unsigned int num)
374 if (num >= ARM64_NCAPS) {
375 pr_warn("Attempt to set an illegal CPU capability (%d >= %d)\n",
378 __set_bit(num, cpu_hwcaps);
382 static inline int __attribute_const__
383 cpuid_feature_extract_signed_field_width(u64 features, int field, int width)
385 return (s64)(features << (64 - width - field)) >> (64 - width);
388 static inline int __attribute_const__
389 cpuid_feature_extract_signed_field(u64 features, int field)
391 return cpuid_feature_extract_signed_field_width(features, field, 4);
394 static inline unsigned int __attribute_const__
395 cpuid_feature_extract_unsigned_field_width(u64 features, int field, int width)
397 return (u64)(features << (64 - width - field)) >> (64 - width);
400 static inline unsigned int __attribute_const__
401 cpuid_feature_extract_unsigned_field(u64 features, int field)
403 return cpuid_feature_extract_unsigned_field_width(features, field, 4);
406 static inline u64 arm64_ftr_mask(const struct arm64_ftr_bits *ftrp)
408 return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);
411 static inline u64 arm64_ftr_reg_user_value(const struct arm64_ftr_reg *reg)
413 return (reg->user_val | (reg->sys_val & reg->user_mask));
416 static inline int __attribute_const__
417 cpuid_feature_extract_field_width(u64 features, int field, int width, bool sign)
420 cpuid_feature_extract_signed_field_width(features, field, width) :
421 cpuid_feature_extract_unsigned_field_width(features, field, width);
424 static inline int __attribute_const__
425 cpuid_feature_extract_field(u64 features, int field, bool sign)
427 return cpuid_feature_extract_field_width(features, field, 4, sign);
430 static inline s64 arm64_ftr_value(const struct arm64_ftr_bits *ftrp, u64 val)
432 return (s64)cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width, ftrp->sign);
435 static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
437 return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 ||
438 cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1;
441 static inline bool id_aa64pfr0_32bit_el0(u64 pfr0)
443 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL0_SHIFT);
445 return val == ID_AA64PFR0_EL0_32BIT_64BIT;
448 void __init setup_cpu_features(void);
449 void check_local_cpu_capabilities(void);
452 u64 read_sanitised_ftr_reg(u32 id);
454 static inline bool cpu_supports_mixed_endian_el0(void)
456 return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));
459 static inline bool system_supports_32bit_el0(void)
461 return cpus_have_const_cap(ARM64_HAS_32BIT_EL0);
464 static inline bool system_supports_mixed_endian_el0(void)
466 return id_aa64mmfr0_mixed_endian_el0(read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1));
469 static inline bool system_supports_fpsimd(void)
471 return !cpus_have_const_cap(ARM64_HAS_NO_FPSIMD);
474 static inline bool system_uses_ttbr0_pan(void)
476 return IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN) &&
477 !cpus_have_const_cap(ARM64_HAS_PAN);
480 #define ARM64_SSBD_UNKNOWN -1
481 #define ARM64_SSBD_FORCE_DISABLE 0
482 #define ARM64_SSBD_KERNEL 1
483 #define ARM64_SSBD_FORCE_ENABLE 2
484 #define ARM64_SSBD_MITIGATED 3
486 static inline int arm64_get_ssbd_state(void)
488 #ifdef CONFIG_ARM64_SSBD
489 extern int ssbd_state;
492 return ARM64_SSBD_UNKNOWN;
496 void arm64_set_ssbd_mitigation(bool state);
498 #endif /* __ASSEMBLY__ */