2 * Based on arch/arm/include/asm/barrier.h
4 * Copyright (C) 2012 ARM Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #ifndef __ASM_BARRIER_H
19 #define __ASM_BARRIER_H
23 #define __nops(n) ".rept " #n "\nnop\n.endr\n"
24 #define nops(n) asm volatile(__nops(n))
26 #define sev() asm volatile("sev" : : : "memory")
27 #define wfe() asm volatile("wfe" : : : "memory")
28 #define wfi() asm volatile("wfi" : : : "memory")
30 #define isb() asm volatile("isb" : : : "memory")
31 #define dmb(opt) asm volatile("dmb " #opt : : : "memory")
32 #define dsb(opt) asm volatile("dsb " #opt : : : "memory")
34 #define csdb() asm volatile("hint #20" : : : "memory")
40 #define dma_rmb() dmb(oshld)
41 #define dma_wmb() dmb(oshst)
44 * Generate a mask for array_index__nospec() that is ~0UL when 0 <= idx < sz
47 #define array_index_mask_nospec array_index_mask_nospec
48 static inline unsigned long array_index_mask_nospec(unsigned long idx,
57 : "r" (idx), "Ir" (sz)
64 #define __smp_mb() dmb(ish)
65 #define __smp_rmb() dmb(ishld)
66 #define __smp_wmb() dmb(ishst)
68 #define __smp_store_release(p, v) \
70 union { typeof(*p) __val; char __c[1]; } __u = \
71 { .__val = (__force typeof(*p)) (v) }; \
72 compiletime_assert_atomic_type(*p); \
73 switch (sizeof(*p)) { \
75 asm volatile ("stlrb %w1, %0" \
77 : "r" (*(__u8 *)__u.__c) \
81 asm volatile ("stlrh %w1, %0" \
83 : "r" (*(__u16 *)__u.__c) \
87 asm volatile ("stlr %w1, %0" \
89 : "r" (*(__u32 *)__u.__c) \
93 asm volatile ("stlr %1, %0" \
95 : "r" (*(__u64 *)__u.__c) \
101 #define __smp_load_acquire(p) \
103 union { typeof(*p) __val; char __c[1]; } __u; \
104 compiletime_assert_atomic_type(*p); \
105 switch (sizeof(*p)) { \
107 asm volatile ("ldarb %w0, %1" \
108 : "=r" (*(__u8 *)__u.__c) \
109 : "Q" (*p) : "memory"); \
112 asm volatile ("ldarh %w0, %1" \
113 : "=r" (*(__u16 *)__u.__c) \
114 : "Q" (*p) : "memory"); \
117 asm volatile ("ldar %w0, %1" \
118 : "=r" (*(__u32 *)__u.__c) \
119 : "Q" (*p) : "memory"); \
122 asm volatile ("ldar %0, %1" \
123 : "=r" (*(__u64 *)__u.__c) \
124 : "Q" (*p) : "memory"); \
130 #define smp_cond_load_acquire(ptr, cond_expr) \
132 typeof(ptr) __PTR = (ptr); \
135 VAL = smp_load_acquire(__PTR); \
138 __cmpwait_relaxed(__PTR, VAL); \
143 #include <asm-generic/barrier.h>
145 #endif /* __ASSEMBLY__ */
147 #endif /* __ASM_BARRIER_H */