1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Based on arch/arm/include/asm/atomic.h
5 * Copyright (C) 1996 Russell King.
6 * Copyright (C) 2002 Deep Blue Solutions Ltd.
7 * Copyright (C) 2012 ARM Ltd.
10 #ifndef __ASM_ATOMIC_LSE_H
11 #define __ASM_ATOMIC_LSE_H
13 #define ATOMIC_OP(op, asm_op) \
14 static inline void __lse_atomic_##op(int i, atomic_t *v) \
18 " " #asm_op " %w[i], %[v]\n" \
19 : [v] "+Q" (v->counter) \
23 ATOMIC_OP(andnot, stclr)
28 static inline void __lse_atomic_sub(int i, atomic_t *v)
30 __lse_atomic_add(-i, v);
35 #define ATOMIC_FETCH_OP(name, mb, op, asm_op, cl...) \
36 static inline int __lse_atomic_fetch_##op##name(int i, atomic_t *v) \
42 " " #asm_op #mb " %w[i], %w[old], %[v]" \
43 : [v] "+Q" (v->counter), \
51 #define ATOMIC_FETCH_OPS(op, asm_op) \
52 ATOMIC_FETCH_OP(_relaxed, , op, asm_op) \
53 ATOMIC_FETCH_OP(_acquire, a, op, asm_op, "memory") \
54 ATOMIC_FETCH_OP(_release, l, op, asm_op, "memory") \
55 ATOMIC_FETCH_OP( , al, op, asm_op, "memory")
57 ATOMIC_FETCH_OPS(andnot, ldclr)
58 ATOMIC_FETCH_OPS(or, ldset)
59 ATOMIC_FETCH_OPS(xor, ldeor)
60 ATOMIC_FETCH_OPS(add, ldadd)
62 #undef ATOMIC_FETCH_OP
63 #undef ATOMIC_FETCH_OPS
65 #define ATOMIC_FETCH_OP_SUB(name) \
66 static inline int __lse_atomic_fetch_sub##name(int i, atomic_t *v) \
68 return __lse_atomic_fetch_add##name(-i, v); \
71 ATOMIC_FETCH_OP_SUB(_relaxed)
72 ATOMIC_FETCH_OP_SUB(_acquire)
73 ATOMIC_FETCH_OP_SUB(_release)
74 ATOMIC_FETCH_OP_SUB( )
76 #undef ATOMIC_FETCH_OP_SUB
78 #define ATOMIC_OP_ADD_SUB_RETURN(name) \
79 static inline int __lse_atomic_add_return##name(int i, atomic_t *v) \
81 return __lse_atomic_fetch_add##name(i, v) + i; \
84 static inline int __lse_atomic_sub_return##name(int i, atomic_t *v) \
86 return __lse_atomic_fetch_sub(i, v) - i; \
89 ATOMIC_OP_ADD_SUB_RETURN(_relaxed)
90 ATOMIC_OP_ADD_SUB_RETURN(_acquire)
91 ATOMIC_OP_ADD_SUB_RETURN(_release)
92 ATOMIC_OP_ADD_SUB_RETURN( )
94 #undef ATOMIC_OP_ADD_SUB_RETURN
96 static inline void __lse_atomic_and(int i, atomic_t *v)
98 return __lse_atomic_andnot(~i, v);
101 #define ATOMIC_FETCH_OP_AND(name, mb, cl...) \
102 static inline int __lse_atomic_fetch_and##name(int i, atomic_t *v) \
104 return __lse_atomic_fetch_andnot##name(~i, v); \
107 ATOMIC_FETCH_OP_AND(_relaxed, )
108 ATOMIC_FETCH_OP_AND(_acquire, a, "memory")
109 ATOMIC_FETCH_OP_AND(_release, l, "memory")
110 ATOMIC_FETCH_OP_AND( , al, "memory")
112 #undef ATOMIC_FETCH_OP_AND
114 #define ATOMIC64_OP(op, asm_op) \
115 static inline void __lse_atomic64_##op(s64 i, atomic64_t *v) \
119 " " #asm_op " %[i], %[v]\n" \
120 : [v] "+Q" (v->counter) \
124 ATOMIC64_OP(andnot, stclr)
125 ATOMIC64_OP(or, stset)
126 ATOMIC64_OP(xor, steor)
127 ATOMIC64_OP(add, stadd)
129 static inline void __lse_atomic64_sub(s64 i, atomic64_t *v)
131 __lse_atomic64_add(-i, v);
136 #define ATOMIC64_FETCH_OP(name, mb, op, asm_op, cl...) \
137 static inline long __lse_atomic64_fetch_##op##name(s64 i, atomic64_t *v)\
143 " " #asm_op #mb " %[i], %[old], %[v]" \
144 : [v] "+Q" (v->counter), \
152 #define ATOMIC64_FETCH_OPS(op, asm_op) \
153 ATOMIC64_FETCH_OP(_relaxed, , op, asm_op) \
154 ATOMIC64_FETCH_OP(_acquire, a, op, asm_op, "memory") \
155 ATOMIC64_FETCH_OP(_release, l, op, asm_op, "memory") \
156 ATOMIC64_FETCH_OP( , al, op, asm_op, "memory")
158 ATOMIC64_FETCH_OPS(andnot, ldclr)
159 ATOMIC64_FETCH_OPS(or, ldset)
160 ATOMIC64_FETCH_OPS(xor, ldeor)
161 ATOMIC64_FETCH_OPS(add, ldadd)
163 #undef ATOMIC64_FETCH_OP
164 #undef ATOMIC64_FETCH_OPS
166 #define ATOMIC64_FETCH_OP_SUB(name) \
167 static inline long __lse_atomic64_fetch_sub##name(s64 i, atomic64_t *v) \
169 return __lse_atomic64_fetch_add##name(-i, v); \
172 ATOMIC64_FETCH_OP_SUB(_relaxed)
173 ATOMIC64_FETCH_OP_SUB(_acquire)
174 ATOMIC64_FETCH_OP_SUB(_release)
175 ATOMIC64_FETCH_OP_SUB( )
177 #undef ATOMIC64_FETCH_OP_SUB
179 #define ATOMIC64_OP_ADD_SUB_RETURN(name) \
180 static inline long __lse_atomic64_add_return##name(s64 i, atomic64_t *v)\
182 return __lse_atomic64_fetch_add##name(i, v) + i; \
185 static inline long __lse_atomic64_sub_return##name(s64 i, atomic64_t *v)\
187 return __lse_atomic64_fetch_sub##name(i, v) - i; \
190 ATOMIC64_OP_ADD_SUB_RETURN(_relaxed)
191 ATOMIC64_OP_ADD_SUB_RETURN(_acquire)
192 ATOMIC64_OP_ADD_SUB_RETURN(_release)
193 ATOMIC64_OP_ADD_SUB_RETURN( )
195 #undef ATOMIC64_OP_ADD_SUB_RETURN
197 static inline void __lse_atomic64_and(s64 i, atomic64_t *v)
199 return __lse_atomic64_andnot(~i, v);
202 #define ATOMIC64_FETCH_OP_AND(name, mb, cl...) \
203 static inline long __lse_atomic64_fetch_and##name(s64 i, atomic64_t *v) \
205 return __lse_atomic64_fetch_andnot##name(~i, v); \
208 ATOMIC64_FETCH_OP_AND(_relaxed, )
209 ATOMIC64_FETCH_OP_AND(_acquire, a, "memory")
210 ATOMIC64_FETCH_OP_AND(_release, l, "memory")
211 ATOMIC64_FETCH_OP_AND( , al, "memory")
213 #undef ATOMIC64_FETCH_OP_AND
215 static inline s64 __lse_atomic64_dec_if_positive(atomic64_t *v)
221 "1: ldr %x[tmp], %[v]\n"
222 " subs %[ret], %x[tmp], #1\n"
224 " casal %x[tmp], %[ret], %[v]\n"
225 " sub %x[tmp], %x[tmp], #1\n"
226 " sub %x[tmp], %x[tmp], %[ret]\n"
227 " cbnz %x[tmp], 1b\n"
229 : [ret] "+&r" (v), [v] "+Q" (v->counter), [tmp] "=&r" (tmp)
236 #define __CMPXCHG_CASE(w, sfx, name, sz, mb, cl...) \
237 static __always_inline u##sz \
238 __lse__cmpxchg_case_##name##sz(volatile void *ptr, \
242 register unsigned long x0 asm ("x0") = (unsigned long)ptr; \
243 register u##sz x1 asm ("x1") = old; \
244 register u##sz x2 asm ("x2") = new; \
249 " mov %" #w "[tmp], %" #w "[old]\n" \
250 " cas" #mb #sfx "\t%" #w "[tmp], %" #w "[new], %[v]\n" \
251 " mov %" #w "[ret], %" #w "[tmp]" \
252 : [ret] "+r" (x0), [v] "+Q" (*(u##sz *)ptr), \
254 : [old] "r" (x1), [new] "r" (x2) \
260 __CMPXCHG_CASE(w, b, , 8, )
261 __CMPXCHG_CASE(w, h, , 16, )
262 __CMPXCHG_CASE(w, , , 32, )
263 __CMPXCHG_CASE(x, , , 64, )
264 __CMPXCHG_CASE(w, b, acq_, 8, a, "memory")
265 __CMPXCHG_CASE(w, h, acq_, 16, a, "memory")
266 __CMPXCHG_CASE(w, , acq_, 32, a, "memory")
267 __CMPXCHG_CASE(x, , acq_, 64, a, "memory")
268 __CMPXCHG_CASE(w, b, rel_, 8, l, "memory")
269 __CMPXCHG_CASE(w, h, rel_, 16, l, "memory")
270 __CMPXCHG_CASE(w, , rel_, 32, l, "memory")
271 __CMPXCHG_CASE(x, , rel_, 64, l, "memory")
272 __CMPXCHG_CASE(w, b, mb_, 8, al, "memory")
273 __CMPXCHG_CASE(w, h, mb_, 16, al, "memory")
274 __CMPXCHG_CASE(w, , mb_, 32, al, "memory")
275 __CMPXCHG_CASE(x, , mb_, 64, al, "memory")
277 #undef __CMPXCHG_CASE
279 #define __CMPXCHG_DBL(name, mb, cl...) \
280 static __always_inline long \
281 __lse__cmpxchg_double##name(unsigned long old1, \
282 unsigned long old2, \
283 unsigned long new1, \
284 unsigned long new2, \
285 volatile void *ptr) \
287 unsigned long oldval1 = old1; \
288 unsigned long oldval2 = old2; \
289 register unsigned long x0 asm ("x0") = old1; \
290 register unsigned long x1 asm ("x1") = old2; \
291 register unsigned long x2 asm ("x2") = new1; \
292 register unsigned long x3 asm ("x3") = new2; \
293 register unsigned long x4 asm ("x4") = (unsigned long)ptr; \
297 " casp" #mb "\t%[old1], %[old2], %[new1], %[new2], %[v]\n"\
298 " eor %[old1], %[old1], %[oldval1]\n" \
299 " eor %[old2], %[old2], %[oldval2]\n" \
300 " orr %[old1], %[old1], %[old2]" \
301 : [old1] "+&r" (x0), [old2] "+&r" (x1), \
302 [v] "+Q" (*(unsigned long *)ptr) \
303 : [new1] "r" (x2), [new2] "r" (x3), [ptr] "r" (x4), \
304 [oldval1] "r" (oldval1), [oldval2] "r" (oldval2) \
311 __CMPXCHG_DBL(_mb, al, "memory")
315 #endif /* __ASM_ATOMIC_LSE_H */