2 * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
4 * Copyright (C) 1996-2000 Russell King
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #error "Only include this from assembly code"
23 #ifndef __ASM_ASSEMBLER_H
24 #define __ASM_ASSEMBLER_H
26 #include <asm/asm-offsets.h>
27 #include <asm/cpufeature.h>
28 #include <asm/cputype.h>
30 #include <asm/pgtable-hwdef.h>
31 #include <asm/ptrace.h>
32 #include <asm/thread_info.h>
35 * Enable and disable interrupts.
46 * Enable and disable debug exceptions.
56 .macro disable_step_tsk, flgs, tmp
57 tbz \flgs, #TIF_SINGLESTEP, 9990f
61 isb // Synchronise with enable_dbg
65 .macro enable_step_tsk, flgs, tmp
66 tbz \flgs, #TIF_SINGLESTEP, 9990f
75 * Enable both debug exceptions and interrupts. This is likely to be
76 * faster than two daifclr operations, since writes to this register
77 * are self-synchronising.
79 .macro enable_dbg_and_irq
84 * SMP data memory barrier
91 * Value prediction barrier
98 * Sanitise a 64-bit bounded index wrt speculation, returning zero if out
101 .macro mask_nospec64, idx, limit, tmp
102 sub \tmp, \idx, \limit
104 and \idx, \idx, \tmp, asr #63
118 * Emit an entry into the exception table
120 .macro _asm_extable, from, to
121 .pushsection __ex_table, "a"
123 .long (\from - .), (\to - .)
127 #define USER(l, x...) \
129 _asm_extable 9999b, l
134 lr .req x30 // link register
145 * Select code when configured for BE.
147 #ifdef CONFIG_CPU_BIG_ENDIAN
148 #define CPU_BE(code...) code
150 #define CPU_BE(code...)
154 * Select code when configured for LE.
156 #ifdef CONFIG_CPU_BIG_ENDIAN
157 #define CPU_LE(code...)
159 #define CPU_LE(code...) code
163 * Define a macro that constructs a 64-bit value by concatenating two
164 * 32-bit registers. Note that on big endian systems the order of the
165 * registers is swapped.
167 #ifndef CONFIG_CPU_BIG_ENDIAN
168 .macro regs_to_64, rd, lbits, hbits
170 .macro regs_to_64, rd, hbits, lbits
172 orr \rd, \lbits, \hbits, lsl #32
176 * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
177 * <symbol> is within the range +/- 4 GB of the PC when running
178 * in core kernel context. In module context, a movz/movk sequence
179 * is used, since modules may be loaded far away from the kernel
180 * when KASLR is in effect.
183 * @dst: destination register (64 bit wide)
184 * @sym: name of the symbol
186 .macro adr_l, dst, sym
189 add \dst, \dst, :lo12:\sym
191 movz \dst, #:abs_g3:\sym
192 movk \dst, #:abs_g2_nc:\sym
193 movk \dst, #:abs_g1_nc:\sym
194 movk \dst, #:abs_g0_nc:\sym
199 * @dst: destination register (32 or 64 bit wide)
200 * @sym: name of the symbol
201 * @tmp: optional 64-bit scratch register to be used if <dst> is a
202 * 32-bit wide register, in which case it cannot be used to hold
205 .macro ldr_l, dst, sym, tmp=
209 ldr \dst, [\dst, :lo12:\sym]
212 ldr \dst, [\tmp, :lo12:\sym]
226 * @src: source register (32 or 64 bit wide)
227 * @sym: name of the symbol
228 * @tmp: mandatory 64-bit scratch register to calculate the address
229 * while <src> needs to be preserved.
231 .macro str_l, src, sym, tmp
234 str \src, [\tmp, :lo12:\sym]
242 * @dst: Result of per_cpu(sym, smp_processor_id())
243 * @sym: The name of the per-cpu variable
244 * @tmp: scratch register
246 .macro adr_this_cpu, dst, sym, tmp
248 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
257 * @dst: Result of READ_ONCE(per_cpu(sym, smp_processor_id()))
258 * @sym: The name of the per-cpu variable
259 * @tmp: scratch register
261 .macro ldr_this_cpu dst, sym, tmp
263 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
268 ldr \dst, [\dst, \tmp]
272 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
274 .macro vma_vm_mm, rd, rn
275 ldr \rd, [\rn, #VMA_VM_MM]
279 * mmid - get context id from mm pointer (mm->context.id)
282 ldr \rd, [\rn, #MM_CONTEXT_ID]
285 * read_ctr - read CTR_EL0. If the system has mismatched
286 * cache line sizes, provide the system wide safe value
287 * from arm64_ftr_reg_ctrel0.sys_val
290 alternative_if_not ARM64_MISMATCHED_CACHE_LINE_SIZE
291 mrs \reg, ctr_el0 // read CTR
294 ldr_l \reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL
300 * raw_dcache_line_size - get the minimum D-cache line size on this CPU
301 * from the CTR register.
303 .macro raw_dcache_line_size, reg, tmp
304 mrs \tmp, ctr_el0 // read CTR
305 ubfm \tmp, \tmp, #16, #19 // cache line size encoding
306 mov \reg, #4 // bytes per word
307 lsl \reg, \reg, \tmp // actual cache line size
311 * dcache_line_size - get the safe D-cache line size across all CPUs
313 .macro dcache_line_size, reg, tmp
315 ubfm \tmp, \tmp, #16, #19 // cache line size encoding
316 mov \reg, #4 // bytes per word
317 lsl \reg, \reg, \tmp // actual cache line size
321 * raw_icache_line_size - get the minimum I-cache line size on this CPU
322 * from the CTR register.
324 .macro raw_icache_line_size, reg, tmp
325 mrs \tmp, ctr_el0 // read CTR
326 and \tmp, \tmp, #0xf // cache line size encoding
327 mov \reg, #4 // bytes per word
328 lsl \reg, \reg, \tmp // actual cache line size
332 * icache_line_size - get the safe I-cache line size across all CPUs
334 .macro icache_line_size, reg, tmp
336 and \tmp, \tmp, #0xf // cache line size encoding
337 mov \reg, #4 // bytes per word
338 lsl \reg, \reg, \tmp // actual cache line size
342 * tcr_set_idmap_t0sz - update TCR.T0SZ so that we can load the ID map
344 .macro tcr_set_idmap_t0sz, valreg, tmpreg
345 #ifndef CONFIG_ARM64_VA_BITS_48
346 ldr_l \tmpreg, idmap_t0sz
347 bfi \valreg, \tmpreg, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH
352 * Macro to perform a data cache maintenance for the interval
353 * [kaddr, kaddr + size)
355 * op: operation passed to dc instruction
356 * domain: domain used in dsb instruciton
357 * kaddr: starting virtual address of the region
358 * size: size of the region
359 * Corrupts: kaddr, size, tmp1, tmp2
361 .macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2
362 dcache_line_size \tmp1, \tmp2
363 add \size, \kaddr, \size
365 bic \kaddr, \kaddr, \tmp2
367 .if (\op == cvau || \op == cvac)
368 alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE
376 add \kaddr, \kaddr, \tmp1
383 * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
385 .macro reset_pmuserenr_el0, tmpreg
386 mrs \tmpreg, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer
387 sbfx \tmpreg, \tmpreg, #8, #4
388 cmp \tmpreg, #1 // Skip if no PMU present
390 msr pmuserenr_el0, xzr // Disable PMU access from EL0
395 * copy_page - copy src to dest using temp registers t1-t8
397 .macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req
398 9998: ldp \t1, \t2, [\src]
399 ldp \t3, \t4, [\src, #16]
400 ldp \t5, \t6, [\src, #32]
401 ldp \t7, \t8, [\src, #48]
403 stnp \t1, \t2, [\dest]
404 stnp \t3, \t4, [\dest, #16]
405 stnp \t5, \t6, [\dest, #32]
406 stnp \t7, \t8, [\dest, #48]
407 add \dest, \dest, #64
408 tst \src, #(PAGE_SIZE - 1)
413 * Annotate a function as position independent, i.e., safe to be called before
414 * the kernel virtual mapping is activated.
416 #define ENDPIPROC(x) \
418 .type __pi_##x, %function; \
420 .size __pi_##x, . - x; \
424 * Emit a 64-bit absolute little endian symbol reference in a way that
425 * ensures that it will be resolved at build time, even when building a
426 * PIE binary. This requires cooperation from the linker script, which
427 * must emit the lo32/hi32 halves individually.
435 * mov_q - move an immediate constant into a 64-bit register using
436 * between 2 and 4 movz/movk instructions (depending on the
437 * magnitude and sign of the operand)
439 .macro mov_q, reg, val
440 .if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff)
441 movz \reg, :abs_g1_s:\val
443 .if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff)
444 movz \reg, :abs_g2_s:\val
446 movz \reg, :abs_g3:\val
447 movk \reg, :abs_g2_nc:\val
449 movk \reg, :abs_g1_nc:\val
451 movk \reg, :abs_g0_nc:\val
454 .macro pte_to_phys, phys, pte
455 and \phys, \pte, #(((1 << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT)
459 * Check the MIDR_EL1 of the current CPU for a given model and a range of
460 * variant/revision. See asm/cputype.h for the macros used below.
462 * model: MIDR_CPU_MODEL of CPU
463 * rv_min: Minimum of MIDR_CPU_VAR_REV()
464 * rv_max: Maximum of MIDR_CPU_VAR_REV()
465 * res: Result register.
466 * tmp1, tmp2, tmp3: Temporary registers
468 * Corrupts: res, tmp1, tmp2, tmp3
469 * Returns: 0, if the CPU id doesn't match. Non-zero otherwise
471 .macro cpu_midr_match model, rv_min, rv_max, res, tmp1, tmp2, tmp3
473 mov_q \tmp1, (MIDR_REVISION_MASK | MIDR_VARIANT_MASK)
474 mov_q \tmp2, MIDR_CPU_MODEL_MASK
475 and \tmp3, \res, \tmp2 // Extract model
476 and \tmp1, \res, \tmp1 // rev & variant
480 cbz \res, .Ldone\@ // Model matches ?
482 .if (\rv_min != 0) // Skip min check if rv_min == 0
486 .endif // \rv_min != 0
487 /* Skip rv_max check if rv_min == rv_max && rv_min != 0 */
488 .if ((\rv_min != \rv_max) || \rv_min == 0)
492 and \res, \res, \tmp2
497 #endif /* __ASM_ASSEMBLER_H */