arch/arm64/boot/dts/zte/zx296718.dtsi

   1 /*
   2  * Copyright 2016 ZTE Corporation.
   3  * Copyright 2016 Linaro Ltd.
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This library is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This library is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/input/input.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/gpio/gpio.h>
  47 #include <dt-bindings/clock/zx296718-clock.h>
  48
  49 / {
  50         compatible = "zte,zx296718";
  51         #address-cells = <1>;
  52         #size-cells = <1>;
  53         interrupt-parent = <&gic>;
  54
  55         aliases {
  56                 gpio0 = &bgpio0;
  57                 gpio1 = &bgpio1;
  58                 gpio2 = &bgpio2;
  59                 gpio3 = &bgpio3;
  60                 gpio4 = &bgpio4;
  61                 gpio5 = &bgpio5;
  62                 gpio6 = &bgpio6;
  63                 serial0 = &uart0;
  64         };
  65
  66         cpus {
  67                 #address-cells = <2>;
  68                 #size-cells = <0>;
  69
  70                 cpu-map {
  71                         cluster0 {
  72                                 core0 {
  73                                         cpu = <&cpu0>;
  74                                 };
  75                                 core1 {
  76                                         cpu = <&cpu1>;
  77                                 };
  78                                 core2 {
  79                                         cpu = <&cpu2>;
  80                                 };
  81                                 core3 {
  82                                         cpu = <&cpu3>;
  83                                 };
  84                         };
  85                 };
  86
  87                 cpu0: cpu@0 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a53","arm,armv8";
  90                         reg = <0x0 0x0>;
  91                         enable-method = "psci";
  92                         clocks = <&topcrm A53_GATE>;
  93                         operating-points-v2 = <&cluster0_opp>;
  94                 };
  95
  96                 cpu1: cpu@1 {
  97                         device_type = "cpu";
  98                         compatible = "arm,cortex-a53","arm,armv8";
  99                         reg = <0x0 0x1>;
 100                         enable-method = "psci";
 101                         clocks = <&topcrm A53_GATE>;
 102                         operating-points-v2 = <&cluster0_opp>;
 103                 };
 104
 105                 cpu2: cpu@2 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a53","arm,armv8";
 108                         reg = <0x0 0x2>;
 109                         enable-method = "psci";
 110                         clocks = <&topcrm A53_GATE>;
 111                         operating-points-v2 = <&cluster0_opp>;
 112                 };
 113
 114                 cpu3: cpu@3 {
 115                         device_type = "cpu";
 116                         compatible = "arm,cortex-a53","arm,armv8";
 117                         reg = <0x0 0x3>;
 118                         enable-method = "psci";
 119                         clocks = <&topcrm A53_GATE>;
 120                         operating-points-v2 = <&cluster0_opp>;
 121                 };
 122         };
 123
 124         cluster0_opp: opp-table0 {
 125                 compatible = "operating-points-v2";
 126                 opp-shared;
 127
 128                 opp-500000000 {
 129                         opp-hz = /bits/ 64 <500000000>;
 130                         opp-microvolt = <866000>;
 131                         clock-latency-ns = <500000>;
 132                 };
 133
 134                 opp-648000000 {
 135                         opp-hz = /bits/ 64 <648000000>;
 136                         opp-microvolt = <866000>;
 137                         clock-latency-ns = <500000>;
 138                 };
 139
 140                 opp-800000000 {
 141                         opp-hz = /bits/ 64 <800000000>;
 142                         opp-microvolt = <888000>;
 143                         clock-latency-ns = <500000>;
 144                 };
 145
 146                 opp-1000000000 {
 147                         opp-hz = /bits/ 64 <1000000000>;
 148                         opp-microvolt = <898000>;
 149                         clock-latency-ns = <500000>;
 150                 };
 151
 152                 opp-1188000000 {
 153                         opp-hz = /bits/ 64 <1188000000>;
 154                         opp-microvolt = <1015000>;
 155                         clock-latency-ns = <500000>;
 156                 };
 157         };
 158
 159         clk24k: clk-24k {
 160                 compatible = "fixed-clock";
 161                 #clock-cells = <0>;
 162                 clock-frequency = <24000>;
 163                 clock-output-names = "rtcclk";
 164         };
 165
 166         osc32k: clk-osc32k {
 167                 compatible = "fixed-clock";
 168                 #clock-cells = <0>;
 169                 clock-frequency = <32000>;
 170                 clock-output-names = "osc32k";
 171         };
 172
 173         osc12m: clk-osc12m {
 174                 compatible = "fixed-clock";
 175                 #clock-cells = <0>;
 176                 clock-frequency = <12000000>;
 177                 clock-output-names = "osc12m";
 178         };
 179
 180         osc24m: clk-osc24m {
 181                 compatible = "fixed-clock";
 182                 #clock-cells = <0>;
 183                 clock-frequency = <24000000>;
 184                 clock-output-names = "osc24m";
 185         };
 186
 187         osc25m: clk-osc25m {
 188                 compatible = "fixed-clock";
 189                 #clock-cells = <0>;
 190                 clock-frequency = <25000000>;
 191                 clock-output-names = "osc25m";
 192         };
 193
 194         osc60m: clk-osc60m {
 195                 compatible = "fixed-clock";
 196                 #clock-cells = <0>;
 197                 clock-frequency = <60000000>;
 198                 clock-output-names = "osc60m";
 199         };
 200
 201         osc99m: clk-osc99m {
 202                 compatible = "fixed-clock";
 203                 #clock-cells = <0>;
 204                 clock-frequency = <99000000>;
 205                 clock-output-names = "osc99m";
 206         };
 207
 208         osc125m: clk-osc125m {
 209                 compatible = "fixed-clock";
 210                 #clock-cells = <0>;
 211                 clock-frequency = <125000000>;
 212                 clock-output-names = "osc125m";
 213         };
 214
 215         osc198m: clk-osc198m {
 216                 compatible = "fixed-clock";
 217                 #clock-cells = <0>;
 218                 clock-frequency = <198000000>;
 219                 clock-output-names = "osc198m";
 220         };
 221
 222         pll_audio: clk-pll-884m {
 223                 compatible = "fixed-clock";
 224                 #clock-cells = <0>;
 225                 clock-frequency = <884000000>;
 226                 clock-output-names = "pll_audio";
 227         };
 228
 229         pll_ddr: clk-pll-932m {
 230                 compatible = "fixed-clock";
 231                 #clock-cells = <0>;
 232                 clock-frequency = <932000000>;
 233                 clock-output-names = "pll_ddr";
 234         };
 235
 236         pll_hsic: clk-pll-960m {
 237                 compatible = "fixed-clock";
 238                 #clock-cells = <0>;
 239                 clock-frequency = <960000000>;
 240                 clock-output-names = "pll_hsic";
 241         };
 242
 243         pll_mac: clk-pll-1000m {
 244                 compatible = "fixed-clock";
 245                 #clock-cells = <0>;
 246                 clock-frequency = <1000000000>;
 247                 clock-output-names = "pll_mac";
 248         };
 249
 250         pll_mm0: clk-pll-1188m {
 251                 compatible = "fixed-clock";
 252                 #clock-cells = <0>;
 253                 clock-frequency = <1188000000>;
 254                 clock-output-names = "pll_mm0";
 255         };
 256
 257         pll_mm1: clk-pll-1296m {
 258                 compatible = "fixed-clock";
 259                 #clock-cells = <0>;
 260                 clock-frequency = <1296000000>;
 261                 clock-output-names = "pll_mm1";
 262         };
 263
 264         psci {
 265                 compatible = "arm,psci-1.0";
 266                 method = "smc";
 267         };
 268
 269         timer {
 270                 compatible = "arm,armv8-timer";
 271                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 272                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 273                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 274                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 275         };
 276
 277         pmu {
 278                 compatible = "arm,cortex-a53-pmu";
 279                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 280         };
 281
 282         gic: interrupt-controller@2a00000 {
 283                 compatible = "arm,gic-v3";
 284                 #interrupt-cells = <3>;
 285                 #address-cells = <0>;
 286                 interrupt-controller;
 287                 reg = <0x02a00000 0x10000>,
 288                       <0x02b00000 0xc0000>;
 289                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 290         };
 291
 292         soc {
 293                 #address-cells = <1>;
 294                 #size-cells = <1>;
 295                 compatible = "simple-bus";
 296                 ranges;
 297
 298                 irdec: ir-decoder@111000 {
 299                         compatible = "zte,zx296718-irdec";
 300                         reg = <0x111000 0x1000>;
 301                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 302                         status = "disabled";
 303                 };
 304
 305                 aon_sysctrl: aon-sysctrl@116000 {
 306                         compatible = "zte,zx296718-aon-sysctrl", "syscon";
 307                         reg = <0x116000 0x1000>;
 308                 };
 309
 310                 iocfg: pin-controller@119000 {
 311                         compatible = "zte,zx296718-iocfg";
 312                         reg = <0x119000 0x1000>;
 313                 };
 314
 315                 uart0: uart@11f000 {
 316                         compatible = "arm,pl011", "arm,primecell";
 317                         arm,primecell-periphid = <0x001feffe>;
 318                         reg = <0x11f000 0x1000>;
 319                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 320                         clocks = <&osc24m>;
 321                         clock-names = "apb_pclk";
 322                         status = "disabled";
 323                 };
 324
 325                 sd0: mmc@1110000 {
 326                         compatible = "zte,zx296718-dw-mshc";
 327                         #address-cells = <1>;
 328                         #size-cells = <0>;
 329                         reg = <0x01110000 0x1000>;
 330                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 331                         fifo-depth = <32>;
 332                         data-addr = <0x200>;
 333                         fifo-watermark-aligned;
 334                         bus-width = <4>;
 335                         clock-frequency = <50000000>;
 336                         clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>;
 337                         clock-names = "biu", "ciu";
 338                         max-frequency = <50000000>;
 339                         cap-sdio-irq;
 340                         cap-sd-highspeed;
 341                         sd-uhs-sdr12;
 342                         sd-uhs-sdr25;
 343                         sd-uhs-sdr50;
 344                         sd-uhs-sdr104;
 345                         sd-uhs-ddr50;
 346                         status = "disabled";
 347                 };
 348
 349                 sd1: mmc@1111000 {
 350                         compatible = "zte,zx296718-dw-mshc";
 351                         #address-cells = <1>;
 352                         #size-cells = <0>;
 353                         reg = <0x01111000 0x1000>;
 354                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 355                         fifo-depth = <32>;
 356                         data-addr = <0x200>;
 357                         fifo-watermark-aligned;
 358                         bus-width = <4>;
 359                         clock-frequency = <167000000>;
 360                         clocks = <&topcrm SD1_AHB>, <&topcrm SD1_WCLK>;
 361                         clock-names = "biu", "ciu";
 362                         max-frequency = <167000000>;
 363                         cap-sdio-irq;
 364                         cap-sd-highspeed;
 365                         status = "disabled";
 366                 };
 367
 368                 dma: dma-controller@1460000 {
 369                         compatible = "zte,zx296702-dma";
 370                         reg = <0x01460000 0x1000>;
 371                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 372                         clocks = <&osc24m>;
 373                         clock-names = "dmaclk";
 374                         #dma-cells = <1>;
 375                         dma-channels = <32>;
 376                         dma-requests = <32>;
 377                 };
 378
 379                 lsp0crm: clock-controller@1420000 {
 380                         compatible = "zte,zx296718-lsp0crm";
 381                         reg = <0x01420000 0x1000>;
 382                         #clock-cells = <1>;
 383                 };
 384
 385                 bgpio0: gpio@142d000 {
 386                         compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
 387                         reg = <0x142d000 0x40>;
 388                         gpio-controller;
 389                         #gpio-cells = <2>;
 390                         gpio-ranges = <&pmm 0 48 16>;
 391                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 392                         interrupt-parent = <&gic>;
 393                         interrupt-controller;
 394                         #interrupt-cells = <2>;
 395                 };
 396
 397                 bgpio1: gpio@142d040 {
 398                         compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
 399                         reg = <0x142d040 0x40>;
 400                         gpio-controller;
 401                         #gpio-cells = <2>;
 402                         gpio-ranges = <&pmm 0 80 16>;
 403                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 404                         interrupt-parent = <&gic>;
 405                         interrupt-controller;
 406                         #interrupt-cells = <2>;
 407                 };
 408
 409                 bgpio2: gpio@142d080 {
 410                         compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
 411                         reg = <0x142d080 0x40>;
 412                         gpio-controller;
 413                         #gpio-cells = <2>;
 414                         gpio-ranges = <&pmm 0 80 3
 415                                        &pmm 3 32 4
 416                                        &pmm 7 83 9>;
 417                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 418                         interrupt-parent = <&gic>;
 419                         interrupt-controller;
 420                         #interrupt-cells = <2>;
 421                 };
 422
 423                 bgpio3: gpio@142d0c0 {
 424                         compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
 425                         reg = <0x142d0c0 0x40>;
 426                         gpio-controller;
 427                         #gpio-cells = <2>;
 428                         gpio-ranges = <&pmm 0 92 16>;
 429                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 430                         interrupt-parent = <&gic>;
 431                         interrupt-controller;
 432                         #interrupt-cells = <2>;
 433                 };
 434
 435                 bgpio4: gpio@142d100 {
 436                         compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
 437                         reg = <0x142d100 0x40>;
 438                         gpio-controller;
 439                         #gpio-cells = <2>;
 440                         gpio-ranges = <&pmm 0 108 12
 441                                        &pmm 12 121 4>;
 442                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 443                         interrupt-parent = <&gic>;
 444                         interrupt-controller;
 445                         #interrupt-cells = <2>;
 446                 };
 447
 448                 bgpio5: gpio@142d140 {
 449                         compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
 450                         reg = <0x142d140 0x40>;
 451                         gpio-controller;
 452                         #gpio-cells = <2>;
 453                         gpio-ranges = <&pmm 0 125 16>;
 454                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 455                         interrupt-parent = <&gic>;
 456                         interrupt-controller;
 457                         #interrupt-cells = <2>;
 458                 };
 459
 460                 bgpio6: gpio@142d180 {
 461                         compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
 462                         reg = <0x142d180 0x40>;
 463                         gpio-controller;
 464                         #gpio-cells = <2>;
 465                         gpio-ranges = <&pmm 0 141 2>;
 466                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 467                         interrupt-parent = <&gic>;
 468                         interrupt-controller;
 469                         #interrupt-cells = <2>;
 470                 };
 471
 472                 lsp1crm: clock-controller@1430000 {
 473                         compatible = "zte,zx296718-lsp1crm";
 474                         reg = <0x01430000 0x1000>;
 475                         #clock-cells = <1>;
 476                 };
 477
 478                 pwm: pwm@1439000 {
 479                         compatible = "zte,zx296718-pwm";
 480                         reg = <0x1439000 0x1000>;
 481                         clocks = <&lsp1crm LSP1_PWM_PCLK>,
 482                                  <&lsp1crm LSP1_PWM_WCLK>;
 483                         clock-names = "pclk", "wclk";
 484                         #pwm-cells = <3>;
 485                         status = "disabled";
 486                 };
 487
 488                 vou: vou@1440000 {
 489                         compatible = "zte,zx296718-vou";
 490                         #address-cells = <1>;
 491                         #size-cells = <1>;
 492                         ranges = <0 0x1440000 0x10000>;
 493
 494                         dpc: dpc@0 {
 495                                 compatible = "zte,zx296718-dpc";
 496                                 reg = <0x0000 0x1000>, <0x1000 0x1000>,
 497                                       <0x5000 0x1000>, <0x6000 0x1000>,
 498                                       <0xa000 0x1000>;
 499                                 reg-names = "osd", "timing_ctrl",
 500                                             "dtrc", "vou_ctrl",
 501                                             "otfppu";
 502                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 503                                 clocks = <&topcrm VOU_ACLK>, <&topcrm VOU_PPU_WCLK>,
 504                                          <&topcrm VOU_MAIN_WCLK>, <&topcrm VOU_AUX_WCLK>;
 505                                 clock-names = "aclk", "ppu_wclk",
 506                                               "main_wclk", "aux_wclk";
 507                         };
 508
 509                         vga: vga@8000 {
 510                                 compatible = "zte,zx296718-vga";
 511                                 reg = <0x8000 0x1000>;
 512                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 513                                 clocks = <&topcrm VGA_I2C_WCLK>;
 514                                 clock-names = "i2c_wclk";
 515                                 zte,vga-power-control = <&sysctrl 0x170 0xe0>;
 516                                 status = "disabled";
 517                         };
 518
 519                         hdmi: hdmi@c000 {
 520                                 compatible = "zte,zx296718-hdmi";
 521                                 reg = <0xc000 0x4000>;
 522                                 interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
 523                                 clocks = <&topcrm HDMI_OSC_CEC>,
 524                                          <&topcrm HDMI_OSC_CLK>,
 525                                          <&topcrm HDMI_XCLK>;
 526                                 clock-names = "osc_cec", "osc_clk", "xclk";
 527                                 #sound-dai-cells = <0>;
 528                                 status = "disabled";
 529                         };
 530
 531                         tvenc: tvenc@2000 {
 532                                 compatible = "zte,zx296718-tvenc";
 533                                 reg = <0x2000 0x1000>;
 534                                 zte,tvenc-power-control = <&sysctrl 0x170 0x10>;
 535                                 status = "disabled";
 536                         };
 537                 };
 538
 539                 topcrm: clock-controller@1461000 {
 540                         compatible = "zte,zx296718-topcrm";
 541                         reg = <0x01461000 0x1000>;
 542                         #clock-cells = <1>;
 543                 };
 544
 545                 pmm: pin-controller@1462000 {
 546                         compatible = "zte,zx296718-pmm";
 547                         reg = <0x1462000 0x1000>;
 548                         zte,auxiliary-controller = <&iocfg>;
 549                 };
 550
 551                 sysctrl: sysctrl@1463000 {
 552                         compatible = "zte,zx296718-sysctrl", "syscon";
 553                         reg = <0x1463000 0x1000>;
 554                 };
 555
 556                 emmc: mmc@1470000{
 557                         compatible = "zte,zx296718-dw-mshc";
 558                         reg = <0x01470000 0x1000>;
 559                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 560                         zte,aon-syscon = <&aon_sysctrl>;
 561                         bus-width = <8>;
 562                         fifo-depth = <128>;
 563                         data-addr = <0x200>;
 564                         fifo-watermark-aligned;
 565                         clock-frequency = <167000000>;
 566                         clocks = <&topcrm EMMC_NAND_AHB>, <&topcrm EMMC_WCLK>;
 567                         clock-names = "biu", "ciu";
 568                         max-frequency = <167000000>;
 569                         cap-mmc-highspeed;
 570                         mmc-ddr-1_8v;
 571                         mmc-hs200-1_8v;
 572                         non-removable;
 573                         disable-wp;
 574                         status = "disabled";
 575                 };
 576
 577                 audiocrm: clock-controller@1480000 {
 578                         compatible = "zte,zx296718-audiocrm";
 579                         reg = <0x01480000 0x1000>;
 580                         #clock-cells = <1>;
 581                 };
 582
 583                 i2s0: i2s@1482000 {
 584                         compatible = "zte,zx296718-i2s", "zte,zx296702-i2s";
 585                         reg = <0x01482000 0x1000>;
 586                         clocks = <&audiocrm AUDIO_I2S0_WCLK>,
 587                                  <&audiocrm AUDIO_I2S0_PCLK>;
 588                         clock-names = "wclk", "pclk";
 589                         assigned-clocks = <&audiocrm I2S0_WCLK_MUX>;
 590                         assigned-clock-parents = <&topcrm AUDIO_99M>;
 591                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 592                         dmas = <&dma 22>, <&dma 23>;
 593                         dma-names = "tx", "rx";
 594                         #sound-dai-cells = <0>;
 595                         status = "disabled";
 596                 };
 597
 598                 i2c0: i2c@1486000 {
 599                         compatible = "zte,zx296718-i2c";
 600                         reg = <0x01486000 0x1000>;
 601                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 602                         #address-cells = <1>;
 603                         #size-cells = <0>;
 604                         clocks = <&audiocrm AUDIO_I2C0_WCLK>;
 605                         clock-frequency = <1600000>;
 606                         status = "disabled";
 607
 608                         aud96p22: codec@22 {
 609                                 compatible = "zte,zx-aud96p22";
 610                                 #sound-dai-cells = <0>;
 611                                 reg = <0x22>;
 612                         };
 613                 };
 614
 615                 spdif0: spdif@1488000 {
 616                         compatible = "zte,zx296702-spdif";
 617                         reg = <0x1488000 0x1000>;
 618                         clocks = <&audiocrm AUDIO_SPDIF0_WCLK>;
 619                         clock-names = "tx";
 620                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 621                         #sound-dai-cells = <0>;
 622                         dmas = <&dma 30>;
 623                         dma-names = "tx";
 624                         status = "disabled";
 625                 };
 626         };
 627 };