2 * dts file for Xilinx ZynqMP
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
6 * Michal Simek <michal.simek@xilinx.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
15 compatible = "xlnx,zynqmp";
24 compatible = "arm,cortex-a53", "arm,armv8";
26 enable-method = "psci";
31 compatible = "arm,cortex-a53", "arm,armv8";
33 enable-method = "psci";
38 compatible = "arm,cortex-a53", "arm,armv8";
40 enable-method = "psci";
45 compatible = "arm,cortex-a53", "arm,armv8";
47 enable-method = "psci";
53 compatible = "arm,armv8-pmuv3";
54 interrupt-parent = <&gic>;
55 interrupts = <0 143 4>,
62 compatible = "arm,psci-0.2";
67 compatible = "arm,armv8-timer";
68 interrupt-parent = <&gic>;
69 interrupts = <1 13 0xf08>,
75 amba_apu: amba_apu@0 {
76 compatible = "simple-bus";
79 ranges = <0 0 0 0 0xffffffff>;
81 gic: interrupt-controller@f9010000 {
82 compatible = "arm,gic-400", "arm,cortex-a15-gic";
83 #interrupt-cells = <3>;
84 reg = <0x0 0xf9010000 0x10000>,
85 <0x0 0xf9020000 0x20000>,
86 <0x0 0xf9040000 0x20000>,
87 <0x0 0xf9060000 0x20000>;
89 interrupt-parent = <&gic>;
90 interrupts = <1 9 0xf04>;
95 compatible = "simple-bus";
101 compatible = "xlnx,zynq-can-1.0";
103 clock-names = "can_clk", "pclk";
104 reg = <0x0 0xff060000 0x0 0x1000>;
105 interrupts = <0 23 4>;
106 interrupt-parent = <&gic>;
107 tx-fifo-depth = <0x40>;
108 rx-fifo-depth = <0x40>;
112 compatible = "xlnx,zynq-can-1.0";
114 clock-names = "can_clk", "pclk";
115 reg = <0x0 0xff070000 0x0 0x1000>;
116 interrupts = <0 24 4>;
117 interrupt-parent = <&gic>;
118 tx-fifo-depth = <0x40>;
119 rx-fifo-depth = <0x40>;
122 gem0: ethernet@ff0b0000 {
123 compatible = "cdns,gem";
125 interrupt-parent = <&gic>;
126 interrupts = <0 57 4>, <0 57 4>;
127 reg = <0x0 0xff0b0000 0x0 0x1000>;
128 clock-names = "pclk", "hclk", "tx_clk";
129 #address-cells = <1>;
133 gem1: ethernet@ff0c0000 {
134 compatible = "cdns,gem";
136 interrupt-parent = <&gic>;
137 interrupts = <0 59 4>, <0 59 4>;
138 reg = <0x0 0xff0c0000 0x0 0x1000>;
139 clock-names = "pclk", "hclk", "tx_clk";
140 #address-cells = <1>;
144 gem2: ethernet@ff0d0000 {
145 compatible = "cdns,gem";
147 interrupt-parent = <&gic>;
148 interrupts = <0 61 4>, <0 61 4>;
149 reg = <0x0 0xff0d0000 0x0 0x1000>;
150 clock-names = "pclk", "hclk", "tx_clk";
151 #address-cells = <1>;
155 gem3: ethernet@ff0e0000 {
156 compatible = "cdns,gem";
158 interrupt-parent = <&gic>;
159 interrupts = <0 63 4>, <0 63 4>;
160 reg = <0x0 0xff0e0000 0x0 0x1000>;
161 clock-names = "pclk", "hclk", "tx_clk";
162 #address-cells = <1>;
166 gpio: gpio@ff0a0000 {
167 compatible = "xlnx,zynqmp-gpio-1.0";
170 interrupt-parent = <&gic>;
171 interrupts = <0 16 4>;
172 interrupt-controller;
173 #interrupt-cells = <2>;
174 reg = <0x0 0xff0a0000 0x0 0x1000>;
178 compatible = "cdns,i2c-r1p14";
180 interrupt-parent = <&gic>;
181 interrupts = <0 17 4>;
182 reg = <0x0 0xff020000 0x0 0x1000>;
183 #address-cells = <1>;
188 compatible = "cdns,i2c-r1p14";
190 interrupt-parent = <&gic>;
191 interrupts = <0 18 4>;
192 reg = <0x0 0xff030000 0x0 0x1000>;
193 #address-cells = <1>;
197 pcie: pcie@fd0e0000 {
198 compatible = "xlnx,nwl-pcie-2.11";
200 #address-cells = <3>;
202 #interrupt-cells = <1>;
205 interrupt-parent = <&gic>;
206 interrupts = <0 118 4>,
209 <0 115 4>, /* MSI_1 [63...32] */
210 <0 114 4>; /* MSI_0 [31...0] */
211 interrupt-names = "misc", "dummy", "intx",
213 msi-parent = <&pcie>;
214 reg = <0x0 0xfd0e0000 0x0 0x1000>,
215 <0x0 0xfd480000 0x0 0x1000>,
216 <0x80 0x00000000 0x0 0x1000000>;
217 reg-names = "breg", "pcireg", "cfg";
218 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000
219 0xe0000000 0x00000000 0x10000000
220 /* non-prefetchable memory */
221 0x43000000 0x00000006 0x00000000 0x00000006
222 0x00000000 0x00000002 0x00000000>;
223 /* prefetchable memory */
224 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
225 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
226 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
227 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
228 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
229 pcie_intc: legacy-interrupt-controller {
230 interrupt-controller;
231 #address-cells = <0>;
232 #interrupt-cells = <1>;
236 sata: ahci@fd0c0000 {
237 compatible = "ceva,ahci-1v84";
239 reg = <0x0 0xfd0c0000 0x0 0x2000>;
240 interrupt-parent = <&gic>;
241 interrupts = <0 133 4>;
244 sdhci0: sdhci@ff160000 {
245 compatible = "arasan,sdhci-8.9a";
247 interrupt-parent = <&gic>;
248 interrupts = <0 48 4>;
249 reg = <0x0 0xff160000 0x0 0x1000>;
250 clock-names = "clk_xin", "clk_ahb";
253 sdhci1: sdhci@ff170000 {
254 compatible = "arasan,sdhci-8.9a";
256 interrupt-parent = <&gic>;
257 interrupts = <0 49 4>;
258 reg = <0x0 0xff170000 0x0 0x1000>;
259 clock-names = "clk_xin", "clk_ahb";
262 smmu: smmu@fd800000 {
263 compatible = "arm,mmu-500";
264 reg = <0x0 0xfd800000 0x0 0x20000>;
265 #global-interrupts = <1>;
266 interrupt-parent = <&gic>;
267 interrupts = <0 157 4>,
268 <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
269 <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
270 <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
271 <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>;
275 compatible = "cdns,spi-r1p6";
277 interrupt-parent = <&gic>;
278 interrupts = <0 19 4>;
279 reg = <0x0 0xff040000 0x0 0x1000>;
280 clock-names = "ref_clk", "pclk";
281 #address-cells = <1>;
286 compatible = "cdns,spi-r1p6";
288 interrupt-parent = <&gic>;
289 interrupts = <0 20 4>;
290 reg = <0x0 0xff050000 0x0 0x1000>;
291 clock-names = "ref_clk", "pclk";
292 #address-cells = <1>;
296 ttc0: timer@ff110000 {
297 compatible = "cdns,ttc";
299 interrupt-parent = <&gic>;
300 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
301 reg = <0x0 0xff110000 0x0 0x1000>;
305 ttc1: timer@ff120000 {
306 compatible = "cdns,ttc";
308 interrupt-parent = <&gic>;
309 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
310 reg = <0x0 0xff120000 0x0 0x1000>;
314 ttc2: timer@ff130000 {
315 compatible = "cdns,ttc";
317 interrupt-parent = <&gic>;
318 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
319 reg = <0x0 0xff130000 0x0 0x1000>;
323 ttc3: timer@ff140000 {
324 compatible = "cdns,ttc";
326 interrupt-parent = <&gic>;
327 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
328 reg = <0x0 0xff140000 0x0 0x1000>;
332 uart0: serial@ff000000 {
333 compatible = "cdns,uart-r1p8";
335 interrupt-parent = <&gic>;
336 interrupts = <0 21 4>;
337 reg = <0x0 0xff000000 0x0 0x1000>;
338 clock-names = "uart_clk", "pclk";
341 uart1: serial@ff010000 {
342 compatible = "cdns,uart-r1p8";
344 interrupt-parent = <&gic>;
345 interrupts = <0 22 4>;
346 reg = <0x0 0xff010000 0x0 0x1000>;
347 clock-names = "uart_clk", "pclk";
351 compatible = "snps,dwc3";
353 interrupt-parent = <&gic>;
354 interrupts = <0 65 4>;
355 reg = <0x0 0xfe200000 0x0 0x40000>;
356 clock-names = "clk_xin", "clk_ahb";
360 compatible = "snps,dwc3";
362 interrupt-parent = <&gic>;
363 interrupts = <0 70 4>;
364 reg = <0x0 0xfe300000 0x0 0x40000>;
365 clock-names = "clk_xin", "clk_ahb";
368 watchdog0: watchdog@fd4d0000 {
369 compatible = "cdns,wdt-r1p2";
371 interrupt-parent = <&gic>;
372 interrupts = <0 113 1>;
373 reg = <0x0 0xfd4d0000 0x0 0x1000>;