1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
7 * Michal Simek <michal.simek@amd.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
23 compatible = "xlnx,zynqmp";
32 compatible = "arm,cortex-a53";
34 enable-method = "psci";
35 operating-points-v2 = <&cpu_opp_table>;
37 cpu-idle-states = <&CPU_SLEEP_0>;
38 next-level-cache = <&L2>;
42 compatible = "arm,cortex-a53";
44 enable-method = "psci";
46 operating-points-v2 = <&cpu_opp_table>;
47 cpu-idle-states = <&CPU_SLEEP_0>;
48 next-level-cache = <&L2>;
52 compatible = "arm,cortex-a53";
54 enable-method = "psci";
56 operating-points-v2 = <&cpu_opp_table>;
57 cpu-idle-states = <&CPU_SLEEP_0>;
58 next-level-cache = <&L2>;
62 compatible = "arm,cortex-a53";
64 enable-method = "psci";
66 operating-points-v2 = <&cpu_opp_table>;
67 cpu-idle-states = <&CPU_SLEEP_0>;
68 next-level-cache = <&L2>;
78 entry-method = "psci";
80 CPU_SLEEP_0: cpu-sleep-0 {
81 compatible = "arm,idle-state";
82 arm,psci-suspend-param = <0x40000000>;
84 entry-latency-us = <300>;
85 exit-latency-us = <600>;
86 min-residency-us = <10000>;
91 cpu_opp_table: opp-table-cpu {
92 compatible = "operating-points-v2";
95 opp-hz = /bits/ 64 <1199999988>;
96 opp-microvolt = <1000000>;
97 clock-latency-ns = <500000>;
100 opp-hz = /bits/ 64 <599999994>;
101 opp-microvolt = <1000000>;
102 clock-latency-ns = <500000>;
105 opp-hz = /bits/ 64 <399999996>;
106 opp-microvolt = <1000000>;
107 clock-latency-ns = <500000>;
110 opp-hz = /bits/ 64 <299999997>;
111 opp-microvolt = <1000000>;
112 clock-latency-ns = <500000>;
117 #address-cells = <2>;
121 rproc_0_fw_image: memory@3ed00000 {
123 reg = <0x0 0x3ed00000 0x0 0x40000>;
126 rproc_1_fw_image: memory@3ef00000 {
128 reg = <0x0 0x3ef00000 0x0 0x40000>;
132 zynqmp_ipi: zynqmp_ipi {
134 compatible = "xlnx,zynqmp-ipi-mailbox";
135 interrupt-parent = <&gic>;
136 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
138 #address-cells = <2>;
142 ipi_mailbox_pmu1: mailbox@ff9905c0 {
144 reg = <0x0 0xff9905c0 0x0 0x20>,
145 <0x0 0xff9905e0 0x0 0x20>,
146 <0x0 0xff990e80 0x0 0x20>,
147 <0x0 0xff990ea0 0x0 0x20>;
148 reg-names = "local_request_region",
149 "local_response_region",
150 "remote_request_region",
151 "remote_response_region";
158 compatible = "arm,dcc";
164 compatible = "arm,armv8-pmuv3";
165 interrupt-parent = <&gic>;
166 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
170 interrupt-affinity = <&cpu0>,
177 compatible = "arm,psci-0.2";
182 zynqmp_firmware: zynqmp-firmware {
183 compatible = "xlnx,zynqmp-firmware";
184 #power-domain-cells = <1>;
188 zynqmp_power: zynqmp-power {
190 compatible = "xlnx,zynqmp-power";
191 interrupt-parent = <&gic>;
192 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
193 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
194 mbox-names = "tx", "rx";
198 compatible = "xlnx,zynqmp-nvmem-fw";
199 #address-cells = <1>;
202 soc_revision: soc_revision@0 {
208 compatible = "xlnx,zynqmp-pcap-fpga";
211 xlnx_aes: zynqmp-aes {
212 compatible = "xlnx,zynqmp-aes";
215 zynqmp_reset: reset-controller {
216 compatible = "xlnx,zynqmp-reset";
221 compatible = "xlnx,zynqmp-pinctrl";
226 compatible = "xlnx,zynqmp-gpio-modepin";
234 compatible = "arm,armv8-timer";
235 interrupt-parent = <&gic>;
236 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
237 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
238 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
239 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
242 fpga_full: fpga-full {
243 compatible = "fpga-region";
244 fpga-mgr = <&zynqmp_pcap>;
245 #address-cells = <2>;
251 compatible = "xlnx,zynqmp-r5fss";
252 xlnx,cluster-mode = <1>;
255 compatible = "xlnx,zynqmp-r5f";
256 power-domains = <&zynqmp_firmware PD_RPU_0>;
257 memory-region = <&rproc_0_fw_image>;
261 compatible = "xlnx,zynqmp-r5f";
262 power-domains = <&zynqmp_firmware PD_RPU_1>;
263 memory-region = <&rproc_1_fw_image>;
268 compatible = "simple-bus";
270 #address-cells = <2>;
275 compatible = "xlnx,zynq-can-1.0";
277 clock-names = "can_clk", "pclk";
278 reg = <0x0 0xff060000 0x0 0x1000>;
279 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
280 interrupt-parent = <&gic>;
281 tx-fifo-depth = <0x40>;
282 rx-fifo-depth = <0x40>;
283 power-domains = <&zynqmp_firmware PD_CAN_0>;
287 compatible = "xlnx,zynq-can-1.0";
289 clock-names = "can_clk", "pclk";
290 reg = <0x0 0xff070000 0x0 0x1000>;
291 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
292 interrupt-parent = <&gic>;
293 tx-fifo-depth = <0x40>;
294 rx-fifo-depth = <0x40>;
295 power-domains = <&zynqmp_firmware PD_CAN_1>;
299 compatible = "arm,cci-400";
301 reg = <0x0 0xfd6e0000 0x0 0x9000>;
302 ranges = <0x0 0x0 0xfd6e0000 0x10000>;
303 #address-cells = <1>;
307 compatible = "arm,cci-400-pmu,r1";
308 reg = <0x9000 0x5000>;
309 interrupt-parent = <&gic>;
310 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
319 fpd_dma_chan1: dma-controller@fd500000 {
321 compatible = "xlnx,zynqmp-dma-1.0";
322 reg = <0x0 0xfd500000 0x0 0x1000>;
323 interrupt-parent = <&gic>;
324 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
325 clock-names = "clk_main", "clk_apb";
327 xlnx,bus-width = <128>;
328 iommus = <&smmu 0x14e8>;
329 power-domains = <&zynqmp_firmware PD_GDMA>;
332 fpd_dma_chan2: dma-controller@fd510000 {
334 compatible = "xlnx,zynqmp-dma-1.0";
335 reg = <0x0 0xfd510000 0x0 0x1000>;
336 interrupt-parent = <&gic>;
337 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
338 clock-names = "clk_main", "clk_apb";
340 xlnx,bus-width = <128>;
341 iommus = <&smmu 0x14e9>;
342 power-domains = <&zynqmp_firmware PD_GDMA>;
345 fpd_dma_chan3: dma-controller@fd520000 {
347 compatible = "xlnx,zynqmp-dma-1.0";
348 reg = <0x0 0xfd520000 0x0 0x1000>;
349 interrupt-parent = <&gic>;
350 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
351 clock-names = "clk_main", "clk_apb";
353 xlnx,bus-width = <128>;
354 iommus = <&smmu 0x14ea>;
355 power-domains = <&zynqmp_firmware PD_GDMA>;
358 fpd_dma_chan4: dma-controller@fd530000 {
360 compatible = "xlnx,zynqmp-dma-1.0";
361 reg = <0x0 0xfd530000 0x0 0x1000>;
362 interrupt-parent = <&gic>;
363 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
364 clock-names = "clk_main", "clk_apb";
366 xlnx,bus-width = <128>;
367 iommus = <&smmu 0x14eb>;
368 power-domains = <&zynqmp_firmware PD_GDMA>;
371 fpd_dma_chan5: dma-controller@fd540000 {
373 compatible = "xlnx,zynqmp-dma-1.0";
374 reg = <0x0 0xfd540000 0x0 0x1000>;
375 interrupt-parent = <&gic>;
376 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
377 clock-names = "clk_main", "clk_apb";
379 xlnx,bus-width = <128>;
380 iommus = <&smmu 0x14ec>;
381 power-domains = <&zynqmp_firmware PD_GDMA>;
384 fpd_dma_chan6: dma-controller@fd550000 {
386 compatible = "xlnx,zynqmp-dma-1.0";
387 reg = <0x0 0xfd550000 0x0 0x1000>;
388 interrupt-parent = <&gic>;
389 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
390 clock-names = "clk_main", "clk_apb";
392 xlnx,bus-width = <128>;
393 iommus = <&smmu 0x14ed>;
394 power-domains = <&zynqmp_firmware PD_GDMA>;
397 fpd_dma_chan7: dma-controller@fd560000 {
399 compatible = "xlnx,zynqmp-dma-1.0";
400 reg = <0x0 0xfd560000 0x0 0x1000>;
401 interrupt-parent = <&gic>;
402 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
403 clock-names = "clk_main", "clk_apb";
405 xlnx,bus-width = <128>;
406 iommus = <&smmu 0x14ee>;
407 power-domains = <&zynqmp_firmware PD_GDMA>;
410 fpd_dma_chan8: dma-controller@fd570000 {
412 compatible = "xlnx,zynqmp-dma-1.0";
413 reg = <0x0 0xfd570000 0x0 0x1000>;
414 interrupt-parent = <&gic>;
415 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
416 clock-names = "clk_main", "clk_apb";
418 xlnx,bus-width = <128>;
419 iommus = <&smmu 0x14ef>;
420 power-domains = <&zynqmp_firmware PD_GDMA>;
423 gic: interrupt-controller@f9010000 {
424 compatible = "arm,gic-400";
425 #interrupt-cells = <3>;
426 reg = <0x0 0xf9010000 0x0 0x10000>,
427 <0x0 0xf9020000 0x0 0x20000>,
428 <0x0 0xf9040000 0x0 0x20000>,
429 <0x0 0xf9060000 0x0 0x20000>;
430 interrupt-controller;
431 interrupt-parent = <&gic>;
432 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
437 compatible = "xlnx,zynqmp-mali", "arm,mali-400";
438 reg = <0x0 0xfd4b0000 0x0 0x10000>;
439 interrupt-parent = <&gic>;
440 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
446 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1";
447 clock-names = "bus", "core";
448 power-domains = <&zynqmp_firmware PD_GPU>;
451 /* LPDDMA default allows only secured access. inorder to enable
452 * These dma channels, Users should ensure that these dma
453 * Channels are allowed for non secure access.
455 lpd_dma_chan1: dma-controller@ffa80000 {
457 compatible = "xlnx,zynqmp-dma-1.0";
458 reg = <0x0 0xffa80000 0x0 0x1000>;
459 interrupt-parent = <&gic>;
460 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
461 clock-names = "clk_main", "clk_apb";
463 xlnx,bus-width = <64>;
464 iommus = <&smmu 0x868>;
465 power-domains = <&zynqmp_firmware PD_ADMA>;
468 lpd_dma_chan2: dma-controller@ffa90000 {
470 compatible = "xlnx,zynqmp-dma-1.0";
471 reg = <0x0 0xffa90000 0x0 0x1000>;
472 interrupt-parent = <&gic>;
473 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
474 clock-names = "clk_main", "clk_apb";
476 xlnx,bus-width = <64>;
477 iommus = <&smmu 0x869>;
478 power-domains = <&zynqmp_firmware PD_ADMA>;
481 lpd_dma_chan3: dma-controller@ffaa0000 {
483 compatible = "xlnx,zynqmp-dma-1.0";
484 reg = <0x0 0xffaa0000 0x0 0x1000>;
485 interrupt-parent = <&gic>;
486 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
487 clock-names = "clk_main", "clk_apb";
489 xlnx,bus-width = <64>;
490 iommus = <&smmu 0x86a>;
491 power-domains = <&zynqmp_firmware PD_ADMA>;
494 lpd_dma_chan4: dma-controller@ffab0000 {
496 compatible = "xlnx,zynqmp-dma-1.0";
497 reg = <0x0 0xffab0000 0x0 0x1000>;
498 interrupt-parent = <&gic>;
499 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
500 clock-names = "clk_main", "clk_apb";
502 xlnx,bus-width = <64>;
503 iommus = <&smmu 0x86b>;
504 power-domains = <&zynqmp_firmware PD_ADMA>;
507 lpd_dma_chan5: dma-controller@ffac0000 {
509 compatible = "xlnx,zynqmp-dma-1.0";
510 reg = <0x0 0xffac0000 0x0 0x1000>;
511 interrupt-parent = <&gic>;
512 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
513 clock-names = "clk_main", "clk_apb";
515 xlnx,bus-width = <64>;
516 iommus = <&smmu 0x86c>;
517 power-domains = <&zynqmp_firmware PD_ADMA>;
520 lpd_dma_chan6: dma-controller@ffad0000 {
522 compatible = "xlnx,zynqmp-dma-1.0";
523 reg = <0x0 0xffad0000 0x0 0x1000>;
524 interrupt-parent = <&gic>;
525 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
526 clock-names = "clk_main", "clk_apb";
528 xlnx,bus-width = <64>;
529 iommus = <&smmu 0x86d>;
530 power-domains = <&zynqmp_firmware PD_ADMA>;
533 lpd_dma_chan7: dma-controller@ffae0000 {
535 compatible = "xlnx,zynqmp-dma-1.0";
536 reg = <0x0 0xffae0000 0x0 0x1000>;
537 interrupt-parent = <&gic>;
538 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
539 clock-names = "clk_main", "clk_apb";
541 xlnx,bus-width = <64>;
542 iommus = <&smmu 0x86e>;
543 power-domains = <&zynqmp_firmware PD_ADMA>;
546 lpd_dma_chan8: dma-controller@ffaf0000 {
548 compatible = "xlnx,zynqmp-dma-1.0";
549 reg = <0x0 0xffaf0000 0x0 0x1000>;
550 interrupt-parent = <&gic>;
551 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
552 clock-names = "clk_main", "clk_apb";
554 xlnx,bus-width = <64>;
555 iommus = <&smmu 0x86f>;
556 power-domains = <&zynqmp_firmware PD_ADMA>;
559 mc: memory-controller@fd070000 {
560 compatible = "xlnx,zynqmp-ddrc-2.40a";
561 reg = <0x0 0xfd070000 0x0 0x30000>;
562 interrupt-parent = <&gic>;
563 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
566 nand0: nand-controller@ff100000 {
567 compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
569 reg = <0x0 0xff100000 0x0 0x1000>;
570 clock-names = "controller", "bus";
571 interrupt-parent = <&gic>;
572 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
573 #address-cells = <1>;
575 iommus = <&smmu 0x872>;
576 power-domains = <&zynqmp_firmware PD_NAND>;
579 gem0: ethernet@ff0b0000 {
580 compatible = "xlnx,zynqmp-gem", "cdns,gem";
582 interrupt-parent = <&gic>;
583 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
585 reg = <0x0 0xff0b0000 0x0 0x1000>;
586 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
587 #address-cells = <1>;
589 iommus = <&smmu 0x874>;
590 power-domains = <&zynqmp_firmware PD_ETH_0>;
591 resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;
592 reset-names = "gem0_rst";
595 gem1: ethernet@ff0c0000 {
596 compatible = "xlnx,zynqmp-gem", "cdns,gem";
598 interrupt-parent = <&gic>;
599 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
601 reg = <0x0 0xff0c0000 0x0 0x1000>;
602 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
603 #address-cells = <1>;
605 iommus = <&smmu 0x875>;
606 power-domains = <&zynqmp_firmware PD_ETH_1>;
607 resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
608 reset-names = "gem1_rst";
611 gem2: ethernet@ff0d0000 {
612 compatible = "xlnx,zynqmp-gem", "cdns,gem";
614 interrupt-parent = <&gic>;
615 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
616 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
617 reg = <0x0 0xff0d0000 0x0 0x1000>;
618 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
619 #address-cells = <1>;
621 iommus = <&smmu 0x876>;
622 power-domains = <&zynqmp_firmware PD_ETH_2>;
623 resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;
624 reset-names = "gem2_rst";
627 gem3: ethernet@ff0e0000 {
628 compatible = "xlnx,zynqmp-gem", "cdns,gem";
630 interrupt-parent = <&gic>;
631 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
632 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
633 reg = <0x0 0xff0e0000 0x0 0x1000>;
634 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
635 #address-cells = <1>;
637 iommus = <&smmu 0x877>;
638 power-domains = <&zynqmp_firmware PD_ETH_3>;
639 resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;
640 reset-names = "gem3_rst";
643 gpio: gpio@ff0a0000 {
644 compatible = "xlnx,zynqmp-gpio-1.0";
648 interrupt-parent = <&gic>;
649 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
650 interrupt-controller;
651 #interrupt-cells = <2>;
652 reg = <0x0 0xff0a0000 0x0 0x1000>;
653 power-domains = <&zynqmp_firmware PD_GPIO>;
657 compatible = "cdns,i2c-r1p14";
659 interrupt-parent = <&gic>;
660 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
661 clock-frequency = <400000>;
662 reg = <0x0 0xff020000 0x0 0x1000>;
663 #address-cells = <1>;
665 power-domains = <&zynqmp_firmware PD_I2C_0>;
669 compatible = "cdns,i2c-r1p14";
671 interrupt-parent = <&gic>;
672 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
673 clock-frequency = <400000>;
674 reg = <0x0 0xff030000 0x0 0x1000>;
675 #address-cells = <1>;
677 power-domains = <&zynqmp_firmware PD_I2C_1>;
680 pcie: pcie@fd0e0000 {
681 compatible = "xlnx,nwl-pcie-2.11";
683 #address-cells = <3>;
685 #interrupt-cells = <1>;
688 interrupt-parent = <&gic>;
689 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
690 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
691 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
692 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, /* MSI_1 [63...32] */
693 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; /* MSI_0 [31...0] */
694 interrupt-names = "misc", "dummy", "intx",
696 msi-parent = <&pcie>;
697 reg = <0x0 0xfd0e0000 0x0 0x1000>,
698 <0x0 0xfd480000 0x0 0x1000>,
699 <0x80 0x00000000 0x0 0x1000000>;
700 reg-names = "breg", "pcireg", "cfg";
701 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */
702 <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
703 bus-range = <0x00 0xff>;
704 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
705 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
706 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
707 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
708 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
709 iommus = <&smmu 0x4d0>;
710 power-domains = <&zynqmp_firmware PD_PCIE>;
711 pcie_intc: legacy-interrupt-controller {
712 interrupt-controller;
713 #address-cells = <0>;
714 #interrupt-cells = <1>;
720 compatible = "xlnx,zynqmp-qspi-1.0";
722 clock-names = "ref_clk", "pclk";
723 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
724 interrupt-parent = <&gic>;
726 reg = <0x0 0xff0f0000 0x0 0x1000>,
727 <0x0 0xc0000000 0x0 0x8000000>;
728 #address-cells = <1>;
730 iommus = <&smmu 0x873>;
731 power-domains = <&zynqmp_firmware PD_QSPI>;
734 psgtr: phy@fd400000 {
735 compatible = "xlnx,zynqmp-psgtr-v1.1";
737 reg = <0x0 0xfd400000 0x0 0x40000>,
738 <0x0 0xfd3d0000 0x0 0x1000>;
739 reg-names = "serdes", "siou";
744 compatible = "xlnx,zynqmp-rtc";
746 reg = <0x0 0xffa60000 0x0 0x100>;
747 interrupt-parent = <&gic>;
748 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
750 interrupt-names = "alarm", "sec";
751 calibration = <0x7FFF>;
754 sata: ahci@fd0c0000 {
755 compatible = "ceva,ahci-1v84";
757 reg = <0x0 0xfd0c0000 0x0 0x2000>;
758 interrupt-parent = <&gic>;
759 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
760 power-domains = <&zynqmp_firmware PD_SATA>;
761 resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
762 iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
763 <&smmu 0x4c2>, <&smmu 0x4c3>;
766 sdhci0: mmc@ff160000 {
768 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
770 interrupt-parent = <&gic>;
771 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
772 reg = <0x0 0xff160000 0x0 0x1000>;
773 clock-names = "clk_xin", "clk_ahb";
774 iommus = <&smmu 0x870>;
776 clock-output-names = "clk_out_sd0", "clk_in_sd0";
777 power-domains = <&zynqmp_firmware PD_SD_0>;
778 resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>;
781 sdhci1: mmc@ff170000 {
783 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
785 interrupt-parent = <&gic>;
786 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
787 reg = <0x0 0xff170000 0x0 0x1000>;
788 clock-names = "clk_xin", "clk_ahb";
789 iommus = <&smmu 0x871>;
791 clock-output-names = "clk_out_sd1", "clk_in_sd1";
792 power-domains = <&zynqmp_firmware PD_SD_1>;
793 resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>;
796 smmu: iommu@fd800000 {
797 compatible = "arm,mmu-500";
798 reg = <0x0 0xfd800000 0x0 0x20000>;
801 #global-interrupts = <1>;
802 interrupt-parent = <&gic>;
803 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
804 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
805 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
806 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
807 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
808 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
809 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
810 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
811 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
812 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
813 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
814 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
815 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
816 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
817 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
818 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
819 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
823 compatible = "cdns,spi-r1p6";
825 interrupt-parent = <&gic>;
826 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
827 reg = <0x0 0xff040000 0x0 0x1000>;
828 clock-names = "ref_clk", "pclk";
829 #address-cells = <1>;
831 power-domains = <&zynqmp_firmware PD_SPI_0>;
835 compatible = "cdns,spi-r1p6";
837 interrupt-parent = <&gic>;
838 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
839 reg = <0x0 0xff050000 0x0 0x1000>;
840 clock-names = "ref_clk", "pclk";
841 #address-cells = <1>;
843 power-domains = <&zynqmp_firmware PD_SPI_1>;
846 ttc0: timer@ff110000 {
847 compatible = "cdns,ttc";
849 interrupt-parent = <&gic>;
850 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
851 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
852 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
853 reg = <0x0 0xff110000 0x0 0x1000>;
855 power-domains = <&zynqmp_firmware PD_TTC_0>;
858 ttc1: timer@ff120000 {
859 compatible = "cdns,ttc";
861 interrupt-parent = <&gic>;
862 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
863 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
864 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
865 reg = <0x0 0xff120000 0x0 0x1000>;
867 power-domains = <&zynqmp_firmware PD_TTC_1>;
870 ttc2: timer@ff130000 {
871 compatible = "cdns,ttc";
873 interrupt-parent = <&gic>;
874 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
875 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
876 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
877 reg = <0x0 0xff130000 0x0 0x1000>;
879 power-domains = <&zynqmp_firmware PD_TTC_2>;
882 ttc3: timer@ff140000 {
883 compatible = "cdns,ttc";
885 interrupt-parent = <&gic>;
886 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
887 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
888 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
889 reg = <0x0 0xff140000 0x0 0x1000>;
891 power-domains = <&zynqmp_firmware PD_TTC_3>;
894 uart0: serial@ff000000 {
896 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
898 interrupt-parent = <&gic>;
899 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
900 reg = <0x0 0xff000000 0x0 0x1000>;
901 clock-names = "uart_clk", "pclk";
902 power-domains = <&zynqmp_firmware PD_UART_0>;
905 uart1: serial@ff010000 {
907 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
909 interrupt-parent = <&gic>;
910 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
911 reg = <0x0 0xff010000 0x0 0x1000>;
912 clock-names = "uart_clk", "pclk";
913 power-domains = <&zynqmp_firmware PD_UART_1>;
917 #address-cells = <2>;
920 compatible = "xlnx,zynqmp-dwc3";
921 reg = <0x0 0xff9d0000 0x0 0x100>;
922 power-domains = <&zynqmp_firmware PD_USB_0>;
923 resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
924 <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
925 <&zynqmp_reset ZYNQMP_RESET_USB0_APB>;
926 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
927 reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;
930 dwc3_0: usb@fe200000 {
931 compatible = "snps,dwc3";
932 reg = <0x0 0xfe200000 0x0 0x40000>;
933 interrupt-parent = <&gic>;
934 interrupt-names = "host", "peripheral", "otg";
935 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
936 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
937 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
938 clock-names = "bus_early", "ref";
939 iommus = <&smmu 0x860>;
940 snps,quirk-frame-length-adjustment = <0x20>;
941 snps,resume-hs-terminations;
947 #address-cells = <2>;
950 compatible = "xlnx,zynqmp-dwc3";
951 reg = <0x0 0xff9e0000 0x0 0x100>;
952 power-domains = <&zynqmp_firmware PD_USB_1>;
953 resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
954 <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
955 <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
956 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
959 dwc3_1: usb@fe300000 {
960 compatible = "snps,dwc3";
961 reg = <0x0 0xfe300000 0x0 0x40000>;
962 interrupt-parent = <&gic>;
963 interrupt-names = "host", "peripheral", "otg";
964 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
965 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
966 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
967 clock-names = "bus_early", "ref";
968 iommus = <&smmu 0x861>;
969 snps,quirk-frame-length-adjustment = <0x20>;
970 snps,resume-hs-terminations;
975 watchdog0: watchdog@fd4d0000 {
976 compatible = "cdns,wdt-r1p2";
978 interrupt-parent = <&gic>;
979 interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
980 reg = <0x0 0xfd4d0000 0x0 0x1000>;
985 lpd_watchdog: watchdog@ff150000 {
986 compatible = "cdns,wdt-r1p2";
988 interrupt-parent = <&gic>;
989 interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>;
990 reg = <0x0 0xff150000 0x0 0x1000>;
994 xilinx_ams: ams@ffa50000 {
995 compatible = "xlnx,zynqmp-ams";
997 interrupt-parent = <&gic>;
998 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
999 reg = <0x0 0xffa50000 0x0 0x800>;
1000 #address-cells = <1>;
1002 #io-channel-cells = <1>;
1003 ranges = <0 0 0xffa50800 0x800>;
1006 compatible = "xlnx,zynqmp-ams-ps";
1007 status = "disabled";
1011 ams_pl: ams-pl@400 {
1012 compatible = "xlnx,zynqmp-ams-pl";
1013 status = "disabled";
1014 reg = <0x400 0x400>;
1015 #address-cells = <1>;
1020 zynqmp_dpdma: dma-controller@fd4c0000 {
1021 compatible = "xlnx,zynqmp-dpdma";
1022 status = "disabled";
1023 reg = <0x0 0xfd4c0000 0x0 0x1000>;
1024 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1025 interrupt-parent = <&gic>;
1026 clock-names = "axi_clk";
1027 power-domains = <&zynqmp_firmware PD_DP>;
1031 zynqmp_dpsub: display@fd4a0000 {
1033 compatible = "xlnx,zynqmp-dpsub-1.7";
1034 status = "disabled";
1035 reg = <0x0 0xfd4a0000 0x0 0x1000>,
1036 <0x0 0xfd4aa000 0x0 0x1000>,
1037 <0x0 0xfd4ab000 0x0 0x1000>,
1038 <0x0 0xfd4ac000 0x0 0x1000>;
1039 reg-names = "dp", "blend", "av_buf", "aud";
1040 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1041 interrupt-parent = <&gic>;
1042 clock-names = "dp_apb_clk", "dp_aud_clk",
1043 "dp_vtc_pixel_clk_in";
1044 power-domains = <&zynqmp_firmware PD_DP>;
1045 resets = <&zynqmp_reset ZYNQMP_RESET_DP>;
1046 dma-names = "vid0", "vid1", "vid2", "gfx0";
1047 dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,
1048 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,
1049 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,
1050 <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;
1053 #address-cells = <1>;