1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU111
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
8 * Michal Simek <michal.simek@amd.com>
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
21 model = "ZynqMP ZCU111 RevA";
22 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
38 bootargs = "earlycon";
39 stdout-path = "serial0:115200n8";
43 device_type = "memory";
44 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
45 /* Another 4GB connected to PL */
49 compatible = "gpio-keys";
53 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
54 linux,code = <KEY_DOWN>;
61 compatible = "gpio-leds";
64 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
65 linux,default-trigger = "heartbeat";
70 compatible = "iio-hwmon";
71 io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;
74 compatible = "iio-hwmon";
75 io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;
78 compatible = "iio-hwmon";
79 io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;
82 compatible = "iio-hwmon";
83 io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;
86 compatible = "iio-hwmon";
87 io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;
90 compatible = "iio-hwmon";
91 io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;
94 compatible = "iio-hwmon";
95 io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;
98 compatible = "iio-hwmon";
99 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
102 compatible = "iio-hwmon";
103 io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;
106 compatible = "iio-hwmon";
107 io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;
110 compatible = "iio-hwmon";
111 io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;
114 compatible = "iio-hwmon";
115 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
118 compatible = "iio-hwmon";
119 io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;
122 compatible = "iio-hwmon";
123 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
126 /* 48MHz reference crystal */
128 compatible = "fixed-clock";
130 clock-frequency = <48000000>;
172 phy-handle = <&phy0>;
173 phy-mode = "rgmii-id";
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_gem3_default>;
177 #address-cells = <1>;
179 phy0: ethernet-phy@c {
181 compatible = "ethernet-phy-id2000.a231";
183 ti,rx-internal-delay = <0x8>;
184 ti,tx-internal-delay = <0xa>;
185 ti,fifo-depth = <0x1>;
186 ti,dp83867-rxctrl-strap-quirk;
187 reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>;
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_gpio_default>;
204 clock-frequency = <400000>;
205 pinctrl-names = "default", "gpio";
206 pinctrl-0 = <&pinctrl_i2c0_default>;
207 pinctrl-1 = <&pinctrl_i2c0_gpio>;
208 scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
209 sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
211 tca6416_u22: gpio@20 {
212 compatible = "ti,tca6416";
214 gpio-controller; /* interrupt not connected */
220 * 1 - MAX6643_FANFAIL_B
221 * 2 - MIO26_PMU_INPUT_LS
222 * 4 - SFP_SI5382_INT_ALM
223 * 5 - IIC_MUX_RESET_B
224 * 6 - GEM3_EXP_RESET_B
225 * 10 - FMCP_HSPC_PRSNT_M2C_B
226 * 11 - CLK_SPI_MUX_SEL0
227 * 12 - CLK_SPI_MUX_SEL1
228 * 16 - IRPS5401_ALERT_B
229 * 17 - INA226_PMBUS_ALERT
230 * 3, 7, 13-15 - not connected
234 i2c-mux@75 { /* u23 */
235 compatible = "nxp,pca9544";
236 #address-cells = <1>;
240 #address-cells = <1>;
244 /* PMBUS_ALERT done via pca9544 */
245 u67: ina226@40 { /* u67 */
246 compatible = "ti,ina226";
247 #io-channel-cells = <1>;
248 label = "ina226-u67";
250 shunt-resistor = <2000>;
252 u59: ina226@41 { /* u59 */
253 compatible = "ti,ina226";
254 #io-channel-cells = <1>;
255 label = "ina226-u59";
257 shunt-resistor = <5000>;
259 u61: ina226@42 { /* u61 */
260 compatible = "ti,ina226";
261 #io-channel-cells = <1>;
262 label = "ina226-u61";
264 shunt-resistor = <5000>;
266 u60: ina226@43 { /* u60 */
267 compatible = "ti,ina226";
268 #io-channel-cells = <1>;
269 label = "ina226-u60";
271 shunt-resistor = <5000>;
273 u64: ina226@45 { /* u64 */
274 compatible = "ti,ina226";
275 #io-channel-cells = <1>;
276 label = "ina226-u64";
278 shunt-resistor = <5000>;
280 u69: ina226@46 { /* u69 */
281 compatible = "ti,ina226";
282 #io-channel-cells = <1>;
283 label = "ina226-u69";
285 shunt-resistor = <2000>;
287 u66: ina226@47 { /* u66 */
288 compatible = "ti,ina226";
289 #io-channel-cells = <1>;
290 label = "ina226-u66";
292 shunt-resistor = <5000>;
294 u65: ina226@48 { /* u65 */
295 compatible = "ti,ina226";
296 #io-channel-cells = <1>;
297 label = "ina226-u65";
299 shunt-resistor = <5000>;
301 u63: ina226@49 { /* u63 */
302 compatible = "ti,ina226";
303 #io-channel-cells = <1>;
304 label = "ina226-u63";
306 shunt-resistor = <5000>;
308 u3: ina226@4a { /* u3 */
309 compatible = "ti,ina226";
310 #io-channel-cells = <1>;
313 shunt-resistor = <5000>;
315 u71: ina226@4b { /* u71 */
316 compatible = "ti,ina226";
317 #io-channel-cells = <1>;
318 label = "ina226-u71";
320 shunt-resistor = <5000>;
322 u77: ina226@4c { /* u77 */
323 compatible = "ti,ina226";
324 #io-channel-cells = <1>;
325 label = "ina226-u77";
327 shunt-resistor = <5000>;
329 u73: ina226@4d { /* u73 */
330 compatible = "ti,ina226";
331 #io-channel-cells = <1>;
332 label = "ina226-u73";
334 shunt-resistor = <5000>;
336 u79: ina226@4e { /* u79 */
337 compatible = "ti,ina226";
338 #io-channel-cells = <1>;
339 label = "ina226-u79";
341 shunt-resistor = <5000>;
345 #address-cells = <1>;
351 #address-cells = <1>;
354 irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */
355 compatible = "infineon,irps5401";
358 irps5401_44: irps5401@44 { /* IRPS5401 - u55 */
359 compatible = "infineon,irps5401";
362 irps5401_45: irps5401@45 { /* IRPS5401 - u57 */
363 compatible = "infineon,irps5401";
374 #address-cells = <1>;
384 clock-frequency = <400000>;
385 pinctrl-names = "default", "gpio";
386 pinctrl-0 = <&pinctrl_i2c1_default>;
387 pinctrl-1 = <&pinctrl_i2c1_gpio>;
388 scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
389 sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
391 i2c-mux@74 { /* u26 */
392 compatible = "nxp,pca9548";
393 #address-cells = <1>;
397 #address-cells = <1>;
401 * IIC_EEPROM 1kB memory which uses 256B blocks
402 * where every block has different address.
403 * 0 - 256B address 0x54
404 * 256B - 512B address 0x55
405 * 512B - 768B address 0x56
406 * 768B - 1024B address 0x57
408 eeprom: eeprom@54 { /* u88 */
409 compatible = "atmel,24c08";
414 #address-cells = <1>;
417 si5341: clock-generator@36 { /* SI5341 - u46 */
418 compatible = "silabs,si5341";
421 #address-cells = <1>;
424 clock-names = "xtal";
425 clock-output-names = "si5341";
428 /* refclk0 for PS-GT, used for DP */
433 /* refclk2 for PS-GT, used for USB3 */
438 /* refclk3 for PS-GT, used for SATA */
443 /* refclk5 PL CLK100 */
448 /* refclk6 PL CLK125 */
453 /* refclk9 used for PS_REF_CLK 33.3 MHz */
460 #address-cells = <1>;
463 si570_1: clock-generator@5d { /* USER SI570 - u47 */
465 compatible = "silabs,si570";
467 temperature-stability = <50>;
468 factory-fout = <300000000>;
469 clock-frequency = <300000000>;
470 clock-output-names = "si570_user";
474 #address-cells = <1>;
477 si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */
479 compatible = "silabs,si570";
481 temperature-stability = <50>;
482 factory-fout = <156250000>;
483 clock-frequency = <156250000>;
484 clock-output-names = "si570_mgt";
488 #address-cells = <1>;
494 #address-cells = <1>;
497 sc18is603@2f { /* sc18is602 - u93 */
498 compatible = "nxp,sc18is603";
500 /* 4 gpios for CS not handled by driver */
511 #address-cells = <1>;
520 compatible = "nxp,pca9548"; /* u27 */
521 #address-cells = <1>;
526 #address-cells = <1>;
532 #address-cells = <1>;
538 #address-cells = <1>;
544 #address-cells = <1>;
550 #address-cells = <1>;
556 #address-cells = <1>;
562 #address-cells = <1>;
568 #address-cells = <1>;
578 pinctrl_i2c0_default: i2c0-default {
580 groups = "i2c0_3_grp";
585 groups = "i2c0_3_grp";
587 slew-rate = <SLEW_RATE_SLOW>;
588 power-source = <IO_STANDARD_LVCMOS18>;
592 pinctrl_i2c0_gpio: i2c0-gpio {
594 groups = "gpio0_14_grp", "gpio0_15_grp";
599 groups = "gpio0_14_grp", "gpio0_15_grp";
600 slew-rate = <SLEW_RATE_SLOW>;
601 power-source = <IO_STANDARD_LVCMOS18>;
605 pinctrl_i2c1_default: i2c1-default {
607 groups = "i2c1_4_grp";
612 groups = "i2c1_4_grp";
614 slew-rate = <SLEW_RATE_SLOW>;
615 power-source = <IO_STANDARD_LVCMOS18>;
619 pinctrl_i2c1_gpio: i2c1-gpio {
621 groups = "gpio0_16_grp", "gpio0_17_grp";
626 groups = "gpio0_16_grp", "gpio0_17_grp";
627 slew-rate = <SLEW_RATE_SLOW>;
628 power-source = <IO_STANDARD_LVCMOS18>;
632 pinctrl_uart0_default: uart0-default {
634 groups = "uart0_4_grp";
639 groups = "uart0_4_grp";
640 slew-rate = <SLEW_RATE_SLOW>;
641 power-source = <IO_STANDARD_LVCMOS18>;
655 pinctrl_usb0_default: usb0-default {
657 groups = "usb0_0_grp";
662 groups = "usb0_0_grp";
663 power-source = <IO_STANDARD_LVCMOS18>;
667 pins = "MIO52", "MIO53", "MIO55";
669 drive-strength = <12>;
670 slew-rate = <SLEW_RATE_FAST>;
674 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
675 "MIO60", "MIO61", "MIO62", "MIO63";
677 drive-strength = <4>;
678 slew-rate = <SLEW_RATE_SLOW>;
682 pinctrl_gem3_default: gem3-default {
684 function = "ethernet3";
685 groups = "ethernet3_0_grp";
689 groups = "ethernet3_0_grp";
690 slew-rate = <SLEW_RATE_SLOW>;
691 power-source = <IO_STANDARD_LVCMOS18>;
695 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
702 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
710 groups = "mdio3_0_grp";
714 groups = "mdio3_0_grp";
715 slew-rate = <SLEW_RATE_SLOW>;
716 power-source = <IO_STANDARD_LVCMOS18>;
721 pinctrl_sdhci1_default: sdhci1-default {
723 groups = "sdio1_0_grp";
728 groups = "sdio1_0_grp";
729 slew-rate = <SLEW_RATE_SLOW>;
730 power-source = <IO_STANDARD_LVCMOS18>;
735 groups = "sdio1_cd_0_grp";
736 function = "sdio1_cd";
740 groups = "sdio1_cd_0_grp";
743 slew-rate = <SLEW_RATE_SLOW>;
744 power-source = <IO_STANDARD_LVCMOS18>;
748 pinctrl_gpio_default: gpio-default {
751 groups = "gpio0_22_grp", "gpio0_23_grp";
755 groups = "gpio0_22_grp", "gpio0_23_grp";
756 slew-rate = <SLEW_RATE_SLOW>;
757 power-source = <IO_STANDARD_LVCMOS18>;
762 groups = "gpio0_13_grp", "gpio0_38_grp";
766 groups = "gpio0_13_grp", "gpio0_38_grp";
767 slew-rate = <SLEW_RATE_SLOW>;
768 power-source = <IO_STANDARD_LVCMOS18>;
777 pins = "MIO13", "MIO23", "MIO38";
785 /* nc, dp, usb3, sata */
786 clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>;
787 clock-names = "ref1", "ref2", "ref3";
793 compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
794 #address-cells = <1>;
797 spi-tx-bus-width = <4>;
798 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
799 spi-max-frequency = <108000000>; /* Based on DC1 spec */
809 /* SATA OOB timing settings */
810 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
811 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
812 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
813 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
814 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
815 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
816 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
817 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
818 phy-names = "sata-phy";
819 phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
822 /* SD1 with level shifter */
825 pinctrl-names = "default";
826 pinctrl-0 = <&pinctrl_sdhci1_default>;
829 * This property should be removed for supporting UHS mode
837 pinctrl-names = "default";
838 pinctrl-0 = <&pinctrl_uart0_default>;
841 /* ULPI SMSC USB3320 */
844 pinctrl-names = "default";
845 pinctrl-0 = <&pinctrl_usb0_default>;
846 phy-names = "usb3-phy";
847 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
853 snps,usb3_lpm_capable;
854 maximum-speed = "super-speed";
863 phy-names = "dp-phy0", "dp-phy1";
864 phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
865 <&psgtr 0 PHY_TYPE_DP 1 1>;