1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU106
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
8 * Michal Simek <michal.simek@amd.com>
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
21 model = "ZynqMP ZCU106 RevA";
22 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
39 bootargs = "earlycon";
40 stdout-path = "serial0:115200n8";
44 device_type = "memory";
45 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
49 compatible = "gpio-keys";
53 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
54 linux,code = <KEY_DOWN>;
61 compatible = "gpio-leds";
64 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
65 linux,default-trigger = "heartbeat";
70 compatible = "iio-hwmon";
71 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
74 compatible = "iio-hwmon";
75 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
78 compatible = "iio-hwmon";
79 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
82 compatible = "iio-hwmon";
83 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
86 compatible = "iio-hwmon";
87 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
90 compatible = "iio-hwmon";
91 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
94 compatible = "iio-hwmon";
95 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
98 compatible = "iio-hwmon";
99 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
102 compatible = "iio-hwmon";
103 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
106 compatible = "iio-hwmon";
107 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
110 compatible = "iio-hwmon";
111 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
114 compatible = "iio-hwmon";
115 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
118 compatible = "iio-hwmon";
119 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
122 compatible = "iio-hwmon";
123 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
126 compatible = "iio-hwmon";
127 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
130 compatible = "iio-hwmon";
131 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
134 compatible = "iio-hwmon";
135 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
138 compatible = "iio-hwmon";
139 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
142 /* 48MHz reference crystal */
144 compatible = "fixed-clock";
146 clock-frequency = <48000000>;
150 compatible = "fixed-clock";
152 clock-frequency = <114285000>;
156 compatible = "dp-connector";
162 remote-endpoint = <&dpsub_dp_out>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_can1_default>;
212 phy-handle = <&phy0>;
213 phy-mode = "rgmii-id";
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_gem3_default>;
217 #address-cells = <1>;
219 phy0: ethernet-phy@c {
222 compatible = "ethernet-phy-id2000.a231";
223 ti,rx-internal-delay = <0x8>;
224 ti,tx-internal-delay = <0xa>;
225 ti,fifo-depth = <0x1>;
226 ti,dp83867-rxctrl-strap-quirk;
227 reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_gpio_default>;
244 clock-frequency = <400000>;
245 pinctrl-names = "default", "gpio";
246 pinctrl-0 = <&pinctrl_i2c0_default>;
247 pinctrl-1 = <&pinctrl_i2c0_gpio>;
248 scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
249 sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
251 tca6416_u97: gpio@20 {
252 compatible = "ti,tca6416";
254 gpio-controller; /* interrupt not connected */
259 * 0 - SFP_SI5328_INT_ALM
260 * 1 - HDMI_SI5328_INT_ALM
261 * 5 - IIC_MUX_RESET_B
262 * 6 - GEM3_EXP_RESET_B
263 * 10 - FMC_HPC0_PRSNT_M2C_B
264 * 11 - FMC_HPC1_PRSNT_M2C_B
265 * 2-4, 7, 12-17 - not connected
269 tca6416_u61: gpio@21 {
270 compatible = "ti,tca6416";
281 * 4 - MIO26_PMU_INPUT_LS
284 * 7 - MAXIM_PMBUS_ALERT
285 * 10 - PL_DDR4_VTERM_EN
286 * 11 - PL_DDR4_VPP_2V5_EN
287 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
288 * 13 - PS_DIMM_SUSPEND_EN
289 * 14 - PS_DDR4_VTERM_EN
290 * 15 - PS_DDR4_VPP_2V5_EN
291 * 16 - 17 - not connected
295 i2c-mux@75 { /* u60 */
296 compatible = "nxp,pca9544";
297 #address-cells = <1>;
301 #address-cells = <1>;
305 u76: ina226@40 { /* u76 */
306 compatible = "ti,ina226";
307 #io-channel-cells = <1>;
308 label = "ina226-u76";
310 shunt-resistor = <5000>;
312 u77: ina226@41 { /* u77 */
313 compatible = "ti,ina226";
314 #io-channel-cells = <1>;
315 label = "ina226-u77";
317 shunt-resistor = <5000>;
319 u78: ina226@42 { /* u78 */
320 compatible = "ti,ina226";
321 #io-channel-cells = <1>;
322 label = "ina226-u78";
324 shunt-resistor = <5000>;
326 u87: ina226@43 { /* u87 */
327 compatible = "ti,ina226";
328 #io-channel-cells = <1>;
329 label = "ina226-u87";
331 shunt-resistor = <5000>;
333 u85: ina226@44 { /* u85 */
334 compatible = "ti,ina226";
335 #io-channel-cells = <1>;
336 label = "ina226-u85";
338 shunt-resistor = <5000>;
340 u86: ina226@45 { /* u86 */
341 compatible = "ti,ina226";
342 #io-channel-cells = <1>;
343 label = "ina226-u86";
345 shunt-resistor = <5000>;
347 u93: ina226@46 { /* u93 */
348 compatible = "ti,ina226";
349 #io-channel-cells = <1>;
350 label = "ina226-u93";
352 shunt-resistor = <5000>;
354 u88: ina226@47 { /* u88 */
355 compatible = "ti,ina226";
356 #io-channel-cells = <1>;
357 label = "ina226-u88";
359 shunt-resistor = <5000>;
361 u15: ina226@4a { /* u15 */
362 compatible = "ti,ina226";
363 #io-channel-cells = <1>;
364 label = "ina226-u15";
366 shunt-resistor = <5000>;
368 u92: ina226@4b { /* u92 */
369 compatible = "ti,ina226";
370 #io-channel-cells = <1>;
371 label = "ina226-u92";
373 shunt-resistor = <5000>;
377 #address-cells = <1>;
381 u79: ina226@40 { /* u79 */
382 compatible = "ti,ina226";
383 #io-channel-cells = <1>;
384 label = "ina226-u79";
386 shunt-resistor = <2000>;
388 u81: ina226@41 { /* u81 */
389 compatible = "ti,ina226";
390 #io-channel-cells = <1>;
391 label = "ina226-u81";
393 shunt-resistor = <5000>;
395 u80: ina226@42 { /* u80 */
396 compatible = "ti,ina226";
397 #io-channel-cells = <1>;
398 label = "ina226-u80";
400 shunt-resistor = <5000>;
402 u84: ina226@43 { /* u84 */
403 compatible = "ti,ina226";
404 #io-channel-cells = <1>;
405 label = "ina226-u84";
407 shunt-resistor = <5000>;
409 u16: ina226@44 { /* u16 */
410 compatible = "ti,ina226";
411 #io-channel-cells = <1>;
412 label = "ina226-u16";
414 shunt-resistor = <5000>;
416 u65: ina226@45 { /* u65 */
417 compatible = "ti,ina226";
418 #io-channel-cells = <1>;
419 label = "ina226-u65";
421 shunt-resistor = <5000>;
423 u74: ina226@46 { /* u74 */
424 compatible = "ti,ina226";
425 #io-channel-cells = <1>;
426 label = "ina226-u74";
428 shunt-resistor = <5000>;
430 u75: ina226@47 { /* u75 */
431 compatible = "ti,ina226";
432 #io-channel-cells = <1>;
433 label = "ina226-u75";
435 shunt-resistor = <5000>;
439 #address-cells = <1>;
442 /* MAXIM_PMBUS - 00 */
443 max15301@a { /* u46 */
444 compatible = "maxim,max15301";
447 max15303@b { /* u4 */
448 compatible = "maxim,max15303";
451 max15303@10 { /* u13 */
452 compatible = "maxim,max15303";
455 max15301@13 { /* u47 */
456 compatible = "maxim,max15301";
459 max15303@14 { /* u7 */
460 compatible = "maxim,max15303";
463 max15303@15 { /* u6 */
464 compatible = "maxim,max15303";
467 max15303@16 { /* u10 */
468 compatible = "maxim,max15303";
471 max15303@17 { /* u9 */
472 compatible = "maxim,max15303";
475 max15301@18 { /* u63 */
476 compatible = "maxim,max15301";
479 max15303@1a { /* u49 */
480 compatible = "maxim,max15303";
483 max15303@1b { /* u8 */
484 compatible = "maxim,max15303";
487 max15303@1d { /* u18 */
488 compatible = "maxim,max15303";
492 max20751@72 { /* u95 */
493 compatible = "maxim,max20751";
496 max20751@73 { /* u96 */
497 compatible = "maxim,max20751";
501 /* Bus 3 is not connected */
507 clock-frequency = <400000>;
508 pinctrl-names = "default", "gpio";
509 pinctrl-0 = <&pinctrl_i2c1_default>;
510 pinctrl-1 = <&pinctrl_i2c1_gpio>;
511 scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
512 sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
514 /* PL i2c via PCA9306 - u45 */
515 i2c-mux@74 { /* u34 */
516 compatible = "nxp,pca9548";
517 #address-cells = <1>;
521 #address-cells = <1>;
525 * IIC_EEPROM 1kB memory which uses 256B blocks
526 * where every block has different address.
527 * 0 - 256B address 0x54
528 * 256B - 512B address 0x55
529 * 512B - 768B address 0x56
530 * 768B - 1024B address 0x57
532 eeprom: eeprom@54 { /* u23 */
533 compatible = "atmel,24c08";
538 #address-cells = <1>;
541 si5341: clock-generator@36 { /* SI5341 - u69 */
542 compatible = "silabs,si5341";
545 #address-cells = <1>;
548 clock-names = "xtal";
549 clock-output-names = "si5341";
552 /* refclk0 for PS-GT, used for DP */
557 /* refclk2 for PS-GT, used for USB3 */
562 /* refclk3 for PS-GT, used for SATA */
567 /* refclk6 PL CLK125 */
572 /* refclk7 PL CLK74 */
577 /* refclk9 used for PS_REF_CLK 33.3 MHz */
585 #address-cells = <1>;
588 si570_1: clock-generator@5d { /* USER SI570 - u42 */
590 compatible = "silabs,si570";
592 temperature-stability = <50>;
593 factory-fout = <300000000>;
594 clock-frequency = <300000000>;
595 clock-output-names = "si570_user";
599 #address-cells = <1>;
602 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
604 compatible = "silabs,si570";
606 temperature-stability = <50>; /* copy from zc702 */
607 factory-fout = <156250000>;
608 clock-frequency = <148500000>;
609 clock-output-names = "si570_mgt";
613 #address-cells = <1>;
619 #address-cells = <1>;
621 reg = <5>; /* FAN controller */
622 temp@4c {/* lm96163 - u128 */
623 compatible = "national,lm96163";
627 /* 6 - 7 unconnected */
631 compatible = "nxp,pca9548"; /* u135 */
632 #address-cells = <1>;
637 #address-cells = <1>;
643 #address-cells = <1>;
649 #address-cells = <1>;
655 #address-cells = <1>;
661 #address-cells = <1>;
667 #address-cells = <1>;
673 #address-cells = <1>;
679 #address-cells = <1>;
689 pinctrl_i2c0_default: i2c0-default {
691 groups = "i2c0_3_grp";
696 groups = "i2c0_3_grp";
698 slew-rate = <SLEW_RATE_SLOW>;
699 power-source = <IO_STANDARD_LVCMOS18>;
703 pinctrl_i2c0_gpio: i2c0-gpio {
705 groups = "gpio0_14_grp", "gpio0_15_grp";
710 groups = "gpio0_14_grp", "gpio0_15_grp";
711 slew-rate = <SLEW_RATE_SLOW>;
712 power-source = <IO_STANDARD_LVCMOS18>;
716 pinctrl_i2c1_default: i2c1-default {
718 groups = "i2c1_4_grp";
723 groups = "i2c1_4_grp";
725 slew-rate = <SLEW_RATE_SLOW>;
726 power-source = <IO_STANDARD_LVCMOS18>;
730 pinctrl_i2c1_gpio: i2c1-gpio {
732 groups = "gpio0_16_grp", "gpio0_17_grp";
737 groups = "gpio0_16_grp", "gpio0_17_grp";
738 slew-rate = <SLEW_RATE_SLOW>;
739 power-source = <IO_STANDARD_LVCMOS18>;
743 pinctrl_uart0_default: uart0-default {
745 groups = "uart0_4_grp";
750 groups = "uart0_4_grp";
751 slew-rate = <SLEW_RATE_SLOW>;
752 power-source = <IO_STANDARD_LVCMOS18>;
766 pinctrl_uart1_default: uart1-default {
768 groups = "uart1_5_grp";
773 groups = "uart1_5_grp";
774 slew-rate = <SLEW_RATE_SLOW>;
775 power-source = <IO_STANDARD_LVCMOS18>;
789 pinctrl_usb0_default: usb0-default {
791 groups = "usb0_0_grp";
796 groups = "usb0_0_grp";
797 power-source = <IO_STANDARD_LVCMOS18>;
801 pins = "MIO52", "MIO53", "MIO55";
803 drive-strength = <12>;
804 slew-rate = <SLEW_RATE_FAST>;
808 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
809 "MIO60", "MIO61", "MIO62", "MIO63";
811 drive-strength = <4>;
812 slew-rate = <SLEW_RATE_SLOW>;
816 pinctrl_gem3_default: gem3-default {
818 function = "ethernet3";
819 groups = "ethernet3_0_grp";
823 groups = "ethernet3_0_grp";
824 slew-rate = <SLEW_RATE_SLOW>;
825 power-source = <IO_STANDARD_LVCMOS18>;
829 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
836 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
844 groups = "mdio3_0_grp";
848 groups = "mdio3_0_grp";
849 slew-rate = <SLEW_RATE_SLOW>;
850 power-source = <IO_STANDARD_LVCMOS18>;
855 pinctrl_can1_default: can1-default {
858 groups = "can1_6_grp";
862 groups = "can1_6_grp";
863 slew-rate = <SLEW_RATE_SLOW>;
864 power-source = <IO_STANDARD_LVCMOS18>;
878 pinctrl_sdhci1_default: sdhci1-default {
880 groups = "sdio1_0_grp";
885 groups = "sdio1_0_grp";
886 slew-rate = <SLEW_RATE_SLOW>;
887 power-source = <IO_STANDARD_LVCMOS18>;
892 groups = "sdio1_cd_0_grp";
893 function = "sdio1_cd";
897 groups = "sdio1_cd_0_grp";
900 slew-rate = <SLEW_RATE_SLOW>;
901 power-source = <IO_STANDARD_LVCMOS18>;
905 groups = "sdio1_wp_0_grp";
906 function = "sdio1_wp";
910 groups = "sdio1_wp_0_grp";
913 slew-rate = <SLEW_RATE_SLOW>;
914 power-source = <IO_STANDARD_LVCMOS18>;
918 pinctrl_gpio_default: gpio-default {
921 groups = "gpio0_22_grp", "gpio0_23_grp";
925 groups = "gpio0_22_grp", "gpio0_23_grp";
926 slew-rate = <SLEW_RATE_SLOW>;
927 power-source = <IO_STANDARD_LVCMOS18>;
932 groups = "gpio0_13_grp", "gpio0_38_grp";
936 groups = "gpio0_13_grp", "gpio0_38_grp";
937 slew-rate = <SLEW_RATE_SLOW>;
938 power-source = <IO_STANDARD_LVCMOS18>;
947 pins = "MIO13", "MIO23", "MIO38";
955 /* nc, sata, usb3, dp */
956 clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
957 clock-names = "ref1", "ref2", "ref3";
963 compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
964 #address-cells = <1>;
967 spi-tx-bus-width = <4>;
968 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
969 spi-max-frequency = <108000000>; /* Based on DC1 spec */
979 /* SATA OOB timing settings */
980 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
981 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
982 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
983 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
984 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
985 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
986 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
987 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
988 phy-names = "sata-phy";
989 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
992 /* SD1 with level shifter */
996 * This property should be removed for supporting UHS mode
999 pinctrl-names = "default";
1000 pinctrl-0 = <&pinctrl_sdhci1_default>;
1001 xlnx,mio-bank = <1>;
1006 pinctrl-names = "default";
1007 pinctrl-0 = <&pinctrl_uart0_default>;
1012 pinctrl-names = "default";
1013 pinctrl-0 = <&pinctrl_uart1_default>;
1016 /* ULPI SMSC USB3320 */
1019 pinctrl-names = "default";
1020 pinctrl-0 = <&pinctrl_usb0_default>;
1021 phy-names = "usb3-phy";
1022 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
1028 snps,usb3_lpm_capable;
1029 maximum-speed = "super-speed";
1042 phy-names = "dp-phy0", "dp-phy1";
1043 phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
1044 <&psgtr 0 PHY_TYPE_DP 1 3>;
1048 dpsub_dp_out: endpoint {
1049 remote-endpoint = <&dpcon_in>;