1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Xilinx ZynqMP ZCU104
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
8 * Michal Simek <michal.simek@amd.com>
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
20 model = "ZynqMP ZCU104 RevC";
21 compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
42 device_type = "memory";
43 reg = <0x0 0x0 0x0 0x80000000>;
47 compatible = "iio-hwmon";
48 io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
51 clock_8t49n287_5: clk125 {
52 compatible = "fixed-clock";
54 clock-frequency = <125000000>;
57 clock_8t49n287_2: clk26 {
58 compatible = "fixed-clock";
60 clock-frequency = <26000000>;
63 clock_8t49n287_3: clk27 {
64 compatible = "fixed-clock";
66 clock-frequency = <27000000>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_can1_default>;
114 phy-handle = <&phy0>;
115 phy-mode = "rgmii-id";
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_gem3_default>;
119 #address-cells = <1>;
121 phy0: ethernet-phy@c {
123 compatible = "ethernet-phy-id2000.a231";
125 ti,rx-internal-delay = <0x8>;
126 ti,tx-internal-delay = <0xa>;
127 ti,fifo-depth = <0x1>;
128 ti,dp83867-rxctrl-strap-quirk;
129 reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
144 clock-frequency = <400000>;
145 pinctrl-names = "default", "gpio";
146 pinctrl-0 = <&pinctrl_i2c1_default>;
147 pinctrl-1 = <&pinctrl_i2c1_gpio>;
148 scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
149 sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
151 tca6416_u97: gpio@20 {
152 compatible = "ti,tca6416";
159 * 0 - IRPS5401_ALERT_B
160 * 1 - HDMI_8T49N241_INT_ALM
162 * 3 - MAX6643_FANFAIL_B
163 * 5 - IIC_MUX_RESET_B
164 * 6 - GEM3_EXP_RESET_B
165 * 7 - FMC_LPC_PRSNT_M2C_B
166 * 4, 10 - 17 - not connected
170 /* Another connection to this bus via PL i2c via PCA9306 - u45 */
171 i2c-mux@74 { /* u34 */
172 compatible = "nxp,pca9548";
173 #address-cells = <1>;
177 #address-cells = <1>;
181 * IIC_EEPROM 1kB memory which uses 256B blocks
182 * where every block has different address.
183 * 0 - 256B address 0x54
184 * 256B - 512B address 0x55
185 * 512B - 768B address 0x56
186 * 768B - 1024B address 0x57
188 eeprom: eeprom@54 { /* u23 */
189 compatible = "atmel,24c08";
191 #address-cells = <1>;
197 #address-cells = <1>;
200 /* 8T49N287 - u182 */
204 #address-cells = <1>;
207 irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
208 compatible = "infineon,irps5401";
209 reg = <0x43>; /* pmbus / i2c 0x13 */
211 irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
212 compatible = "infineon,irps5401";
213 reg = <0x44>; /* pmbus / i2c 0x14 */
218 #address-cells = <1>;
221 u183: ina226@40 { /* u183 */
222 compatible = "ti,ina226";
223 #io-channel-cells = <1>;
225 shunt-resistor = <5000>;
230 #address-cells = <1>;
236 #address-cells = <1>;
241 /* 4, 6 not connected */
248 pinctrl_can1_default: can1-default {
251 groups = "can1_6_grp";
255 groups = "can1_6_grp";
256 slew-rate = <SLEW_RATE_SLOW>;
257 power-source = <IO_STANDARD_LVCMOS18>;
258 drive-strength = <12>;
272 pinctrl_i2c1_default: i2c1-default {
274 groups = "i2c1_4_grp";
279 groups = "i2c1_4_grp";
281 slew-rate = <SLEW_RATE_SLOW>;
282 power-source = <IO_STANDARD_LVCMOS18>;
283 drive-strength = <12>;
287 pinctrl_i2c1_gpio: i2c1-gpio {
289 groups = "gpio0_16_grp", "gpio0_17_grp";
294 groups = "gpio0_16_grp", "gpio0_17_grp";
295 slew-rate = <SLEW_RATE_SLOW>;
296 power-source = <IO_STANDARD_LVCMOS18>;
297 drive-strength = <12>;
301 pinctrl_gem3_default: gem3-default {
303 function = "ethernet3";
304 groups = "ethernet3_0_grp";
308 groups = "ethernet3_0_grp";
309 slew-rate = <SLEW_RATE_SLOW>;
310 power-source = <IO_STANDARD_LVCMOS18>;
311 drive-strength = <12>;
315 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
322 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
330 groups = "mdio3_0_grp";
334 groups = "mdio3_0_grp";
335 slew-rate = <SLEW_RATE_SLOW>;
336 power-source = <IO_STANDARD_LVCMOS18>;
341 pinctrl_sdhci1_default: sdhci1-default {
343 groups = "sdio1_0_grp";
348 groups = "sdio1_0_grp";
349 slew-rate = <SLEW_RATE_SLOW>;
350 power-source = <IO_STANDARD_LVCMOS18>;
352 drive-strength = <12>;
356 groups = "sdio1_cd_0_grp";
357 function = "sdio1_cd";
361 groups = "sdio1_cd_0_grp";
364 slew-rate = <SLEW_RATE_SLOW>;
365 power-source = <IO_STANDARD_LVCMOS18>;
369 pinctrl_uart0_default: uart0-default {
371 groups = "uart0_4_grp";
376 groups = "uart0_4_grp";
377 slew-rate = <SLEW_RATE_SLOW>;
378 power-source = <IO_STANDARD_LVCMOS18>;
379 drive-strength = <12>;
393 pinctrl_uart1_default: uart1-default {
395 groups = "uart1_5_grp";
400 groups = "uart1_5_grp";
401 slew-rate = <SLEW_RATE_SLOW>;
402 power-source = <IO_STANDARD_LVCMOS18>;
403 drive-strength = <12>;
417 pinctrl_usb0_default: usb0-default {
419 groups = "usb0_0_grp";
424 groups = "usb0_0_grp";
425 power-source = <IO_STANDARD_LVCMOS18>;
429 pins = "MIO52", "MIO53", "MIO55";
431 drive-strength = <12>;
432 slew-rate = <SLEW_RATE_FAST>;
436 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
437 "MIO60", "MIO61", "MIO62", "MIO63";
439 drive-strength = <4>;
440 slew-rate = <SLEW_RATE_SLOW>;
447 /* nc, sata, usb3, dp */
448 clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
449 clock-names = "ref1", "ref2", "ref3";
455 compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
456 #address-cells = <1>;
459 spi-tx-bus-width = <4>;
460 spi-rx-bus-width = <4>;
461 spi-max-frequency = <108000000>; /* Based on DC1 spec */
471 /* SATA OOB timing settings */
472 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
473 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
474 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
475 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
476 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
477 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
478 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
479 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
480 phy-names = "sata-phy";
481 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
484 /* SD1 with level shifter */
488 pinctrl-names = "default";
489 pinctrl-0 = <&pinctrl_sdhci1_default>;
496 pinctrl-names = "default";
497 pinctrl-0 = <&pinctrl_uart0_default>;
502 pinctrl-names = "default";
503 pinctrl-0 = <&pinctrl_uart1_default>;
506 /* ULPI SMSC USB3320 */
509 pinctrl-names = "default";
510 pinctrl-0 = <&pinctrl_usb0_default>;
511 phy-names = "usb3-phy";
512 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
518 snps,usb3_lpm_capable;
519 maximum-speed = "super-speed";
544 phy-names = "dp-phy0", "dp-phy1";
545 phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
546 <&psgtr 0 PHY_TYPE_DP 1 3>;