arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU104
   4  *
   5  * (C) Copyright 2017 - 2021, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  16 #include <dt-bindings/phy/phy.h>
  17
  18 / {
  19         model = "ZynqMP ZCU104 RevC";
  20         compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
  21
  22         aliases {
  23                 ethernet0 = &gem3;
  24                 i2c0 = &i2c1;
  25                 mmc0 = &sdhci1;
  26                 nvmem0 = &eeprom;
  27                 rtc0 = &rtc;
  28                 serial0 = &uart0;
  29                 serial1 = &uart1;
  30                 serial2 = &dcc;
  31                 spi0 = &qspi;
  32                 usb0 = &usb0;
  33         };
  34
  35         chosen {
  36                 bootargs = "earlycon";
  37                 stdout-path = "serial0:115200n8";
  38         };
  39
  40         memory@0 {
  41                 device_type = "memory";
  42                 reg = <0x0 0x0 0x0 0x80000000>;
  43         };
  44
  45         ina226 {
  46                 compatible = "iio-hwmon";
  47                 io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
  48         };
  49
  50         clock_8t49n287_5: clk125 {
  51                 compatible = "fixed-clock";
  52                 #clock-cells = <0>;
  53                 clock-frequency = <125000000>;
  54         };
  55
  56         clock_8t49n287_2: clk26 {
  57                 compatible = "fixed-clock";
  58                 #clock-cells = <0>;
  59                 clock-frequency = <26000000>;
  60         };
  61
  62         clock_8t49n287_3: clk27 {
  63                 compatible = "fixed-clock";
  64                 #clock-cells = <0>;
  65                 clock-frequency = <27000000>;
  66         };
  67 };
  68
  69 &can1 {
  70         status = "okay";
  71         pinctrl-names = "default";
  72         pinctrl-0 = <&pinctrl_can1_default>;
  73 };
  74
  75 &dcc {
  76         status = "okay";
  77 };
  78
  79 &fpd_dma_chan1 {
  80         status = "okay";
  81 };
  82
  83 &fpd_dma_chan2 {
  84         status = "okay";
  85 };
  86
  87 &fpd_dma_chan3 {
  88         status = "okay";
  89 };
  90
  91 &fpd_dma_chan4 {
  92         status = "okay";
  93 };
  94
  95 &fpd_dma_chan5 {
  96         status = "okay";
  97 };
  98
  99 &fpd_dma_chan6 {
 100         status = "okay";
 101 };
 102
 103 &fpd_dma_chan7 {
 104         status = "okay";
 105 };
 106
 107 &fpd_dma_chan8 {
 108         status = "okay";
 109 };
 110
 111 &gem3 {
 112         status = "okay";
 113         phy-handle = <&phy0>;
 114         phy-mode = "rgmii-id";
 115         pinctrl-names = "default";
 116         pinctrl-0 = <&pinctrl_gem3_default>;
 117         phy0: ethernet-phy@c {
 118                 reg = <0xc>;
 119                 ti,rx-internal-delay = <0x8>;
 120                 ti,tx-internal-delay = <0xa>;
 121                 ti,fifo-depth = <0x1>;
 122                 ti,dp83867-rxctrl-strap-quirk;
 123         };
 124 };
 125
 126 &gpio {
 127         status = "okay";
 128 };
 129
 130 &i2c1 {
 131         status = "okay";
 132         clock-frequency = <400000>;
 133         pinctrl-names = "default", "gpio";
 134         pinctrl-0 = <&pinctrl_i2c1_default>;
 135         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 136         scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 137         sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 138
 139         tca6416_u97: gpio@20 {
 140                 compatible = "ti,tca6416";
 141                 reg = <0x20>;
 142                 gpio-controller;
 143                 #gpio-cells = <2>;
 144                 /*
 145                  * IRQ not connected
 146                  * Lines:
 147                  * 0 - IRPS5401_ALERT_B
 148                  * 1 - HDMI_8T49N241_INT_ALM
 149                  * 2 - MAX6643_OT_B
 150                  * 3 - MAX6643_FANFAIL_B
 151                  * 5 - IIC_MUX_RESET_B
 152                  * 6 - GEM3_EXP_RESET_B
 153                  * 7 - FMC_LPC_PRSNT_M2C_B
 154                  * 4, 10 - 17 - not connected
 155                  */
 156         };
 157
 158         /* Another connection to this bus via PL i2c via PCA9306 - u45 */
 159         i2c-mux@74 { /* u34 */
 160                 compatible = "nxp,pca9548";
 161                 #address-cells = <1>;
 162                 #size-cells = <0>;
 163                 reg = <0x74>;
 164                 i2c@0 {
 165                         #address-cells = <1>;
 166                         #size-cells = <0>;
 167                         reg = <0>;
 168                         /*
 169                          * IIC_EEPROM 1kB memory which uses 256B blocks
 170                          * where every block has different address.
 171                          *    0 - 256B address 0x54
 172                          * 256B - 512B address 0x55
 173                          * 512B - 768B address 0x56
 174                          * 768B - 1024B address 0x57
 175                          */
 176                         eeprom: eeprom@54 { /* u23 */
 177                                 compatible = "atmel,24c08";
 178                                 reg = <0x54>;
 179                                 #address-cells = <1>;
 180                                 #size-cells = <1>;
 181                         };
 182                 };
 183
 184                 i2c@1 {
 185                         #address-cells = <1>;
 186                         #size-cells = <0>;
 187                         reg = <1>;
 188                         /* 8T49N287 - u182 */
 189                 };
 190
 191                 i2c@2 {
 192                         #address-cells = <1>;
 193                         #size-cells = <0>;
 194                         reg = <2>;
 195                         irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
 196                                 compatible = "infineon,irps5401";
 197                                 reg = <0x43>; /* pmbus / i2c 0x13 */
 198                         };
 199                         irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
 200                                 compatible = "infineon,irps5401";
 201                                 reg = <0x44>; /* pmbus / i2c 0x14 */
 202                         };
 203                 };
 204
 205                 i2c@3 {
 206                         #address-cells = <1>;
 207                         #size-cells = <0>;
 208                         reg = <3>;
 209                         u183: ina226@40 { /* u183 */
 210                                 compatible = "ti,ina226";
 211                                 #io-channel-cells = <1>;
 212                                 reg = <0x40>;
 213                                 shunt-resistor = <5000>;
 214                         };
 215                 };
 216
 217                 i2c@5 {
 218                         #address-cells = <1>;
 219                         #size-cells = <0>;
 220                         reg = <5>;
 221                 };
 222
 223                 i2c@7 {
 224                         #address-cells = <1>;
 225                         #size-cells = <0>;
 226                         reg = <7>;
 227                 };
 228
 229                 /* 4, 6 not connected */
 230         };
 231 };
 232
 233 &pinctrl0 {
 234         status = "okay";
 235
 236         pinctrl_can1_default: can1-default {
 237                 mux {
 238                         function = "can1";
 239                         groups = "can1_6_grp";
 240                 };
 241
 242                 conf {
 243                         groups = "can1_6_grp";
 244                         slew-rate = <SLEW_RATE_SLOW>;
 245                         power-source = <IO_STANDARD_LVCMOS18>;
 246                         drive-strength = <12>;
 247                 };
 248
 249                 conf-rx {
 250                         pins = "MIO25";
 251                         bias-high-impedance;
 252                 };
 253
 254                 conf-tx {
 255                         pins = "MIO24";
 256                         bias-disable;
 257                 };
 258         };
 259
 260         pinctrl_i2c1_default: i2c1-default {
 261                 mux {
 262                         groups = "i2c1_4_grp";
 263                         function = "i2c1";
 264                 };
 265
 266                 conf {
 267                         groups = "i2c1_4_grp";
 268                         bias-pull-up;
 269                         slew-rate = <SLEW_RATE_SLOW>;
 270                         power-source = <IO_STANDARD_LVCMOS18>;
 271                         drive-strength = <12>;
 272                 };
 273         };
 274
 275         pinctrl_i2c1_gpio: i2c1-gpio {
 276                 mux {
 277                         groups = "gpio0_16_grp", "gpio0_17_grp";
 278                         function = "gpio0";
 279                 };
 280
 281                 conf {
 282                         groups = "gpio0_16_grp", "gpio0_17_grp";
 283                         slew-rate = <SLEW_RATE_SLOW>;
 284                         power-source = <IO_STANDARD_LVCMOS18>;
 285                         drive-strength = <12>;
 286                 };
 287         };
 288
 289         pinctrl_gem3_default: gem3-default {
 290                 mux {
 291                         function = "ethernet3";
 292                         groups = "ethernet3_0_grp";
 293                 };
 294
 295                 conf {
 296                         groups = "ethernet3_0_grp";
 297                         slew-rate = <SLEW_RATE_SLOW>;
 298                         power-source = <IO_STANDARD_LVCMOS18>;
 299                         drive-strength = <12>;
 300                 };
 301
 302                 conf-rx {
 303                         pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
 304                                                                         "MIO75";
 305                         bias-high-impedance;
 306                         low-power-disable;
 307                 };
 308
 309                 conf-tx {
 310                         pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
 311                                                                         "MIO69";
 312                         bias-disable;
 313                         low-power-enable;
 314                 };
 315
 316                 mux-mdio {
 317                         function = "mdio3";
 318                         groups = "mdio3_0_grp";
 319                 };
 320
 321                 conf-mdio {
 322                         groups = "mdio3_0_grp";
 323                         slew-rate = <SLEW_RATE_SLOW>;
 324                         power-source = <IO_STANDARD_LVCMOS18>;
 325                         bias-disable;
 326                 };
 327         };
 328
 329         pinctrl_sdhci1_default: sdhci1-default {
 330                 mux {
 331                         groups = "sdio1_0_grp";
 332                         function = "sdio1";
 333                 };
 334
 335                 conf {
 336                         groups = "sdio1_0_grp";
 337                         slew-rate = <SLEW_RATE_SLOW>;
 338                         power-source = <IO_STANDARD_LVCMOS18>;
 339                         bias-disable;
 340                         drive-strength = <12>;
 341                 };
 342
 343                 mux-cd {
 344                         groups = "sdio1_cd_0_grp";
 345                         function = "sdio1_cd";
 346                 };
 347
 348                 conf-cd {
 349                         groups = "sdio1_cd_0_grp";
 350                         bias-high-impedance;
 351                         bias-pull-up;
 352                         slew-rate = <SLEW_RATE_SLOW>;
 353                         power-source = <IO_STANDARD_LVCMOS18>;
 354                 };
 355         };
 356
 357         pinctrl_uart0_default: uart0-default {
 358                 mux {
 359                         groups = "uart0_4_grp";
 360                         function = "uart0";
 361                 };
 362
 363                 conf {
 364                         groups = "uart0_4_grp";
 365                         slew-rate = <SLEW_RATE_SLOW>;
 366                         power-source = <IO_STANDARD_LVCMOS18>;
 367                         drive-strength = <12>;
 368                 };
 369
 370                 conf-rx {
 371                         pins = "MIO18";
 372                         bias-high-impedance;
 373                 };
 374
 375                 conf-tx {
 376                         pins = "MIO19";
 377                         bias-disable;
 378                 };
 379         };
 380
 381         pinctrl_uart1_default: uart1-default {
 382                 mux {
 383                         groups = "uart1_5_grp";
 384                         function = "uart1";
 385                 };
 386
 387                 conf {
 388                         groups = "uart1_5_grp";
 389                         slew-rate = <SLEW_RATE_SLOW>;
 390                         power-source = <IO_STANDARD_LVCMOS18>;
 391                         drive-strength = <12>;
 392                 };
 393
 394                 conf-rx {
 395                         pins = "MIO21";
 396                         bias-high-impedance;
 397                 };
 398
 399                 conf-tx {
 400                         pins = "MIO20";
 401                         bias-disable;
 402                 };
 403         };
 404
 405         pinctrl_usb0_default: usb0-default {
 406                 mux {
 407                         groups = "usb0_0_grp";
 408                         function = "usb0";
 409                 };
 410
 411                 conf {
 412                         groups = "usb0_0_grp";
 413                         slew-rate = <SLEW_RATE_SLOW>;
 414                         power-source = <IO_STANDARD_LVCMOS18>;
 415                         drive-strength = <12>;
 416                 };
 417
 418                 conf-rx {
 419                         pins = "MIO52", "MIO53", "MIO55";
 420                         bias-high-impedance;
 421                 };
 422
 423                 conf-tx {
 424                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 425                                "MIO60", "MIO61", "MIO62", "MIO63";
 426                         bias-disable;
 427                 };
 428         };
 429 };
 430
 431 &psgtr {
 432         status = "okay";
 433         /* nc, sata, usb3, dp */
 434         clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
 435         clock-names = "ref1", "ref2", "ref3";
 436 };
 437
 438 &qspi {
 439         status = "okay";
 440         flash@0 {
 441                 compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
 442                 #address-cells = <1>;
 443                 #size-cells = <1>;
 444                 reg = <0x0>;
 445                 spi-tx-bus-width = <1>;
 446                 spi-rx-bus-width = <4>;
 447                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 448         };
 449 };
 450
 451 &rtc {
 452         status = "okay";
 453 };
 454
 455 &sata {
 456         status = "okay";
 457         /* SATA OOB timing settings */
 458         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 459         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 460         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 461         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 462         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 463         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 464         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 465         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 466         phy-names = "sata-phy";
 467         phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
 468 };
 469
 470 /* SD1 with level shifter */
 471 &sdhci1 {
 472         status = "okay";
 473         no-1-8-v;
 474         pinctrl-names = "default";
 475         pinctrl-0 = <&pinctrl_sdhci1_default>;
 476         xlnx,mio-bank = <1>;
 477         disable-wp;
 478 };
 479
 480 &uart0 {
 481         status = "okay";
 482         pinctrl-names = "default";
 483         pinctrl-0 = <&pinctrl_uart0_default>;
 484 };
 485
 486 &uart1 {
 487         status = "okay";
 488         pinctrl-names = "default";
 489         pinctrl-0 = <&pinctrl_uart1_default>;
 490 };
 491
 492 /* ULPI SMSC USB3320 */
 493 &usb0 {
 494         status = "okay";
 495         pinctrl-names = "default";
 496         pinctrl-0 = <&pinctrl_usb0_default>;
 497         phy-names = "usb3-phy";
 498         phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
 499 };
 500
 501 &dwc3_0 {
 502         status = "okay";
 503         dr_mode = "host";
 504         snps,usb3_lpm_capable;
 505         maximum-speed = "super-speed";
 506 };
 507
 508 &watchdog0 {
 509         status = "okay";
 510 };
 511
 512 &zynqmp_dpdma {
 513         status = "okay";
 514 };
 515
 516 &zynqmp_dpsub {
 517         status = "okay";
 518         phy-names = "dp-phy0", "dp-phy1";
 519         phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
 520                <&psgtr 0 PHY_TYPE_DP 1 3>;
 521 };