1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU102 RevA
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
18 model = "ZynqMP ZCU102 RevA";
19 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
33 bootargs = "earlycon";
34 stdout-path = "serial0:115200n8";
38 device_type = "memory";
39 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
43 compatible = "gpio-keys";
47 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
48 linux,code = <KEY_DOWN>;
55 compatible = "gpio-leds";
58 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
59 linux,default-trigger = "heartbeat";
106 phy-handle = <&phy0>;
107 phy-mode = "rgmii-id";
110 ti,rx-internal-delay = <0x8>;
111 ti,tx-internal-delay = <0xa>;
112 ti,fifo-depth = <0x1>;
122 clock-frequency = <400000>;
124 tca6416_u97: gpio@20 {
125 compatible = "ti,tca6416";
132 * 0 - PS_GTR_LAN_SEL0
133 * 1 - PS_GTR_LAN_SEL1
134 * 2 - PS_GTR_LAN_SEL2
135 * 3 - PS_GTR_LAN_SEL3
136 * 4 - PCI_CLK_DIR_SEL
137 * 5 - IIC_MUX_RESET_B
138 * 6 - GEM3_EXP_RESET_B
139 * 7, 10 - 17 - not connected
145 output-low; /* PCIE = 0, DP = 1 */
151 output-high; /* PCIE = 0, DP = 1 */
157 output-high; /* PCIE = 0, USB0 = 1 */
163 output-high; /* PCIE = 0, SATA = 1 */
168 tca6416_u61: gpio@21 {
169 compatible = "ti,tca6416";
180 * 4 - MIO26_PMU_INPUT_LS
183 * 7 - MAXIM_PMBUS_ALERT
184 * 10 - PL_DDR4_VTERM_EN
185 * 11 - PL_DDR4_VPP_2V5_EN
186 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
187 * 13 - PS_DIMM_SUSPEND_EN
188 * 14 - PS_DDR4_VTERM_EN
189 * 15 - PS_DDR4_VPP_2V5_EN
190 * 16 - 17 - not connected
194 i2c-mux@75 { /* u60 */
195 compatible = "nxp,pca9544";
196 #address-cells = <1>;
200 #address-cells = <1>;
204 ina226@40 { /* u76 */
205 compatible = "ti,ina226";
207 shunt-resistor = <5000>;
209 ina226@41 { /* u77 */
210 compatible = "ti,ina226";
212 shunt-resistor = <5000>;
214 ina226@42 { /* u78 */
215 compatible = "ti,ina226";
217 shunt-resistor = <5000>;
219 ina226@43 { /* u87 */
220 compatible = "ti,ina226";
222 shunt-resistor = <5000>;
224 ina226@44 { /* u85 */
225 compatible = "ti,ina226";
227 shunt-resistor = <5000>;
229 ina226@45 { /* u86 */
230 compatible = "ti,ina226";
232 shunt-resistor = <5000>;
234 ina226@46 { /* u93 */
235 compatible = "ti,ina226";
237 shunt-resistor = <5000>;
239 ina226@47 { /* u88 */
240 compatible = "ti,ina226";
242 shunt-resistor = <5000>;
244 ina226@4a { /* u15 */
245 compatible = "ti,ina226";
247 shunt-resistor = <5000>;
249 ina226@4b { /* u92 */
250 compatible = "ti,ina226";
252 shunt-resistor = <5000>;
256 #address-cells = <1>;
260 ina226@40 { /* u79 */
261 compatible = "ti,ina226";
263 shunt-resistor = <2000>;
265 ina226@41 { /* u81 */
266 compatible = "ti,ina226";
268 shunt-resistor = <5000>;
270 ina226@42 { /* u80 */
271 compatible = "ti,ina226";
273 shunt-resistor = <5000>;
275 ina226@43 { /* u84 */
276 compatible = "ti,ina226";
278 shunt-resistor = <5000>;
280 ina226@44 { /* u16 */
281 compatible = "ti,ina226";
283 shunt-resistor = <5000>;
285 ina226@45 { /* u65 */
286 compatible = "ti,ina226";
288 shunt-resistor = <5000>;
290 ina226@46 { /* u74 */
291 compatible = "ti,ina226";
293 shunt-resistor = <5000>;
295 ina226@47 { /* u75 */
296 compatible = "ti,ina226";
298 shunt-resistor = <5000>;
302 #address-cells = <1>;
305 /* MAXIM_PMBUS - 00 */
306 max15301@a { /* u46 */
307 compatible = "maxim,max15301";
310 max15303@b { /* u4 */
311 compatible = "maxim,max15303";
314 max15303@10 { /* u13 */
315 compatible = "maxim,max15303";
318 max15301@13 { /* u47 */
319 compatible = "maxim,max15301";
322 max15303@14 { /* u7 */
323 compatible = "maxim,max15303";
326 max15303@15 { /* u6 */
327 compatible = "maxim,max15303";
330 max15303@16 { /* u10 */
331 compatible = "maxim,max15303";
334 max15303@17 { /* u9 */
335 compatible = "maxim,max15303";
338 max15301@18 { /* u63 */
339 compatible = "maxim,max15301";
342 max15303@1a { /* u49 */
343 compatible = "maxim,max15303";
346 max15303@1d { /* u18 */
347 compatible = "maxim,max15303";
350 max15303@20 { /* u8 */
351 compatible = "maxim,max15303";
352 status = "disabled"; /* unreachable */
356 max20751@72 { /* u95 */
357 compatible = "maxim,max20751";
360 max20751@73 { /* u96 */
361 compatible = "maxim,max20751";
365 /* Bus 3 is not connected */
371 clock-frequency = <400000>;
373 /* PL i2c via PCA9306 - u45 */
374 i2c-mux@74 { /* u34 */
375 compatible = "nxp,pca9548";
376 #address-cells = <1>;
380 #address-cells = <1>;
384 * IIC_EEPROM 1kB memory which uses 256B blocks
385 * where every block has different address.
386 * 0 - 256B address 0x54
387 * 256B - 512B address 0x55
388 * 512B - 768B address 0x56
389 * 768B - 1024B address 0x57
391 eeprom: eeprom@54 { /* u23 */
392 compatible = "atmel,24c08";
397 #address-cells = <1>;
400 si5341: clock-generator@36 { /* SI5341 - u69 */
406 #address-cells = <1>;
409 si570_1: clock-generator@5d { /* USER SI570 - u42 */
411 compatible = "silabs,si570";
413 temperature-stability = <50>;
414 factory-fout = <300000000>;
415 clock-frequency = <300000000>;
419 #address-cells = <1>;
422 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
424 compatible = "silabs,si570";
426 temperature-stability = <50>; /* copy from zc702 */
427 factory-fout = <156250000>;
428 clock-frequency = <148500000>;
432 #address-cells = <1>;
435 si5328: clock-generator@69 {/* SI5328 - u20 */
438 * Chip has interrupt present connected to PL
439 * interrupt-parent = <&>;
444 /* 5 - 7 unconnected */
448 compatible = "nxp,pca9548"; /* u135 */
449 #address-cells = <1>;
454 #address-cells = <1>;
460 #address-cells = <1>;
466 #address-cells = <1>;
472 #address-cells = <1>;
478 #address-cells = <1>;
484 #address-cells = <1>;
490 #address-cells = <1>;
496 #address-cells = <1>;
514 /* SATA OOB timing settings */
515 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
516 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
517 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
518 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
519 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
520 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
521 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
522 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
525 /* SD1 with level shifter */
539 /* ULPI SMSC USB3320 */