1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU102 RevA
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
8 * Michal Simek <michal.simek@amd.com>
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
21 model = "ZynqMP ZCU102 RevA";
22 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
39 bootargs = "earlycon";
40 stdout-path = "serial0:115200n8";
44 device_type = "memory";
45 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
49 compatible = "gpio-keys";
53 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
54 linux,code = <KEY_DOWN>;
61 compatible = "gpio-leds";
64 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
65 linux,default-trigger = "heartbeat";
70 compatible = "iio-hwmon";
71 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
74 compatible = "iio-hwmon";
75 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
78 compatible = "iio-hwmon";
79 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
82 compatible = "iio-hwmon";
83 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
86 compatible = "iio-hwmon";
87 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
90 compatible = "iio-hwmon";
91 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
94 compatible = "iio-hwmon";
95 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
98 compatible = "iio-hwmon";
99 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
102 compatible = "iio-hwmon";
103 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
106 compatible = "iio-hwmon";
107 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
110 compatible = "iio-hwmon";
111 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
114 compatible = "iio-hwmon";
115 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
118 compatible = "iio-hwmon";
119 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
122 compatible = "iio-hwmon";
123 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
126 compatible = "iio-hwmon";
127 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
130 compatible = "iio-hwmon";
131 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
134 compatible = "iio-hwmon";
135 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
138 compatible = "iio-hwmon";
139 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
142 /* 48MHz reference crystal */
144 compatible = "fixed-clock";
146 clock-frequency = <48000000>;
150 compatible = "fixed-clock";
152 clock-frequency = <114285000>;
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_can1_default>;
200 phy-handle = <&phy0>;
201 phy-mode = "rgmii-id";
202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_gem3_default>;
205 #address-cells = <1>;
207 phy0: ethernet-phy@21 {
209 compatible = "ethernet-phy-id2000.a231";
211 ti,rx-internal-delay = <0x8>;
212 ti,tx-internal-delay = <0xa>;
213 ti,fifo-depth = <0x1>;
214 ti,dp83867-rxctrl-strap-quirk;
215 reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_gpio_default>;
232 clock-frequency = <400000>;
233 pinctrl-names = "default", "gpio";
234 pinctrl-0 = <&pinctrl_i2c0_default>;
235 pinctrl-1 = <&pinctrl_i2c0_gpio>;
236 scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
237 sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
239 tca6416_u97: gpio@20 {
240 compatible = "ti,tca6416";
242 gpio-controller; /* IRQ not connected */
244 gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
245 "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
246 "", "", "", "", "", "", "", "", "";
250 output-low; /* PCIE = 0, DP = 1 */
256 output-high; /* PCIE = 0, DP = 1 */
262 output-high; /* PCIE = 0, USB0 = 1 */
268 output-high; /* PCIE = 0, SATA = 1 */
273 tca6416_u61: gpio@21 {
274 compatible = "ti,tca6416";
276 gpio-controller; /* IRQ not connected */
278 gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS",
279 "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN",
280 "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN",
281 "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", "";
284 i2c-mux@75 { /* u60 */
285 compatible = "nxp,pca9544";
286 #address-cells = <1>;
290 #address-cells = <1>;
294 u76: ina226@40 { /* u76 */
295 compatible = "ti,ina226";
296 #io-channel-cells = <1>;
297 label = "ina226-u76";
299 shunt-resistor = <5000>;
301 u77: ina226@41 { /* u77 */
302 compatible = "ti,ina226";
303 #io-channel-cells = <1>;
304 label = "ina226-u77";
306 shunt-resistor = <5000>;
308 u78: ina226@42 { /* u78 */
309 compatible = "ti,ina226";
310 #io-channel-cells = <1>;
311 label = "ina226-u78";
313 shunt-resistor = <5000>;
315 u87: ina226@43 { /* u87 */
316 compatible = "ti,ina226";
317 #io-channel-cells = <1>;
318 label = "ina226-u87";
320 shunt-resistor = <5000>;
322 u85: ina226@44 { /* u85 */
323 compatible = "ti,ina226";
324 #io-channel-cells = <1>;
325 label = "ina226-u85";
327 shunt-resistor = <5000>;
329 u86: ina226@45 { /* u86 */
330 compatible = "ti,ina226";
331 #io-channel-cells = <1>;
332 label = "ina226-u86";
334 shunt-resistor = <5000>;
336 u93: ina226@46 { /* u93 */
337 compatible = "ti,ina226";
338 #io-channel-cells = <1>;
339 label = "ina226-u93";
341 shunt-resistor = <5000>;
343 u88: ina226@47 { /* u88 */
344 compatible = "ti,ina226";
345 #io-channel-cells = <1>;
346 label = "ina226-u88";
348 shunt-resistor = <5000>;
350 u15: ina226@4a { /* u15 */
351 compatible = "ti,ina226";
352 #io-channel-cells = <1>;
353 label = "ina226-u15";
355 shunt-resistor = <5000>;
357 u92: ina226@4b { /* u92 */
358 compatible = "ti,ina226";
359 #io-channel-cells = <1>;
360 label = "ina226-u92";
362 shunt-resistor = <5000>;
366 #address-cells = <1>;
370 u79: ina226@40 { /* u79 */
371 compatible = "ti,ina226";
372 #io-channel-cells = <1>;
373 label = "ina226-u79";
375 shunt-resistor = <2000>;
377 u81: ina226@41 { /* u81 */
378 compatible = "ti,ina226";
379 #io-channel-cells = <1>;
380 label = "ina226-u81";
382 shunt-resistor = <5000>;
384 u80: ina226@42 { /* u80 */
385 compatible = "ti,ina226";
386 #io-channel-cells = <1>;
387 label = "ina226-u80";
389 shunt-resistor = <5000>;
391 u84: ina226@43 { /* u84 */
392 compatible = "ti,ina226";
393 #io-channel-cells = <1>;
394 label = "ina226-u84";
396 shunt-resistor = <5000>;
398 u16: ina226@44 { /* u16 */
399 compatible = "ti,ina226";
400 #io-channel-cells = <1>;
401 label = "ina226-u16";
403 shunt-resistor = <5000>;
405 u65: ina226@45 { /* u65 */
406 compatible = "ti,ina226";
407 #io-channel-cells = <1>;
408 label = "ina226-u65";
410 shunt-resistor = <5000>;
412 u74: ina226@46 { /* u74 */
413 compatible = "ti,ina226";
414 #io-channel-cells = <1>;
415 label = "ina226-u74";
417 shunt-resistor = <5000>;
419 u75: ina226@47 { /* u75 */
420 compatible = "ti,ina226";
421 #io-channel-cells = <1>;
422 label = "ina226-u75";
424 shunt-resistor = <5000>;
428 #address-cells = <1>;
431 /* MAXIM_PMBUS - 00 */
432 max15301@a { /* u46 */
433 compatible = "maxim,max15301";
436 max15303@b { /* u4 */
437 compatible = "maxim,max15303";
440 max15303@10 { /* u13 */
441 compatible = "maxim,max15303";
444 max15301@13 { /* u47 */
445 compatible = "maxim,max15301";
448 max15303@14 { /* u7 */
449 compatible = "maxim,max15303";
452 max15303@15 { /* u6 */
453 compatible = "maxim,max15303";
456 max15303@16 { /* u10 */
457 compatible = "maxim,max15303";
460 max15303@17 { /* u9 */
461 compatible = "maxim,max15303";
464 max15301@18 { /* u63 */
465 compatible = "maxim,max15301";
468 max15303@1a { /* u49 */
469 compatible = "maxim,max15303";
472 max15303@1d { /* u18 */
473 compatible = "maxim,max15303";
476 max15303@20 { /* u8 */
477 compatible = "maxim,max15303";
478 status = "disabled"; /* unreachable */
481 max20751@72 { /* u95 */
482 compatible = "maxim,max20751";
485 max20751@73 { /* u96 */
486 compatible = "maxim,max20751";
490 /* Bus 3 is not connected */
496 clock-frequency = <400000>;
497 pinctrl-names = "default", "gpio";
498 pinctrl-0 = <&pinctrl_i2c1_default>;
499 pinctrl-1 = <&pinctrl_i2c1_gpio>;
500 scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
501 sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
503 /* PL i2c via PCA9306 - u45 */
504 i2c-mux@74 { /* u34 */
505 compatible = "nxp,pca9548";
506 #address-cells = <1>;
510 #address-cells = <1>;
514 * IIC_EEPROM 1kB memory which uses 256B blocks
515 * where every block has different address.
516 * 0 - 256B address 0x54
517 * 256B - 512B address 0x55
518 * 512B - 768B address 0x56
519 * 768B - 1024B address 0x57
521 eeprom: eeprom@54 { /* u23 */
522 compatible = "atmel,24c08";
527 #address-cells = <1>;
530 si5341: clock-generator@36 { /* SI5341 - u69 */
531 compatible = "silabs,si5341";
534 #address-cells = <1>;
537 clock-names = "xtal";
538 clock-output-names = "si5341";
541 /* refclk0 for PS-GT, used for DP */
546 /* refclk2 for PS-GT, used for USB3 */
551 /* refclk3 for PS-GT, used for SATA */
556 /* refclk4 for PS-GT, used for PCIE slot */
561 /* refclk5 for PS-GT, used for PCIE */
566 /* refclk6 PL CLK125 */
571 /* refclk7 PL CLK74 */
576 /* refclk9 used for PS_REF_CLK 33.3 MHz */
583 #address-cells = <1>;
586 si570_1: clock-generator@5d { /* USER SI570 - u42 */
588 compatible = "silabs,si570";
590 temperature-stability = <50>;
591 factory-fout = <300000000>;
592 clock-frequency = <300000000>;
593 clock-output-names = "si570_user";
597 #address-cells = <1>;
600 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
602 compatible = "silabs,si570";
604 temperature-stability = <50>; /* copy from zc702 */
605 factory-fout = <156250000>;
606 clock-frequency = <148500000>;
607 clock-output-names = "si570_mgt";
611 #address-cells = <1>;
616 /* 5 - 7 unconnected */
620 compatible = "nxp,pca9548"; /* u135 */
621 #address-cells = <1>;
626 #address-cells = <1>;
632 #address-cells = <1>;
638 #address-cells = <1>;
644 #address-cells = <1>;
650 #address-cells = <1>;
656 #address-cells = <1>;
662 #address-cells = <1>;
668 #address-cells = <1>;
678 pinctrl_i2c0_default: i2c0-default {
680 groups = "i2c0_3_grp";
685 groups = "i2c0_3_grp";
687 slew-rate = <SLEW_RATE_SLOW>;
688 power-source = <IO_STANDARD_LVCMOS18>;
692 pinctrl_i2c0_gpio: i2c0-gpio {
694 groups = "gpio0_14_grp", "gpio0_15_grp";
699 groups = "gpio0_14_grp", "gpio0_15_grp";
700 slew-rate = <SLEW_RATE_SLOW>;
701 power-source = <IO_STANDARD_LVCMOS18>;
705 pinctrl_i2c1_default: i2c1-default {
707 groups = "i2c1_4_grp";
712 groups = "i2c1_4_grp";
714 slew-rate = <SLEW_RATE_SLOW>;
715 power-source = <IO_STANDARD_LVCMOS18>;
719 pinctrl_i2c1_gpio: i2c1-gpio {
721 groups = "gpio0_16_grp", "gpio0_17_grp";
726 groups = "gpio0_16_grp", "gpio0_17_grp";
727 slew-rate = <SLEW_RATE_SLOW>;
728 power-source = <IO_STANDARD_LVCMOS18>;
732 pinctrl_uart0_default: uart0-default {
734 groups = "uart0_4_grp";
739 groups = "uart0_4_grp";
740 slew-rate = <SLEW_RATE_SLOW>;
741 power-source = <IO_STANDARD_LVCMOS18>;
755 pinctrl_uart1_default: uart1-default {
757 groups = "uart1_5_grp";
762 groups = "uart1_5_grp";
763 slew-rate = <SLEW_RATE_SLOW>;
764 power-source = <IO_STANDARD_LVCMOS18>;
778 pinctrl_usb0_default: usb0-default {
780 groups = "usb0_0_grp";
785 groups = "usb0_0_grp";
786 power-source = <IO_STANDARD_LVCMOS18>;
790 pins = "MIO52", "MIO53", "MIO55";
792 drive-strength = <12>;
793 slew-rate = <SLEW_RATE_FAST>;
797 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
798 "MIO60", "MIO61", "MIO62", "MIO63";
800 drive-strength = <4>;
801 slew-rate = <SLEW_RATE_SLOW>;
805 pinctrl_gem3_default: gem3-default {
807 function = "ethernet3";
808 groups = "ethernet3_0_grp";
812 groups = "ethernet3_0_grp";
813 slew-rate = <SLEW_RATE_SLOW>;
814 power-source = <IO_STANDARD_LVCMOS18>;
818 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
825 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
833 groups = "mdio3_0_grp";
837 groups = "mdio3_0_grp";
838 slew-rate = <SLEW_RATE_SLOW>;
839 power-source = <IO_STANDARD_LVCMOS18>;
844 pinctrl_can1_default: can1-default {
847 groups = "can1_6_grp";
851 groups = "can1_6_grp";
852 slew-rate = <SLEW_RATE_SLOW>;
853 power-source = <IO_STANDARD_LVCMOS18>;
867 pinctrl_sdhci1_default: sdhci1-default {
869 groups = "sdio1_0_grp";
874 groups = "sdio1_0_grp";
875 slew-rate = <SLEW_RATE_SLOW>;
876 power-source = <IO_STANDARD_LVCMOS18>;
881 groups = "sdio1_cd_0_grp";
882 function = "sdio1_cd";
886 groups = "sdio1_cd_0_grp";
889 slew-rate = <SLEW_RATE_SLOW>;
890 power-source = <IO_STANDARD_LVCMOS18>;
894 groups = "sdio1_wp_0_grp";
895 function = "sdio1_wp";
899 groups = "sdio1_wp_0_grp";
902 slew-rate = <SLEW_RATE_SLOW>;
903 power-source = <IO_STANDARD_LVCMOS18>;
907 pinctrl_gpio_default: gpio-default {
910 groups = "gpio0_22_grp", "gpio0_23_grp";
914 groups = "gpio0_22_grp", "gpio0_23_grp";
915 slew-rate = <SLEW_RATE_SLOW>;
916 power-source = <IO_STANDARD_LVCMOS18>;
921 groups = "gpio0_13_grp", "gpio0_38_grp";
925 groups = "gpio0_13_grp", "gpio0_38_grp";
926 slew-rate = <SLEW_RATE_SLOW>;
927 power-source = <IO_STANDARD_LVCMOS18>;
931 pins = "MIO22", "MIO23";
936 pins = "MIO13", "MIO38";
948 /* pcie, sata, usb3, dp */
949 clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
950 clock-names = "ref0", "ref1", "ref2", "ref3";
956 compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
957 #address-cells = <1>;
960 spi-tx-bus-width = <4>;
961 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
962 spi-max-frequency = <108000000>; /* Based on DC1 spec */
972 /* SATA OOB timing settings */
973 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
974 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
975 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
976 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
977 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
978 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
979 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
980 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
981 phy-names = "sata-phy";
982 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
985 /* SD1 with level shifter */
989 * 1.0 revision has level shifter and this property should be
990 * removed for supporting UHS mode
993 pinctrl-names = "default";
994 pinctrl-0 = <&pinctrl_sdhci1_default>;
1000 pinctrl-names = "default";
1001 pinctrl-0 = <&pinctrl_uart0_default>;
1006 pinctrl-names = "default";
1007 pinctrl-0 = <&pinctrl_uart1_default>;
1010 /* ULPI SMSC USB3320 */
1013 pinctrl-names = "default";
1014 pinctrl-0 = <&pinctrl_usb0_default>;
1015 phy-names = "usb3-phy";
1016 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
1022 snps,usb3_lpm_capable;
1023 maximum-speed = "super-speed";
1048 phy-names = "dp-phy0";
1049 phys = <&psgtr 1 PHY_TYPE_DP 0 3>;