1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU102 RevA
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
20 model = "ZynqMP ZCU102 RevA";
21 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
38 bootargs = "earlycon";
39 stdout-path = "serial0:115200n8";
43 device_type = "memory";
44 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
48 compatible = "gpio-keys";
52 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
53 linux,code = <KEY_DOWN>;
60 compatible = "gpio-leds";
63 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
64 linux,default-trigger = "heartbeat";
69 compatible = "iio-hwmon";
70 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
73 compatible = "iio-hwmon";
74 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
77 compatible = "iio-hwmon";
78 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
81 compatible = "iio-hwmon";
82 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
85 compatible = "iio-hwmon";
86 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
89 compatible = "iio-hwmon";
90 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
93 compatible = "iio-hwmon";
94 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
97 compatible = "iio-hwmon";
98 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
101 compatible = "iio-hwmon";
102 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
105 compatible = "iio-hwmon";
106 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
109 compatible = "iio-hwmon";
110 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
113 compatible = "iio-hwmon";
114 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
117 compatible = "iio-hwmon";
118 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
121 compatible = "iio-hwmon";
122 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
125 compatible = "iio-hwmon";
126 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
129 compatible = "iio-hwmon";
130 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
133 compatible = "iio-hwmon";
134 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
137 compatible = "iio-hwmon";
138 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
141 /* 48MHz reference crystal */
143 compatible = "fixed-clock";
145 clock-frequency = <48000000>;
149 compatible = "fixed-clock";
151 clock-frequency = <114285000>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_can1_default>;
199 phy-handle = <&phy0>;
200 phy-mode = "rgmii-id";
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_gem3_default>;
203 phy0: ethernet-phy@21 {
205 ti,rx-internal-delay = <0x8>;
206 ti,tx-internal-delay = <0xa>;
207 ti,fifo-depth = <0x1>;
208 ti,dp83867-rxctrl-strap-quirk;
209 /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
215 pinctrl-names = "default";
216 pinctrl-0 = <&pinctrl_gpio_default>;
221 clock-frequency = <400000>;
222 pinctrl-names = "default", "gpio";
223 pinctrl-0 = <&pinctrl_i2c0_default>;
224 pinctrl-1 = <&pinctrl_i2c0_gpio>;
225 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
226 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
228 tca6416_u97: gpio@20 {
229 compatible = "ti,tca6416";
231 gpio-controller; /* IRQ not connected */
233 gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
234 "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
235 "", "", "", "", "", "", "", "", "";
239 output-low; /* PCIE = 0, DP = 1 */
245 output-high; /* PCIE = 0, DP = 1 */
251 output-high; /* PCIE = 0, USB0 = 1 */
257 output-high; /* PCIE = 0, SATA = 1 */
262 tca6416_u61: gpio@21 {
263 compatible = "ti,tca6416";
265 gpio-controller; /* IRQ not connected */
267 gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS",
268 "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN",
269 "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN",
270 "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", "";
273 i2c-mux@75 { /* u60 */
274 compatible = "nxp,pca9544";
275 #address-cells = <1>;
279 #address-cells = <1>;
283 u76: ina226@40 { /* u76 */
284 compatible = "ti,ina226";
285 #io-channel-cells = <1>;
286 label = "ina226-u76";
288 shunt-resistor = <5000>;
290 u77: ina226@41 { /* u77 */
291 compatible = "ti,ina226";
292 #io-channel-cells = <1>;
293 label = "ina226-u77";
295 shunt-resistor = <5000>;
297 u78: ina226@42 { /* u78 */
298 compatible = "ti,ina226";
299 #io-channel-cells = <1>;
300 label = "ina226-u78";
302 shunt-resistor = <5000>;
304 u87: ina226@43 { /* u87 */
305 compatible = "ti,ina226";
306 #io-channel-cells = <1>;
307 label = "ina226-u87";
309 shunt-resistor = <5000>;
311 u85: ina226@44 { /* u85 */
312 compatible = "ti,ina226";
313 #io-channel-cells = <1>;
314 label = "ina226-u85";
316 shunt-resistor = <5000>;
318 u86: ina226@45 { /* u86 */
319 compatible = "ti,ina226";
320 #io-channel-cells = <1>;
321 label = "ina226-u86";
323 shunt-resistor = <5000>;
325 u93: ina226@46 { /* u93 */
326 compatible = "ti,ina226";
327 #io-channel-cells = <1>;
328 label = "ina226-u93";
330 shunt-resistor = <5000>;
332 u88: ina226@47 { /* u88 */
333 compatible = "ti,ina226";
334 #io-channel-cells = <1>;
335 label = "ina226-u88";
337 shunt-resistor = <5000>;
339 u15: ina226@4a { /* u15 */
340 compatible = "ti,ina226";
341 #io-channel-cells = <1>;
342 label = "ina226-u15";
344 shunt-resistor = <5000>;
346 u92: ina226@4b { /* u92 */
347 compatible = "ti,ina226";
348 #io-channel-cells = <1>;
349 label = "ina226-u92";
351 shunt-resistor = <5000>;
355 #address-cells = <1>;
359 u79: ina226@40 { /* u79 */
360 compatible = "ti,ina226";
361 #io-channel-cells = <1>;
362 label = "ina226-u79";
364 shunt-resistor = <2000>;
366 u81: ina226@41 { /* u81 */
367 compatible = "ti,ina226";
368 #io-channel-cells = <1>;
369 label = "ina226-u81";
371 shunt-resistor = <5000>;
373 u80: ina226@42 { /* u80 */
374 compatible = "ti,ina226";
375 #io-channel-cells = <1>;
376 label = "ina226-u80";
378 shunt-resistor = <5000>;
380 u84: ina226@43 { /* u84 */
381 compatible = "ti,ina226";
382 #io-channel-cells = <1>;
383 label = "ina226-u84";
385 shunt-resistor = <5000>;
387 u16: ina226@44 { /* u16 */
388 compatible = "ti,ina226";
389 #io-channel-cells = <1>;
390 label = "ina226-u16";
392 shunt-resistor = <5000>;
394 u65: ina226@45 { /* u65 */
395 compatible = "ti,ina226";
396 #io-channel-cells = <1>;
397 label = "ina226-u65";
399 shunt-resistor = <5000>;
401 u74: ina226@46 { /* u74 */
402 compatible = "ti,ina226";
403 #io-channel-cells = <1>;
404 label = "ina226-u74";
406 shunt-resistor = <5000>;
408 u75: ina226@47 { /* u75 */
409 compatible = "ti,ina226";
410 #io-channel-cells = <1>;
411 label = "ina226-u75";
413 shunt-resistor = <5000>;
417 #address-cells = <1>;
420 /* MAXIM_PMBUS - 00 */
421 max15301@a { /* u46 */
422 compatible = "maxim,max15301";
425 max15303@b { /* u4 */
426 compatible = "maxim,max15303";
429 max15303@10 { /* u13 */
430 compatible = "maxim,max15303";
433 max15301@13 { /* u47 */
434 compatible = "maxim,max15301";
437 max15303@14 { /* u7 */
438 compatible = "maxim,max15303";
441 max15303@15 { /* u6 */
442 compatible = "maxim,max15303";
445 max15303@16 { /* u10 */
446 compatible = "maxim,max15303";
449 max15303@17 { /* u9 */
450 compatible = "maxim,max15303";
453 max15301@18 { /* u63 */
454 compatible = "maxim,max15301";
457 max15303@1a { /* u49 */
458 compatible = "maxim,max15303";
461 max15303@1d { /* u18 */
462 compatible = "maxim,max15303";
465 max15303@20 { /* u8 */
466 compatible = "maxim,max15303";
467 status = "disabled"; /* unreachable */
470 max20751@72 { /* u95 */
471 compatible = "maxim,max20751";
474 max20751@73 { /* u96 */
475 compatible = "maxim,max20751";
479 /* Bus 3 is not connected */
485 clock-frequency = <400000>;
486 pinctrl-names = "default", "gpio";
487 pinctrl-0 = <&pinctrl_i2c1_default>;
488 pinctrl-1 = <&pinctrl_i2c1_gpio>;
489 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
490 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
492 /* PL i2c via PCA9306 - u45 */
493 i2c-mux@74 { /* u34 */
494 compatible = "nxp,pca9548";
495 #address-cells = <1>;
499 #address-cells = <1>;
503 * IIC_EEPROM 1kB memory which uses 256B blocks
504 * where every block has different address.
505 * 0 - 256B address 0x54
506 * 256B - 512B address 0x55
507 * 512B - 768B address 0x56
508 * 768B - 1024B address 0x57
510 eeprom: eeprom@54 { /* u23 */
511 compatible = "atmel,24c08";
516 #address-cells = <1>;
519 si5341: clock-generator@36 { /* SI5341 - u69 */
520 compatible = "silabs,si5341";
523 #address-cells = <1>;
526 clock-names = "xtal";
527 clock-output-names = "si5341";
530 /* refclk0 for PS-GT, used for DP */
535 /* refclk2 for PS-GT, used for USB3 */
540 /* refclk3 for PS-GT, used for SATA */
545 /* refclk4 for PS-GT, used for PCIE slot */
550 /* refclk5 for PS-GT, used for PCIE */
555 /* refclk6 PL CLK125 */
560 /* refclk7 PL CLK74 */
565 /* refclk9 used for PS_REF_CLK 33.3 MHz */
572 #address-cells = <1>;
575 si570_1: clock-generator@5d { /* USER SI570 - u42 */
577 compatible = "silabs,si570";
579 temperature-stability = <50>;
580 factory-fout = <300000000>;
581 clock-frequency = <300000000>;
582 clock-output-names = "si570_user";
586 #address-cells = <1>;
589 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
591 compatible = "silabs,si570";
593 temperature-stability = <50>; /* copy from zc702 */
594 factory-fout = <156250000>;
595 clock-frequency = <148500000>;
596 clock-output-names = "si570_mgt";
600 #address-cells = <1>;
605 /* 5 - 7 unconnected */
609 compatible = "nxp,pca9548"; /* u135 */
610 #address-cells = <1>;
615 #address-cells = <1>;
621 #address-cells = <1>;
627 #address-cells = <1>;
633 #address-cells = <1>;
639 #address-cells = <1>;
645 #address-cells = <1>;
651 #address-cells = <1>;
657 #address-cells = <1>;
667 pinctrl_i2c0_default: i2c0-default {
669 groups = "i2c0_3_grp";
674 groups = "i2c0_3_grp";
676 slew-rate = <SLEW_RATE_SLOW>;
677 power-source = <IO_STANDARD_LVCMOS18>;
681 pinctrl_i2c0_gpio: i2c0-gpio {
683 groups = "gpio0_14_grp", "gpio0_15_grp";
688 groups = "gpio0_14_grp", "gpio0_15_grp";
689 slew-rate = <SLEW_RATE_SLOW>;
690 power-source = <IO_STANDARD_LVCMOS18>;
694 pinctrl_i2c1_default: i2c1-default {
696 groups = "i2c1_4_grp";
701 groups = "i2c1_4_grp";
703 slew-rate = <SLEW_RATE_SLOW>;
704 power-source = <IO_STANDARD_LVCMOS18>;
708 pinctrl_i2c1_gpio: i2c1-gpio {
710 groups = "gpio0_16_grp", "gpio0_17_grp";
715 groups = "gpio0_16_grp", "gpio0_17_grp";
716 slew-rate = <SLEW_RATE_SLOW>;
717 power-source = <IO_STANDARD_LVCMOS18>;
721 pinctrl_uart0_default: uart0-default {
723 groups = "uart0_4_grp";
728 groups = "uart0_4_grp";
729 slew-rate = <SLEW_RATE_SLOW>;
730 power-source = <IO_STANDARD_LVCMOS18>;
744 pinctrl_uart1_default: uart1-default {
746 groups = "uart1_5_grp";
751 groups = "uart1_5_grp";
752 slew-rate = <SLEW_RATE_SLOW>;
753 power-source = <IO_STANDARD_LVCMOS18>;
767 pinctrl_usb0_default: usb0-default {
769 groups = "usb0_0_grp";
774 groups = "usb0_0_grp";
775 slew-rate = <SLEW_RATE_SLOW>;
776 power-source = <IO_STANDARD_LVCMOS18>;
780 pins = "MIO52", "MIO53", "MIO55";
785 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
786 "MIO60", "MIO61", "MIO62", "MIO63";
791 pinctrl_gem3_default: gem3-default {
793 function = "ethernet3";
794 groups = "ethernet3_0_grp";
798 groups = "ethernet3_0_grp";
799 slew-rate = <SLEW_RATE_SLOW>;
800 power-source = <IO_STANDARD_LVCMOS18>;
804 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
811 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
819 groups = "mdio3_0_grp";
823 groups = "mdio3_0_grp";
824 slew-rate = <SLEW_RATE_SLOW>;
825 power-source = <IO_STANDARD_LVCMOS18>;
830 pinctrl_can1_default: can1-default {
833 groups = "can1_6_grp";
837 groups = "can1_6_grp";
838 slew-rate = <SLEW_RATE_SLOW>;
839 power-source = <IO_STANDARD_LVCMOS18>;
853 pinctrl_sdhci1_default: sdhci1-default {
855 groups = "sdio1_0_grp";
860 groups = "sdio1_0_grp";
861 slew-rate = <SLEW_RATE_SLOW>;
862 power-source = <IO_STANDARD_LVCMOS18>;
867 groups = "sdio1_cd_0_grp";
868 function = "sdio1_cd";
872 groups = "sdio1_cd_0_grp";
875 slew-rate = <SLEW_RATE_SLOW>;
876 power-source = <IO_STANDARD_LVCMOS18>;
880 groups = "sdio1_wp_0_grp";
881 function = "sdio1_wp";
885 groups = "sdio1_wp_0_grp";
888 slew-rate = <SLEW_RATE_SLOW>;
889 power-source = <IO_STANDARD_LVCMOS18>;
893 pinctrl_gpio_default: gpio-default {
896 groups = "gpio0_22_grp", "gpio0_23_grp";
900 groups = "gpio0_22_grp", "gpio0_23_grp";
901 slew-rate = <SLEW_RATE_SLOW>;
902 power-source = <IO_STANDARD_LVCMOS18>;
907 groups = "gpio0_13_grp", "gpio0_38_grp";
911 groups = "gpio0_13_grp", "gpio0_38_grp";
912 slew-rate = <SLEW_RATE_SLOW>;
913 power-source = <IO_STANDARD_LVCMOS18>;
917 pins = "MIO22", "MIO23";
922 pins = "MIO13", "MIO38";
934 /* pcie, sata, usb3, dp */
935 clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
936 clock-names = "ref0", "ref1", "ref2", "ref3";
942 compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
943 #address-cells = <1>;
946 spi-tx-bus-width = <1>;
947 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
948 spi-max-frequency = <108000000>; /* Based on DC1 spec */
958 /* SATA OOB timing settings */
959 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
960 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
961 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
962 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
963 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
964 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
965 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
966 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
967 phy-names = "sata-phy";
968 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
971 /* SD1 with level shifter */
975 * 1.0 revision has level shifter and this property should be
976 * removed for supporting UHS mode
979 pinctrl-names = "default";
980 pinctrl-0 = <&pinctrl_sdhci1_default>;
986 pinctrl-names = "default";
987 pinctrl-0 = <&pinctrl_uart0_default>;
992 pinctrl-names = "default";
993 pinctrl-0 = <&pinctrl_uart1_default>;
996 /* ULPI SMSC USB3320 */
999 pinctrl-names = "default";
1000 pinctrl-0 = <&pinctrl_usb0_default>;
1001 phy-names = "usb3-phy";
1002 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
1008 snps,usb3_lpm_capable;
1009 maximum-speed = "super-speed";
1022 phy-names = "dp-phy0";
1023 phys = <&psgtr 1 PHY_TYPE_DP 0 3>;