1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU100 revC
5 * (C) Copyright 2016 - 2021, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
8 * Nathalie Chan King Choy
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 #include <dt-bindings/phy/phy.h>
22 model = "ZynqMP ZCU100 RevC";
23 compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp";
40 bootargs = "earlycon";
41 stdout-path = "serial0:115200n8";
45 device_type = "memory";
46 reg = <0x0 0x0 0x0 0x80000000>;
50 compatible = "gpio-keys";
54 gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
55 linux,code = <KEY_POWER>;
62 compatible = "gpio-leds";
65 gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
66 linux,default-trigger = "heartbeat";
71 gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
72 linux,default-trigger = "phy0tx"; /* WLAN tx */
73 default-state = "off";
78 gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
79 linux,default-trigger = "phy0rx"; /* WLAN rx */
80 default-state = "off";
85 gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
86 linux,default-trigger = "bluetooth-power";
89 vbus-det { /* U5 USB5744 VBUS detection via MIO25 */
91 gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
96 wmmcsdio_fixed: fixedregulator-mmcsdio {
97 compatible = "regulator-fixed";
98 regulator-name = "wmmcsdio_fixed";
99 regulator-min-microvolt = <3300000>;
100 regulator-max-microvolt = <3300000>;
105 sdio_pwrseq: sdio-pwrseq {
106 compatible = "mmc-pwrseq-simple";
107 reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
108 post-power-on-delay-ms = <10>;
112 compatible = "iio-hwmon";
113 io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
116 si5335_0: si5335_0 { /* clk0_usb - u23 */
117 compatible = "fixed-clock";
119 clock-frequency = <26000000>;
122 si5335_1: si5335_1 { /* clk1_dp - u23 */
123 compatible = "fixed-clock";
125 clock-frequency = <27000000>;
135 gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL",
136 "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS",
137 "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1",
138 "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1",
139 "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT",
140 "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE",
141 "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL",
142 "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C",
143 "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E",
144 "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3",
145 "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2",
146 "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3",
147 "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK",
148 "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1",
149 "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6",
150 "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */
152 "", "", "", "", "", "", "", "", "", "",
153 "", "", "", "", "", "", "", "", "", "",
154 "", "", "", "", "", "", "", "", "", "",
155 "", "", "", "", "", "", "", "", "", "",
156 "", "", "", "", "", "", "", "", "", "",
157 "", "", "", "", "", "", "", "", "", "",
158 "", "", "", "", "", "", "", "", "", "",
159 "", "", "", "", "", "", "", "", "", "",
160 "", "", "", "", "", "", "", "", "", "",
166 pinctrl-names = "default", "gpio";
167 pinctrl-0 = <&pinctrl_i2c1_default>;
168 pinctrl-1 = <&pinctrl_i2c1_gpio>;
169 scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
170 sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
171 clock-frequency = <100000>;
172 i2c-mux@75 { /* u11 */
173 compatible = "nxp,pca9548";
174 #address-cells = <1>;
178 #address-cells = <1>;
184 #address-cells = <1>;
190 #address-cells = <1>;
196 #address-cells = <1>;
202 #address-cells = <1>;
206 pmic: pmic@5e { /* Custom TI PMIC u33 */
207 compatible = "ti,tps65086";
209 interrupt-parent = <&gpio>;
210 interrupts = <77 IRQ_TYPE_LEVEL_LOW>;
216 #address-cells = <1>;
220 u35: ina226@40 { /* u35 */
221 compatible = "ti,ina226";
222 #io-channel-cells = <1>;
224 shunt-resistor = <10000>;
225 /* MIO31 is alert which should be routed to PMUFW */
229 #address-cells = <1>;
237 #address-cells = <1>;
242 * 100kHz - this is default freq for us
250 pinctrl_i2c1_default: i2c1-default {
252 groups = "i2c1_1_grp";
257 groups = "i2c1_1_grp";
259 slew-rate = <SLEW_RATE_SLOW>;
260 power-source = <IO_STANDARD_LVCMOS18>;
264 pinctrl_i2c1_gpio: i2c1-gpio {
266 groups = "gpio0_4_grp", "gpio0_5_grp";
271 groups = "gpio0_4_grp", "gpio0_5_grp";
272 slew-rate = <SLEW_RATE_SLOW>;
273 power-source = <IO_STANDARD_LVCMOS18>;
277 pinctrl_sdhci0_default: sdhci0-default {
279 groups = "sdio0_3_grp";
284 groups = "sdio0_3_grp";
285 slew-rate = <SLEW_RATE_SLOW>;
286 power-source = <IO_STANDARD_LVCMOS18>;
291 groups = "sdio0_cd_0_grp";
292 function = "sdio0_cd";
296 groups = "sdio0_cd_0_grp";
299 slew-rate = <SLEW_RATE_SLOW>;
300 power-source = <IO_STANDARD_LVCMOS18>;
304 pinctrl_sdhci1_default: sdhci1-default {
306 groups = "sdio1_2_grp";
311 groups = "sdio1_2_grp";
312 slew-rate = <SLEW_RATE_SLOW>;
313 power-source = <IO_STANDARD_LVCMOS18>;
318 pinctrl_spi0_default: spi0-default {
320 groups = "spi0_3_grp";
325 groups = "spi0_3_grp";
327 slew-rate = <SLEW_RATE_SLOW>;
328 power-source = <IO_STANDARD_LVCMOS18>;
332 groups = "spi0_ss_9_grp";
333 function = "spi0_ss";
337 groups = "spi0_ss_9_grp";
343 pinctrl_spi1_default: spi1-default {
345 groups = "spi1_0_grp";
350 groups = "spi1_0_grp";
352 slew-rate = <SLEW_RATE_SLOW>;
353 power-source = <IO_STANDARD_LVCMOS18>;
357 groups = "spi1_ss_0_grp";
358 function = "spi1_ss";
362 groups = "spi1_ss_0_grp";
368 pinctrl_uart0_default: uart0-default {
370 groups = "uart0_0_grp";
375 groups = "uart0_0_grp";
376 slew-rate = <SLEW_RATE_SLOW>;
377 power-source = <IO_STANDARD_LVCMOS18>;
391 pinctrl_uart1_default: uart1-default {
393 groups = "uart1_0_grp";
398 groups = "uart1_0_grp";
399 slew-rate = <SLEW_RATE_SLOW>;
400 power-source = <IO_STANDARD_LVCMOS18>;
414 pinctrl_usb0_default: usb0-default {
416 groups = "usb0_0_grp";
421 groups = "usb0_0_grp";
422 slew-rate = <SLEW_RATE_SLOW>;
423 power-source = <IO_STANDARD_LVCMOS18>;
427 pins = "MIO52", "MIO53", "MIO55";
432 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
433 "MIO60", "MIO61", "MIO62", "MIO63";
438 pinctrl_usb1_default: usb1-default {
440 groups = "usb1_0_grp";
445 groups = "usb1_0_grp";
446 slew-rate = <SLEW_RATE_SLOW>;
447 power-source = <IO_STANDARD_LVCMOS18>;
451 pins = "MIO64", "MIO65", "MIO67";
456 pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
457 "MIO72", "MIO73", "MIO74", "MIO75";
466 clocks = <&si5335_0>, <&si5335_1>;
467 clock-names = "ref0", "ref1";
474 /* SD0 only supports 3.3V, no level shifter */
479 pinctrl-names = "default";
480 pinctrl-0 = <&pinctrl_sdhci0_default>;
487 pinctrl-names = "default";
488 pinctrl-0 = <&pinctrl_sdhci1_default>;
493 mmc-pwrseq = <&sdio_pwrseq>;
494 vqmmc-supply = <&wmmcsdio_fixed>;
495 #address-cells = <1>;
498 compatible = "ti,wl1831";
500 interrupt-parent = <&gpio>;
501 interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */
505 &spi0 { /* Low Speed connector */
509 pinctrl-names = "default";
510 pinctrl-0 = <&pinctrl_spi0_default>;
513 &spi1 { /* High Speed connector */
517 pinctrl-names = "default";
518 pinctrl-0 = <&pinctrl_spi1_default>;
523 pinctrl-names = "default";
524 pinctrl-0 = <&pinctrl_uart0_default>;
526 compatible = "ti,wl1831-st";
527 enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
533 pinctrl-names = "default";
534 pinctrl-0 = <&pinctrl_uart1_default>;
537 /* ULPI SMSC USB3320 */
540 pinctrl-names = "default";
541 pinctrl-0 = <&pinctrl_usb0_default>;
542 phy-names = "usb3-phy";
543 phys = <&psgtr 2 PHY_TYPE_USB3 0 0>;
548 dr_mode = "peripheral";
549 maximum-speed = "super-speed";
552 /* ULPI SMSC USB3320 */
555 pinctrl-names = "default";
556 pinctrl-0 = <&pinctrl_usb1_default>;
557 phy-names = "usb3-phy";
558 phys = <&psgtr 3 PHY_TYPE_USB3 1 0>;
564 maximum-speed = "super-speed";
577 phy-names = "dp-phy0", "dp-phy1";
578 phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
579 <&psgtr 0 PHY_TYPE_DP 1 1>;