1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
7 * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
8 * Michal Simek <michal.simek@amd.com>
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm019-dc5 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
32 bootargs = "earlycon";
33 stdout-path = "serial0:115200n8";
37 device_type = "memory";
38 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
77 phy-mode = "rgmii-id";
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_gem1_default>;
80 phy0: ethernet-phy@0 {
91 pinctrl-names = "default", "gpio";
92 pinctrl-0 = <&pinctrl_i2c0_default>;
93 pinctrl-1 = <&pinctrl_i2c0_gpio>;
94 scl-gpios = <&gpio 74 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
95 sda-gpios = <&gpio 75 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
100 pinctrl-names = "default", "gpio";
101 pinctrl-0 = <&pinctrl_i2c1_default>;
102 pinctrl-1 = <&pinctrl_i2c1_gpio>;
103 scl-gpios = <&gpio 76 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
104 sda-gpios = <&gpio 77 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
110 pinctrl_i2c0_default: i2c0-default {
112 groups = "i2c0_18_grp";
117 groups = "i2c0_18_grp";
119 slew-rate = <SLEW_RATE_SLOW>;
120 power-source = <IO_STANDARD_LVCMOS18>;
124 pinctrl_i2c0_gpio: i2c0-gpio {
126 groups = "gpio0_74_grp", "gpio0_75_grp";
131 groups = "gpio0_74_grp", "gpio0_75_grp";
132 slew-rate = <SLEW_RATE_SLOW>;
133 power-source = <IO_STANDARD_LVCMOS18>;
137 pinctrl_i2c1_default: i2c1-default {
139 groups = "i2c1_19_grp";
144 groups = "i2c1_19_grp";
146 slew-rate = <SLEW_RATE_SLOW>;
147 power-source = <IO_STANDARD_LVCMOS18>;
151 pinctrl_i2c1_gpio: i2c1-gpio {
153 groups = "gpio0_76_grp", "gpio0_77_grp";
158 groups = "gpio0_76_grp", "gpio0_77_grp";
159 slew-rate = <SLEW_RATE_SLOW>;
160 power-source = <IO_STANDARD_LVCMOS18>;
164 pinctrl_uart0_default: uart0-default {
166 groups = "uart0_17_grp";
171 groups = "uart0_17_grp";
172 slew-rate = <SLEW_RATE_SLOW>;
173 power-source = <IO_STANDARD_LVCMOS18>;
187 pinctrl_uart1_default: uart1-default {
189 groups = "uart1_18_grp";
194 groups = "uart1_18_grp";
195 slew-rate = <SLEW_RATE_SLOW>;
196 power-source = <IO_STANDARD_LVCMOS18>;
210 pinctrl_gem1_default: gem1-default {
212 function = "ethernet1";
213 groups = "ethernet1_0_grp";
217 groups = "ethernet1_0_grp";
218 slew-rate = <SLEW_RATE_SLOW>;
219 power-source = <IO_STANDARD_LVCMOS18>;
223 pins = "MIO44", "MIO45", "MIO46", "MIO47", "MIO48",
230 pins = "MIO38", "MIO39", "MIO40", "MIO41", "MIO42",
238 groups = "mdio1_0_grp";
242 groups = "mdio1_0_grp";
243 slew-rate = <SLEW_RATE_SLOW>;
244 power-source = <IO_STANDARD_LVCMOS18>;
249 pinctrl_sdhci0_default: sdhci0-default {
251 groups = "sdio0_0_grp";
256 groups = "sdio0_0_grp";
257 slew-rate = <SLEW_RATE_SLOW>;
258 power-source = <IO_STANDARD_LVCMOS18>;
263 groups = "sdio0_cd_0_grp";
264 function = "sdio0_cd";
268 groups = "sdio0_cd_0_grp";
271 slew-rate = <SLEW_RATE_SLOW>;
272 power-source = <IO_STANDARD_LVCMOS18>;
276 groups = "sdio0_wp_0_grp";
277 function = "sdio0_wp";
281 groups = "sdio0_wp_0_grp";
284 slew-rate = <SLEW_RATE_SLOW>;
285 power-source = <IO_STANDARD_LVCMOS18>;
289 pinctrl_watchdog0_default: watchdog0-default {
291 groups = "swdt0_clk_1_grp";
292 function = "swdt0_clk";
296 groups = "swdt0_clk_1_grp";
301 groups = "swdt0_rst_1_grp";
302 function = "swdt0_rst";
306 groups = "swdt0_rst_1_grp";
308 slew-rate = <SLEW_RATE_SLOW>;
312 pinctrl_ttc0_default: ttc0-default {
314 groups = "ttc0_clk_0_grp";
315 function = "ttc0_clk";
319 groups = "ttc0_clk_0_grp";
324 groups = "ttc0_wav_0_grp";
325 function = "ttc0_wav";
329 groups = "ttc0_wav_0_grp";
331 slew-rate = <SLEW_RATE_SLOW>;
335 pinctrl_ttc1_default: ttc1-default {
337 groups = "ttc1_clk_0_grp";
338 function = "ttc1_clk";
342 groups = "ttc1_clk_0_grp";
347 groups = "ttc1_wav_0_grp";
348 function = "ttc1_wav";
352 groups = "ttc1_wav_0_grp";
354 slew-rate = <SLEW_RATE_SLOW>;
358 pinctrl_ttc2_default: ttc2-default {
360 groups = "ttc2_clk_0_grp";
361 function = "ttc2_clk";
365 groups = "ttc2_clk_0_grp";
370 groups = "ttc2_wav_0_grp";
371 function = "ttc2_wav";
375 groups = "ttc2_wav_0_grp";
377 slew-rate = <SLEW_RATE_SLOW>;
381 pinctrl_ttc3_default: ttc3-default {
383 groups = "ttc3_clk_0_grp";
384 function = "ttc3_clk";
388 groups = "ttc3_clk_0_grp";
393 groups = "ttc3_wav_0_grp";
394 function = "ttc3_wav";
398 groups = "ttc3_wav_0_grp";
400 slew-rate = <SLEW_RATE_SLOW>;
407 pinctrl-names = "default";
408 pinctrl-0 = <&pinctrl_sdhci0_default>;
415 pinctrl-names = "default";
416 pinctrl-0 = <&pinctrl_ttc0_default>;
421 pinctrl-names = "default";
422 pinctrl-0 = <&pinctrl_ttc1_default>;
427 pinctrl-names = "default";
428 pinctrl-0 = <&pinctrl_ttc2_default>;
433 pinctrl-names = "default";
434 pinctrl-0 = <&pinctrl_ttc3_default>;
439 pinctrl-names = "default";
440 pinctrl-0 = <&pinctrl_uart0_default>;
445 pinctrl-names = "default";
446 pinctrl-0 = <&pinctrl_uart1_default>;
451 pinctrl-names = "default";
452 pinctrl-0 = <&pinctrl_watchdog0_default>;