1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
8 * Michal Simek <michal.simek@amd.com>
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm016-dc2 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
34 bootargs = "earlycon";
35 stdout-path = "serial0:115200n8";
39 device_type = "memory";
40 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_can0_default>;
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_can1_default>;
91 phy-mode = "rgmii-id";
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_gem2_default>;
94 phy0: ethernet-phy@5 {
96 ti,rx-internal-delay = <0x8>;
97 ti,tx-internal-delay = <0xa>;
98 ti,fifo-depth = <0x1>;
99 ti,dp83867-rxctrl-strap-quirk;
109 clock-frequency = <400000>;
110 pinctrl-names = "default", "gpio";
111 pinctrl-0 = <&pinctrl_i2c0_default>;
112 pinctrl-1 = <&pinctrl_i2c0_gpio>;
113 scl-gpios = <&gpio 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
114 sda-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
116 tca6416_u26: gpio@20 {
117 compatible = "ti,tca6416";
121 /* IRQ not connected */
125 compatible = "dallas,ds1339";
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_nand0_default>;
138 #address-cells = <0x2>;
140 nand-ecc-mode = "soft";
141 nand-ecc-algo = "bch";
143 label = "main-storage-0";
147 #address-cells = <0x2>;
149 nand-ecc-mode = "soft";
150 nand-ecc-algo = "bch";
152 label = "main-storage-1";
158 pinctrl_can0_default: can0-default {
161 groups = "can0_9_grp";
165 groups = "can0_9_grp";
166 slew-rate = <SLEW_RATE_SLOW>;
167 power-source = <IO_STANDARD_LVCMOS18>;
181 pinctrl_can1_default: can1-default {
184 groups = "can1_8_grp";
188 groups = "can1_8_grp";
189 slew-rate = <SLEW_RATE_SLOW>;
190 power-source = <IO_STANDARD_LVCMOS18>;
204 pinctrl_i2c0_default: i2c0-default {
206 groups = "i2c0_1_grp";
211 groups = "i2c0_1_grp";
213 slew-rate = <SLEW_RATE_SLOW>;
214 power-source = <IO_STANDARD_LVCMOS18>;
218 pinctrl_i2c0_gpio: i2c0-gpio {
220 groups = "gpio0_6_grp", "gpio0_7_grp";
225 groups = "gpio0_6_grp", "gpio0_7_grp";
226 slew-rate = <SLEW_RATE_SLOW>;
227 power-source = <IO_STANDARD_LVCMOS18>;
231 pinctrl_uart0_default: uart0-default {
233 groups = "uart0_10_grp";
238 groups = "uart0_10_grp";
239 slew-rate = <SLEW_RATE_SLOW>;
240 power-source = <IO_STANDARD_LVCMOS18>;
254 pinctrl_uart1_default: uart1-default {
256 groups = "uart1_10_grp";
261 groups = "uart1_10_grp";
262 slew-rate = <SLEW_RATE_SLOW>;
263 power-source = <IO_STANDARD_LVCMOS18>;
277 pinctrl_usb1_default: usb1-default {
279 groups = "usb1_0_grp";
284 groups = "usb1_0_grp";
285 power-source = <IO_STANDARD_LVCMOS18>;
289 pins = "MIO64", "MIO65", "MIO67";
291 drive-strength = <12>;
292 slew-rate = <SLEW_RATE_FAST>;
296 pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
297 "MIO72", "MIO73", "MIO74", "MIO75";
299 drive-strength = <4>;
300 slew-rate = <SLEW_RATE_SLOW>;
304 pinctrl_gem2_default: gem2-default {
306 function = "ethernet2";
307 groups = "ethernet2_0_grp";
311 groups = "ethernet2_0_grp";
312 slew-rate = <SLEW_RATE_SLOW>;
313 power-source = <IO_STANDARD_LVCMOS18>;
317 pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62",
324 pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56",
332 groups = "mdio2_0_grp";
336 groups = "mdio2_0_grp";
337 slew-rate = <SLEW_RATE_SLOW>;
338 power-source = <IO_STANDARD_LVCMOS18>;
343 pinctrl_nand0_default: nand0-default {
345 groups = "nand0_0_grp";
350 groups = "nand0_0_grp";
355 groups = "nand0_ce_0_grp";
356 function = "nand0_ce";
360 groups = "nand0_ce_0_grp";
365 groups = "nand0_rb_0_grp";
366 function = "nand0_rb";
370 groups = "nand0_rb_0_grp";
375 groups = "nand0_dqs_0_grp";
376 function = "nand0_dqs";
380 groups = "nand0_dqs_0_grp";
385 pinctrl_spi0_default: spi0-default {
387 groups = "spi0_0_grp";
392 groups = "spi0_0_grp";
394 slew-rate = <SLEW_RATE_SLOW>;
395 power-source = <IO_STANDARD_LVCMOS18>;
399 groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
401 function = "spi0_ss";
405 groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
411 pinctrl_spi1_default: spi1-default {
413 groups = "spi1_3_grp";
418 groups = "spi1_3_grp";
420 slew-rate = <SLEW_RATE_SLOW>;
421 power-source = <IO_STANDARD_LVCMOS18>;
425 groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
427 function = "spi1_ss";
431 groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
445 pinctrl-names = "default";
446 pinctrl-0 = <&pinctrl_spi0_default>;
448 spi0_flash0: flash@0 {
449 #address-cells = <1>;
451 compatible = "sst,sst25wf080", "jedec,spi-nor";
452 spi-max-frequency = <50000000>;
457 reg = <0x0 0x100000>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&pinctrl_spi1_default>;
468 spi1_flash0: flash@0 {
469 #address-cells = <1>;
471 compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash";
472 spi-max-frequency = <20000000>;
482 /* ULPI SMSC USB3320 */
485 pinctrl-names = "default";
486 pinctrl-0 = <&pinctrl_usb1_default>;
496 pinctrl-names = "default";
497 pinctrl-0 = <&pinctrl_uart0_default>;
502 pinctrl-names = "default";
503 pinctrl-0 = <&pinctrl_uart1_default>;