1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
8 * Michal Simek <michal.simek@amd.com>
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 model = "ZynqMP zc1751-xm015-dc1 RevA";
21 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
35 bootargs = "earlycon";
36 stdout-path = "serial0:115200n8";
40 device_type = "memory";
41 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
44 clock_si5338_0: clk27 { /* u55 SI5338-GM */
45 compatible = "fixed-clock";
47 clock-frequency = <27000000>;
50 clock_si5338_2: clk26 {
51 compatible = "fixed-clock";
53 clock-frequency = <26000000>;
56 clock_si5338_3: clk150 {
57 compatible = "fixed-clock";
59 clock-frequency = <150000000>;
98 phy-mode = "rgmii-id";
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_gem3_default>;
101 phy0: ethernet-phy@0 {
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_gpio_default>;
118 clock-frequency = <400000>;
119 pinctrl-names = "default", "gpio";
120 pinctrl-0 = <&pinctrl_i2c1_default>;
121 pinctrl-1 = <&pinctrl_i2c1_gpio>;
122 scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
123 sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
126 compatible = "atmel,24c64"; /* 24AA64 */
133 pinctrl_i2c1_default: i2c1-default {
135 groups = "i2c1_9_grp";
140 groups = "i2c1_9_grp";
142 slew-rate = <SLEW_RATE_SLOW>;
143 power-source = <IO_STANDARD_LVCMOS18>;
147 pinctrl_i2c1_gpio: i2c1-gpio {
149 groups = "gpio0_36_grp", "gpio0_37_grp";
154 groups = "gpio0_36_grp", "gpio0_37_grp";
155 slew-rate = <SLEW_RATE_SLOW>;
156 power-source = <IO_STANDARD_LVCMOS18>;
160 pinctrl_uart0_default: uart0-default {
162 groups = "uart0_8_grp";
167 groups = "uart0_8_grp";
168 slew-rate = <SLEW_RATE_SLOW>;
169 power-source = <IO_STANDARD_LVCMOS18>;
183 pinctrl_usb0_default: usb0-default {
185 groups = "usb0_0_grp";
190 groups = "usb0_0_grp";
191 power-source = <IO_STANDARD_LVCMOS18>;
195 pins = "MIO52", "MIO53", "MIO55";
197 drive-strength = <12>;
198 slew-rate = <SLEW_RATE_FAST>;
202 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
203 "MIO60", "MIO61", "MIO62", "MIO63";
205 drive-strength = <4>;
206 slew-rate = <SLEW_RATE_SLOW>;
210 pinctrl_gem3_default: gem3-default {
212 function = "ethernet3";
213 groups = "ethernet3_0_grp";
217 groups = "ethernet3_0_grp";
218 slew-rate = <SLEW_RATE_SLOW>;
219 power-source = <IO_STANDARD_LVCMOS18>;
223 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
230 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
238 groups = "mdio3_0_grp";
242 groups = "mdio3_0_grp";
243 slew-rate = <SLEW_RATE_SLOW>;
244 power-source = <IO_STANDARD_LVCMOS18>;
249 pinctrl_sdhci0_default: sdhci0-default {
251 groups = "sdio0_0_grp";
256 groups = "sdio0_0_grp";
257 slew-rate = <SLEW_RATE_SLOW>;
258 power-source = <IO_STANDARD_LVCMOS18>;
263 groups = "sdio0_cd_0_grp";
264 function = "sdio0_cd";
268 groups = "sdio0_cd_0_grp";
271 slew-rate = <SLEW_RATE_SLOW>;
272 power-source = <IO_STANDARD_LVCMOS18>;
276 groups = "sdio0_wp_0_grp";
277 function = "sdio0_wp";
281 groups = "sdio0_wp_0_grp";
284 slew-rate = <SLEW_RATE_SLOW>;
285 power-source = <IO_STANDARD_LVCMOS18>;
289 pinctrl_sdhci1_default: sdhci1-default {
291 groups = "sdio1_0_grp";
296 groups = "sdio1_0_grp";
297 slew-rate = <SLEW_RATE_SLOW>;
298 power-source = <IO_STANDARD_LVCMOS18>;
303 groups = "sdio1_cd_0_grp";
304 function = "sdio1_cd";
308 groups = "sdio1_cd_0_grp";
311 slew-rate = <SLEW_RATE_SLOW>;
312 power-source = <IO_STANDARD_LVCMOS18>;
316 groups = "sdio1_wp_0_grp";
317 function = "sdio1_wp";
321 groups = "sdio1_wp_0_grp";
324 slew-rate = <SLEW_RATE_SLOW>;
325 power-source = <IO_STANDARD_LVCMOS18>;
329 pinctrl_gpio_default: gpio-default {
332 groups = "gpio0_38_grp";
336 groups = "gpio0_38_grp";
338 slew-rate = <SLEW_RATE_SLOW>;
339 power-source = <IO_STANDARD_LVCMOS18>;
347 clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>;
348 clock-names = "ref1", "ref2", "ref3";
354 compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */
355 #address-cells = <1>;
358 spi-tx-bus-width = <4>;
359 spi-rx-bus-width = <4>;
360 spi-max-frequency = <108000000>; /* Based on DC1 spec */
370 /* SATA phy OOB timing settings */
371 ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
372 ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
373 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
374 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
375 ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
376 ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
377 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
378 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
379 phy-names = "sata-phy";
380 phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
386 pinctrl-names = "default";
387 pinctrl-0 = <&pinctrl_sdhci0_default>;
392 /* SD1 with level shifter */
396 * This property should be removed for supporting UHS mode
399 pinctrl-names = "default";
400 pinctrl-0 = <&pinctrl_sdhci1_default>;
406 pinctrl-names = "default";
407 pinctrl-0 = <&pinctrl_uart0_default>;
410 /* ULPI SMSC USB3320 */
413 pinctrl-names = "default";
414 pinctrl-0 = <&pinctrl_usb0_default>;
415 phy-names = "usb3-phy";
416 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
422 snps,usb3_lpm_capable;
423 maximum-speed = "super-speed";
432 phy-names = "dp-phy0", "dp-phy1";
433 phys = <&psgtr 1 PHY_TYPE_DP 0 0>,
434 <&psgtr 0 PHY_TYPE_DP 1 1>;