arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZC1254
   4  *
   5  * (C) Copyright 2015 - 2021, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@amd.com>
   8  * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
   9  */
  10
  11 /dts-v1/;
  12
  13 #include "zynqmp.dtsi"
  14 #include "zynqmp-clk-ccf.dtsi"
  15
  16 / {
  17         model = "ZynqMP ZC1254 RevA";
  18         compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp";
  19
  20         aliases {
  21                 serial0 = &uart0;
  22                 serial1 = &dcc;
  23                 spi0 = &qspi;
  24         };
  25
  26         chosen {
  27                 bootargs = "earlycon";
  28                 stdout-path = "serial0:115200n8";
  29         };
  30
  31         memory@0 {
  32                 device_type = "memory";
  33                 reg = <0x0 0x0 0x0 0x80000000>;
  34         };
  35 };
  36
  37 &dcc {
  38         status = "okay";
  39 };
  40
  41 &qspi {
  42         status = "okay";
  43         flash@0 {
  44                 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
  45                 #address-cells = <1>;
  46                 #size-cells = <1>;
  47                 reg = <0x0>;
  48                 spi-tx-bus-width = <4>;
  49                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
  50                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
  51         };
  52 };
  53
  54 &uart0 {
  55         status = "okay";
  56 };