1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for KV260 revA Carrier Card
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
8 * Michal Simek <michal.simek@amd.com>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
22 pinctrl-names = "default", "gpio";
23 pinctrl-0 = <&pinctrl_i2c1_default>;
24 pinctrl-1 = <&pinctrl_i2c1_gpio>;
25 scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
26 sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
28 /* u14 - 0x40 - ina260 */
29 /* u43 - 0x2d - usb5744 */
30 /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
34 si5332_0: si5332_0 { /* u17 */
35 compatible = "fixed-clock";
37 clock-frequency = <125000000>;
40 si5332_1: si5332_1 { /* u17 */
41 compatible = "fixed-clock";
43 clock-frequency = <25000000>;
46 si5332_2: si5332_2 { /* u17 */
47 compatible = "fixed-clock";
49 clock-frequency = <48000000>;
52 si5332_3: si5332_3 { /* u17 */
53 compatible = "fixed-clock";
55 clock-frequency = <24000000>;
58 si5332_4: si5332_4 { /* u17 */
59 compatible = "fixed-clock";
61 clock-frequency = <26000000>;
64 si5332_5: si5332_5 { /* u17 */
65 compatible = "fixed-clock";
67 clock-frequency = <27000000>;
74 /* pcie, usb3, sata */
75 clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
76 clock-names = "ref0", "ref1", "ref2";
81 phy-names = "dp-phy0", "dp-phy1";
82 phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
83 assigned-clock-rates = <27000000>, <25000000>, <300000000>;
88 assigned-clock-rates = <600000000>;
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_usb0_default>;
95 phy-names = "usb3-phy";
96 phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
102 snps,usb3_lpm_capable;
103 maximum-speed = "super-speed";
106 &sdhci1 { /* on CC with tuned parameters */
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_sdhci1_default>;
111 * SD 3.0 requires level shifter and this property
112 * should be removed if the board has level shifter and
113 * need to work in UHS mode
118 clk-phase-sd-hs = <126>, <60>;
119 clk-phase-uhs-sdr25 = <120>, <60>;
120 clk-phase-uhs-ddr50 = <126>, <48>;
121 assigned-clock-rates = <187498123>;
125 &gem3 { /* required by spec */
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_gem3_default>;
129 phy-handle = <&phy0>;
130 phy-mode = "rgmii-id";
131 assigned-clock-rates = <250000000>;
134 #address-cells = <1>;
137 phy0: ethernet-phy@1 {
140 compatible = "ethernet-phy-id2000.a231";
141 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
142 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
143 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
144 ti,dp83867-rxctrl-strap-quirk;
145 reset-assert-us = <100>;
146 reset-deassert-us = <280>;
147 reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
152 &pinctrl0 { /* required by spec */
155 pinctrl_uart1_default: uart1-default {
157 groups = "uart1_9_grp";
158 slew-rate = <SLEW_RATE_SLOW>;
159 power-source = <IO_STANDARD_LVCMOS18>;
160 drive-strength = <12>;
174 groups = "uart1_9_grp";
179 pinctrl_i2c1_default: i2c1-default {
181 groups = "i2c1_6_grp";
183 slew-rate = <SLEW_RATE_SLOW>;
184 power-source = <IO_STANDARD_LVCMOS18>;
188 groups = "i2c1_6_grp";
193 pinctrl_i2c1_gpio: i2c1-gpio {
195 groups = "gpio0_24_grp", "gpio0_25_grp";
196 slew-rate = <SLEW_RATE_SLOW>;
197 power-source = <IO_STANDARD_LVCMOS18>;
201 groups = "gpio0_24_grp", "gpio0_25_grp";
206 pinctrl_gem3_default: gem3-default {
208 groups = "ethernet3_0_grp";
209 slew-rate = <SLEW_RATE_SLOW>;
210 power-source = <IO_STANDARD_LVCMOS18>;
214 pins = "MIO70", "MIO72", "MIO74";
220 pins = "MIO71", "MIO73", "MIO75";
226 pins = "MIO64", "MIO65", "MIO66",
227 "MIO67", "MIO68", "MIO69";
233 groups = "mdio3_0_grp";
234 slew-rate = <SLEW_RATE_SLOW>;
235 power-source = <IO_STANDARD_LVCMOS18>;
241 groups = "mdio3_0_grp";
245 function = "ethernet3";
246 groups = "ethernet3_0_grp";
250 pinctrl_usb0_default: usb0-default {
252 groups = "usb0_0_grp";
253 power-source = <IO_STANDARD_LVCMOS18>;
257 pins = "MIO52", "MIO53", "MIO55";
259 drive-strength = <12>;
260 slew-rate = <SLEW_RATE_FAST>;
264 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
265 "MIO60", "MIO61", "MIO62", "MIO63";
267 drive-strength = <4>;
268 slew-rate = <SLEW_RATE_SLOW>;
272 groups = "usb0_0_grp";
277 pinctrl_sdhci1_default: sdhci1-default {
279 groups = "sdio1_0_grp";
280 slew-rate = <SLEW_RATE_SLOW>;
281 power-source = <IO_STANDARD_LVCMOS18>;
286 groups = "sdio1_cd_0_grp";
289 slew-rate = <SLEW_RATE_SLOW>;
290 power-source = <IO_STANDARD_LVCMOS18>;
294 groups = "sdio1_cd_0_grp";
295 function = "sdio1_cd";
299 groups = "sdio1_0_grp";
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_uart1_default>;