1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Source for the TMPV7708
5 * (C) Copyright 2018 - 2020, Toshiba Corporation.
6 * (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
10 #include <dt-bindings/clock/toshiba,tmpv770x.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
17 compatible = "toshiba,tmpv7708";
58 compatible = "arm,cortex-a53";
60 enable-method = "spin-table";
61 cpu-release-addr = <0x0 0x81100000>;
66 compatible = "arm,cortex-a53";
68 enable-method = "spin-table";
69 cpu-release-addr = <0x0 0x81100000>;
74 compatible = "arm,cortex-a53";
76 enable-method = "spin-table";
77 cpu-release-addr = <0x0 0x81100000>;
82 compatible = "arm,cortex-a53";
84 enable-method = "spin-table";
85 cpu-release-addr = <0x0 0x81100000>;
90 compatible = "arm,cortex-a53";
92 enable-method = "spin-table";
93 cpu-release-addr = <0x0 0x81100000>;
98 compatible = "arm,cortex-a53";
100 enable-method = "spin-table";
101 cpu-release-addr = <0x0 0x81100000>;
106 compatible = "arm,cortex-a53";
108 enable-method = "spin-table";
109 cpu-release-addr = <0x0 0x81100000>;
114 compatible = "arm,cortex-a53";
116 enable-method = "spin-table";
117 cpu-release-addr = <0x0 0x81100000>;
123 compatible = "arm,armv8-timer";
124 interrupt-parent = <&gic>;
126 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
127 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
128 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
129 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
132 extclk100mhz: extclk100mhz {
133 compatible = "fixed-clock";
135 clock-frequency = <100000000>;
136 clock-output-names = "extclk100mhz";
140 compatible = "fixed-clock";
141 clock-frequency = <20000000>;
146 #address-cells = <2>;
148 compatible = "simple-bus";
149 interrupt-parent = <&gic>;
152 gic: interrupt-controller@24001000 {
153 compatible = "arm,gic-400";
154 interrupt-controller;
155 #interrupt-cells = <3>;
156 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
157 reg = <0 0x24001000 0 0x1000>,
158 <0 0x24002000 0 0x2000>,
159 <0 0x24004000 0 0x2000>,
160 <0 0x24006000 0 0x2000>;
163 pmux: pmux@24190000 {
164 compatible = "toshiba,tmpv7708-pinctrl";
165 reg = <0 0x24190000 0 0x10000>;
168 gpio: gpio@28020000 {
169 compatible = "toshiba,gpio-tmpv7708";
170 reg = <0 0x28020000 0 0x1000>;
172 gpio-ranges = <&pmux 0 0 32>;
174 interrupt-controller;
175 #interrupt-cells = <2>;
176 interrupt-parent = <&gic>;
179 pipllct: clock-controller@24220000 {
180 compatible = "toshiba,tmpv7708-pipllct";
181 reg = <0 0x24220000 0 0x820>;
183 clocks = <&osc2_clk>;
186 pismu: syscon@24200000 {
187 compatible = "toshiba,tmpv7708-pismu", "syscon";
188 reg = <0 0x24200000 0 0x2140>;
193 uart0: serial@28200000 {
194 compatible = "arm,pl011", "arm,primecell";
195 reg = <0 0x28200000 0 0x1000>;
196 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
197 pinctrl-names = "default";
198 pinctrl-0 = <&uart0_pins>;
199 clocks = <&pismu TMPV770X_CLK_PIUART0>;
200 clock-names = "apb_pclk";
204 uart1: serial@28201000 {
205 compatible = "arm,pl011", "arm,primecell";
206 reg = <0 0x28201000 0 0x1000>;
207 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&uart1_pins>;
210 clocks = <&pismu TMPV770X_CLK_PIUART1>;
211 clock-names = "apb_pclk";
215 uart2: serial@28202000 {
216 compatible = "arm,pl011", "arm,primecell";
217 reg = <0 0x28202000 0 0x1000>;
218 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&uart2_pins>;
221 clocks = <&pismu TMPV770X_CLK_PIUART2>;
222 clock-names = "apb_pclk";
226 uart3: serial@28203000 {
227 compatible = "arm,pl011", "arm,primecell";
228 reg = <0 0x28203000 0 0x1000>;
229 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
230 pinctrl-names = "default";
231 pinctrl-0 = <&uart3_pins>;
232 clocks = <&pismu TMPV770X_CLK_PIUART2>;
233 clock-names = "apb_pclk";
238 compatible = "snps,designware-i2c";
239 reg = <0 0x28030000 0 0x1000>;
240 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
241 pinctrl-names = "default";
242 pinctrl-0 = <&i2c0_pins>;
243 clock-frequency = <400000>;
244 #address-cells = <1>;
246 clocks = <&pismu TMPV770X_CLK_PII2C0>;
251 compatible = "snps,designware-i2c";
252 reg = <0 0x28031000 0 0x1000>;
253 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&i2c1_pins>;
256 clock-frequency = <400000>;
257 #address-cells = <1>;
259 clocks = <&pismu TMPV770X_CLK_PII2C1>;
264 compatible = "snps,designware-i2c";
265 reg = <0 0x28032000 0 0x1000>;
266 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
267 pinctrl-names = "default";
268 pinctrl-0 = <&i2c2_pins>;
269 clock-frequency = <400000>;
270 #address-cells = <1>;
272 clocks = <&pismu TMPV770X_CLK_PII2C2>;
277 compatible = "snps,designware-i2c";
278 reg = <0 0x28033000 0 0x1000>;
279 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&i2c3_pins>;
282 clock-frequency = <400000>;
283 #address-cells = <1>;
285 clocks = <&pismu TMPV770X_CLK_PII2C3>;
290 compatible = "snps,designware-i2c";
291 reg = <0 0x28034000 0 0x1000>;
292 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
293 pinctrl-names = "default";
294 pinctrl-0 = <&i2c4_pins>;
295 clock-frequency = <400000>;
296 #address-cells = <1>;
298 clocks = <&pismu TMPV770X_CLK_PII2C4>;
303 compatible = "snps,designware-i2c";
304 reg = <0 0x28035000 0 0x1000>;
305 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&i2c5_pins>;
308 clock-frequency = <400000>;
309 #address-cells = <1>;
311 clocks = <&pismu TMPV770X_CLK_PII2C5>;
316 compatible = "snps,designware-i2c";
317 reg = <0 0x28036000 0 0x1000>;
318 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&i2c6_pins>;
321 clock-frequency = <400000>;
322 #address-cells = <1>;
324 clocks = <&pismu TMPV770X_CLK_PII2C6>;
329 compatible = "snps,designware-i2c";
330 reg = <0 0x28037000 0 0x1000>;
331 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
332 pinctrl-names = "default";
333 pinctrl-0 = <&i2c7_pins>;
334 clock-frequency = <400000>;
335 #address-cells = <1>;
337 clocks = <&pismu TMPV770X_CLK_PII2C7>;
342 compatible = "snps,designware-i2c";
343 reg = <0 0x28038000 0 0x1000>;
344 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
345 pinctrl-names = "default";
346 pinctrl-0 = <&i2c8_pins>;
347 clock-frequency = <400000>;
348 #address-cells = <1>;
350 clocks = <&pismu TMPV770X_CLK_PII2C8>;
355 compatible = "arm,pl022", "arm,primecell";
356 reg = <0 0x28140000 0 0x1000>;
357 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
358 pinctrl-names = "default";
359 pinctrl-0 = <&spi0_pins>;
361 #address-cells = <1>;
363 clocks = <&pismu TMPV770X_CLK_PISPI1>;
364 clock-names = "apb_pclk";
369 compatible = "arm,pl022", "arm,primecell";
370 reg = <0 0x28141000 0 0x1000>;
371 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
372 pinctrl-names = "default";
373 pinctrl-0 = <&spi1_pins>;
375 #address-cells = <1>;
377 clocks = <&pismu TMPV770X_CLK_PISPI1>;
378 clock-names = "apb_pclk";
383 compatible = "arm,pl022", "arm,primecell";
384 reg = <0 0x28142000 0 0x1000>;
385 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
386 pinctrl-names = "default";
387 pinctrl-0 = <&spi2_pins>;
389 #address-cells = <1>;
391 clocks = <&pismu TMPV770X_CLK_PISPI2>;
392 clock-names = "apb_pclk";
397 compatible = "arm,pl022", "arm,primecell";
398 reg = <0 0x28143000 0 0x1000>;
399 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
400 pinctrl-names = "default";
401 pinctrl-0 = <&spi3_pins>;
403 #address-cells = <1>;
405 clocks = <&pismu TMPV770X_CLK_PISPI3>;
406 clock-names = "apb_pclk";
411 compatible = "arm,pl022", "arm,primecell";
412 reg = <0 0x28144000 0 0x1000>;
413 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
414 pinctrl-names = "default";
415 pinctrl-0 = <&spi4_pins>;
417 #address-cells = <1>;
419 clocks = <&pismu TMPV770X_CLK_PISPI4>;
420 clock-names = "apb_pclk";
425 compatible = "arm,pl022", "arm,primecell";
426 reg = <0 0x28145000 0 0x1000>;
427 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
428 pinctrl-names = "default";
429 pinctrl-0 = <&spi5_pins>;
431 #address-cells = <1>;
433 clocks = <&pismu TMPV770X_CLK_PISPI5>;
434 clock-names = "apb_pclk";
439 compatible = "arm,pl022", "arm,primecell";
440 reg = <0 0x28146000 0 0x1000>;
441 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
442 pinctrl-names = "default";
443 pinctrl-0 = <&spi6_pins>;
445 #address-cells = <1>;
447 clocks = <&pismu TMPV770X_CLK_PISPI6>;
448 clock-names = "apb_pclk";
452 piether: ethernet@28000000 {
453 compatible = "toshiba,visconti-dwmac", "snps,dwmac-4.20a";
454 reg = <0 0x28000000 0 0x10000>;
455 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
456 interrupt-names = "macirq";
460 clocks = <&pismu TMPV770X_CLK_PIETHER_BUS>, <&pismu TMPV770X_CLK_PIETHER_125M>;
461 clock-names = "stmmaceth", "phy_ref_clk";
466 compatible = "toshiba,visconti-wdt";
467 reg = <0 0x28330000 0 0x1000>;
468 clocks = <&pismu TMPV770X_CLK_WDTCLK>;
473 compatible = "toshiba,visconti-pwm";
474 reg = <0 0x241c0000 0 0x1000>;
475 pinctrl-names = "default";
476 pinctrl-0 = <&pwm_mux>;
481 pcie: pcie@28400000 {
482 compatible = "toshiba,visconti-pcie";
483 reg = <0x0 0x28400000 0x0 0x00400000>,
484 <0x0 0x70000000 0x0 0x10000000>,
485 <0x0 0x28050000 0x0 0x00010000>,
486 <0x0 0x24200000 0x0 0x00002000>,
487 <0x0 0x24162000 0x0 0x00001000>;
488 reg-names = "dbi", "config", "ulreg", "smu", "mpu";
490 bus-range = <0x00 0xff>;
494 #address-cells = <3>;
496 #interrupt-cells = <1>;
497 ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000
498 0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>;
499 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
500 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
501 interrupt-names = "msi", "intr";
502 interrupt-map-mask = <0 0 0 7>;
504 <0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
505 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
506 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
507 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
508 max-link-speed = <2>;
509 clocks = <&extclk100mhz>, <&pismu TMPV770X_CLK_PCIE_MSTR>, <&pismu TMPV770X_CLK_PCIE_AUX>;
510 clock-names = "ref", "core", "aux";
516 #include "tmpv7708_pins.dtsi"