arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for J784S4 SoC Family MCU/WAKEUP Domain peripherals
   4  *
   5  * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 &cbass_mcu_wakeup {
   9         sms: system-controller@44083000 {
  10                 bootph-all;
  11                 compatible = "ti,k2g-sci";
  12                 ti,host-id = <12>;
  13
  14                 mbox-names = "rx", "tx";
  15
  16                 mboxes = <&secure_proxy_main 11>,
  17                          <&secure_proxy_main 13>;
  18
  19                 reg-names = "debug_messages";
  20                 reg = <0x00 0x44083000 0x00 0x1000>;
  21
  22                 k3_pds: power-controller {
  23                         bootph-all;
  24                         compatible = "ti,sci-pm-domain";
  25                         #power-domain-cells = <2>;
  26                 };
  27
  28                 k3_clks: clock-controller {
  29                         bootph-all;
  30                         compatible = "ti,k2g-sci-clk";
  31                         #clock-cells = <2>;
  32                 };
  33
  34                 k3_reset: reset-controller {
  35                         bootph-all;
  36                         compatible = "ti,sci-reset";
  37                         #reset-cells = <2>;
  38                 };
  39         };
  40
  41         chipid@43000014 {
  42                 bootph-all;
  43                 compatible = "ti,am654-chipid";
  44                 reg = <0x00 0x43000014 0x00 0x4>;
  45         };
  46
  47         secure_proxy_sa3: mailbox@43600000 {
  48                 compatible = "ti,am654-secure-proxy";
  49                 #mbox-cells = <1>;
  50                 reg-names = "target_data", "rt", "scfg";
  51                 reg = <0x00 0x43600000 0x00 0x10000>,
  52                       <0x00 0x44880000 0x00 0x20000>,
  53                       <0x00 0x44860000 0x00 0x20000>;
  54                 /*
  55                  * Marked Disabled:
  56                  * Node is incomplete as it is meant for bootloaders and
  57                  * firmware on non-MPU processors
  58                  */
  59                 status = "disabled";
  60         };
  61
  62         mcu_ram: sram@41c00000 {
  63                 compatible = "mmio-sram";
  64                 reg = <0x00 0x41c00000 0x00 0x100000>;
  65                 ranges = <0x00 0x00 0x41c00000 0x100000>;
  66                 #address-cells = <1>;
  67                 #size-cells = <1>;
  68         };
  69
  70         wkup_pmx0: pinctrl@4301c000 {
  71                 compatible = "pinctrl-single";
  72                 /* Proxy 0 addressing */
  73                 reg = <0x00 0x4301c000 0x00 0x034>;
  74                 #pinctrl-cells = <1>;
  75                 pinctrl-single,register-width = <32>;
  76                 pinctrl-single,function-mask = <0xffffffff>;
  77         };
  78
  79         wkup_pmx1: pinctrl@4301c038 {
  80                 compatible = "pinctrl-single";
  81                 /* Proxy 0 addressing */
  82                 reg = <0x00 0x4301c038 0x00 0x02c>;
  83                 #pinctrl-cells = <1>;
  84                 pinctrl-single,register-width = <32>;
  85                 pinctrl-single,function-mask = <0xffffffff>;
  86         };
  87
  88         wkup_pmx2: pinctrl@4301c068 {
  89                 compatible = "pinctrl-single";
  90                 /* Proxy 0 addressing */
  91                 reg = <0x00 0x4301c068 0x00 0x120>;
  92                 #pinctrl-cells = <1>;
  93                 pinctrl-single,register-width = <32>;
  94                 pinctrl-single,function-mask = <0xffffffff>;
  95         };
  96
  97         wkup_pmx3: pinctrl@4301c190 {
  98                 compatible = "pinctrl-single";
  99                 /* Proxy 0 addressing */
 100                 reg = <0x00 0x4301c190 0x00 0x004>;
 101                 #pinctrl-cells = <1>;
 102                 pinctrl-single,register-width = <32>;
 103                 pinctrl-single,function-mask = <0xffffffff>;
 104         };
 105
 106         wkup_gpio_intr: interrupt-controller@42200000 {
 107                 compatible = "ti,sci-intr";
 108                 reg = <0x00 0x42200000 0x00 0x400>;
 109                 ti,intr-trigger-type = <1>;
 110                 interrupt-controller;
 111                 interrupt-parent = <&gic500>;
 112                 #interrupt-cells = <1>;
 113                 ti,sci = <&sms>;
 114                 ti,sci-dev-id = <177>;
 115                 ti,interrupt-ranges = <16 960 16>;
 116         };
 117
 118         /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
 119         mcu_timerio_input: pinctrl@40f04200 {
 120                 compatible = "pinctrl-single";
 121                 reg = <0x00 0x40f04200 0x00 0x28>;
 122                 #pinctrl-cells = <1>;
 123                 pinctrl-single,register-width = <32>;
 124                 pinctrl-single,function-mask = <0x0000000f>;
 125                 /* Non-MPU Firmware usage */
 126                 status = "reserved";
 127         };
 128
 129         /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
 130         mcu_timerio_output: pinctrl@40f04280 {
 131                 compatible = "pinctrl-single";
 132                 reg = <0x00 0x40f04280 0x00 0x28>;
 133                 #pinctrl-cells = <1>;
 134                 pinctrl-single,register-width = <32>;
 135                 pinctrl-single,function-mask = <0x0000000f>;
 136                 /* Non-MPU Firmware usage */
 137                 status = "reserved";
 138         };
 139
 140         mcu_conf: syscon@40f00000 {
 141                 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
 142                 reg = <0x00 0x40f00000 0x00 0x20000>;
 143                 #address-cells = <1>;
 144                 #size-cells = <1>;
 145                 ranges = <0x00 0x00 0x40f00000 0x20000>;
 146
 147                 phy_gmii_sel: phy@4040 {
 148                         compatible = "ti,am654-phy-gmii-sel";
 149                         reg = <0x4040 0x4>;
 150                         #phy-cells = <1>;
 151                 };
 152         };
 153
 154         mcu_timer0: timer@40400000 {
 155                 compatible = "ti,am654-timer";
 156                 reg = <0x00 0x40400000 0x00 0x400>;
 157                 interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
 158                 clocks = <&k3_clks 35 2>;
 159                 clock-names = "fck";
 160                 assigned-clocks = <&k3_clks 35 2>;
 161                 assigned-clock-parents = <&k3_clks 35 3>;
 162                 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
 163                 ti,timer-pwm;
 164                 /* Non-MPU Firmware usage */
 165                 status = "reserved";
 166         };
 167
 168         mcu_timer1: timer@40410000 {
 169                 bootph-all;
 170                 compatible = "ti,am654-timer";
 171                 reg = <0x00 0x40410000 0x00 0x400>;
 172                 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
 173                 clocks = <&k3_clks 117 2>;
 174                 clock-names = "fck";
 175                 assigned-clocks = <&k3_clks 117 2>;
 176                 assigned-clock-parents = <&k3_clks 117 3>;
 177                 power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
 178                 ti,timer-pwm;
 179                 /* Non-MPU Firmware usage */
 180                 status = "reserved";
 181         };
 182
 183         mcu_timer2: timer@40420000 {
 184                 compatible = "ti,am654-timer";
 185                 reg = <0x00 0x40420000 0x00 0x400>;
 186                 interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>;
 187                 clocks = <&k3_clks 118 2>;
 188                 clock-names = "fck";
 189                 assigned-clocks = <&k3_clks 118 2>;
 190                 assigned-clock-parents = <&k3_clks 118 3>;
 191                 power-domains = <&k3_pds 118 TI_SCI_PD_EXCLUSIVE>;
 192                 ti,timer-pwm;
 193                 /* Non-MPU Firmware usage */
 194                 status = "reserved";
 195         };
 196
 197         mcu_timer3: timer@40430000 {
 198                 compatible = "ti,am654-timer";
 199                 reg = <0x00 0x40430000 0x00 0x400>;
 200                 interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>;
 201                 clocks = <&k3_clks 119 2>;
 202                 clock-names = "fck";
 203                 assigned-clocks = <&k3_clks 119 2>;
 204                 assigned-clock-parents = <&k3_clks 119 3>;
 205                 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
 206                 ti,timer-pwm;
 207                 /* Non-MPU Firmware usage */
 208                 status = "reserved";
 209         };
 210
 211         mcu_timer4: timer@40440000 {
 212                 compatible = "ti,am654-timer";
 213                 reg = <0x00 0x40440000 0x00 0x400>;
 214                 interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>;
 215                 clocks = <&k3_clks 120 2>;
 216                 clock-names = "fck";
 217                 assigned-clocks = <&k3_clks 120 2>;
 218                 assigned-clock-parents = <&k3_clks 120 3>;
 219                 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
 220                 ti,timer-pwm;
 221                 /* Non-MPU Firmware usage */
 222                 status = "reserved";
 223         };
 224
 225         mcu_timer5: timer@40450000 {
 226                 compatible = "ti,am654-timer";
 227                 reg = <0x00 0x40450000 0x00 0x400>;
 228                 interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>;
 229                 clocks = <&k3_clks 121 2>;
 230                 clock-names = "fck";
 231                 assigned-clocks = <&k3_clks 121 2>;
 232                 assigned-clock-parents = <&k3_clks 121 3>;
 233                 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
 234                 ti,timer-pwm;
 235                 /* Non-MPU Firmware usage */
 236                 status = "reserved";
 237         };
 238
 239         mcu_timer6: timer@40460000 {
 240                 compatible = "ti,am654-timer";
 241                 reg = <0x00 0x40460000 0x00 0x400>;
 242                 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
 243                 clocks = <&k3_clks 122 2>;
 244                 clock-names = "fck";
 245                 assigned-clocks = <&k3_clks 122 2>;
 246                 assigned-clock-parents = <&k3_clks 122 3>;
 247                 power-domains = <&k3_pds 122 TI_SCI_PD_EXCLUSIVE>;
 248                 ti,timer-pwm;
 249                 /* Non-MPU Firmware usage */
 250                 status = "reserved";
 251         };
 252
 253         mcu_timer7: timer@40470000 {
 254                 compatible = "ti,am654-timer";
 255                 reg = <0x00 0x40470000 0x00 0x400>;
 256                 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
 257                 clocks = <&k3_clks 123 2>;
 258                 clock-names = "fck";
 259                 assigned-clocks = <&k3_clks 123 2>;
 260                 assigned-clock-parents = <&k3_clks 123 3>;
 261                 power-domains = <&k3_pds 123 TI_SCI_PD_EXCLUSIVE>;
 262                 ti,timer-pwm;
 263                 /* Non-MPU Firmware usage */
 264                 status = "reserved";
 265         };
 266
 267         mcu_timer8: timer@40480000 {
 268                 compatible = "ti,am654-timer";
 269                 reg = <0x00 0x40480000 0x00 0x400>;
 270                 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
 271                 clocks = <&k3_clks 124 2>;
 272                 clock-names = "fck";
 273                 assigned-clocks = <&k3_clks 124 2>;
 274                 assigned-clock-parents = <&k3_clks 124 3>;
 275                 power-domains = <&k3_pds 124 TI_SCI_PD_EXCLUSIVE>;
 276                 ti,timer-pwm;
 277                 /* Non-MPU Firmware usage */
 278                 status = "reserved";
 279         };
 280
 281         mcu_timer9: timer@40490000 {
 282                 compatible = "ti,am654-timer";
 283                 reg = <0x00 0x40490000 0x00 0x400>;
 284                 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
 285                 clocks = <&k3_clks 125 2>;
 286                 clock-names = "fck";
 287                 assigned-clocks = <&k3_clks 125 2>;
 288                 assigned-clock-parents = <&k3_clks 125 3>;
 289                 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
 290                 ti,timer-pwm;
 291                 /* Non-MPU Firmware usage */
 292                 status = "reserved";
 293         };
 294
 295         wkup_uart0: serial@42300000 {
 296                 compatible = "ti,j721e-uart", "ti,am654-uart";
 297                 reg = <0x00 0x42300000 0x00 0x200>;
 298                 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
 299                 current-speed = <115200>;
 300                 clocks = <&k3_clks 397 0>;
 301                 clock-names = "fclk";
 302                 power-domains = <&k3_pds 397 TI_SCI_PD_EXCLUSIVE>;
 303                 status = "disabled";
 304         };
 305
 306         mcu_uart0: serial@40a00000 {
 307                 compatible = "ti,j721e-uart", "ti,am654-uart";
 308                 reg = <0x00 0x40a00000 0x00 0x200>;
 309                 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
 310                 current-speed = <115200>;
 311                 clocks = <&k3_clks 149 0>;
 312                 clock-names = "fclk";
 313                 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
 314                 status = "disabled";
 315         };
 316
 317         wkup_gpio0: gpio@42110000 {
 318                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 319                 reg = <0x00 0x42110000 0x00 0x100>;
 320                 gpio-controller;
 321                 #gpio-cells = <2>;
 322                 interrupt-parent = <&wkup_gpio_intr>;
 323                 interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
 324                 interrupt-controller;
 325                 #interrupt-cells = <2>;
 326                 ti,ngpio = <89>;
 327                 ti,davinci-gpio-unbanked = <0>;
 328                 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
 329                 clocks = <&k3_clks 167 0>;
 330                 clock-names = "gpio";
 331                 status = "disabled";
 332         };
 333
 334         wkup_gpio1: gpio@42100000 {
 335                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 336                 reg = <0x00 0x42100000 0x00 0x100>;
 337                 gpio-controller;
 338                 #gpio-cells = <2>;
 339                 interrupt-parent = <&wkup_gpio_intr>;
 340                 interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
 341                 interrupt-controller;
 342                 #interrupt-cells = <2>;
 343                 ti,ngpio = <89>;
 344                 ti,davinci-gpio-unbanked = <0>;
 345                 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
 346                 clocks = <&k3_clks 168 0>;
 347                 clock-names = "gpio";
 348                 status = "disabled";
 349         };
 350
 351         wkup_i2c0: i2c@42120000 {
 352                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 353                 reg = <0x00 0x42120000 0x00 0x100>;
 354                 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
 355                 #address-cells = <1>;
 356                 #size-cells = <0>;
 357                 clocks = <&k3_clks 279 2>;
 358                 clock-names = "fck";
 359                 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
 360                 status = "disabled";
 361         };
 362
 363         mcu_i2c0: i2c@40b00000 {
 364                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 365                 reg = <0x00 0x40b00000 0x00 0x100>;
 366                 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
 367                 #address-cells = <1>;
 368                 #size-cells = <0>;
 369                 clocks = <&k3_clks 277 2>;
 370                 clock-names = "fck";
 371                 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
 372                 status = "disabled";
 373         };
 374
 375         mcu_i2c1: i2c@40b10000 {
 376                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 377                 reg = <0x00 0x40b10000 0x00 0x100>;
 378                 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
 379                 #address-cells = <1>;
 380                 #size-cells = <0>;
 381                 clocks = <&k3_clks 278 2>;
 382                 clock-names = "fck";
 383                 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
 384                 status = "disabled";
 385         };
 386
 387         mcu_mcan0: can@40528000 {
 388                 compatible = "bosch,m_can";
 389                 reg = <0x00 0x40528000 0x00 0x200>,
 390                       <0x00 0x40500000 0x00 0x8000>;
 391                 reg-names = "m_can", "message_ram";
 392                 power-domains = <&k3_pds 263 TI_SCI_PD_EXCLUSIVE>;
 393                 clocks = <&k3_clks 263 6>, <&k3_clks 263 1>;
 394                 clock-names = "hclk", "cclk";
 395                 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
 396                              <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
 397                 interrupt-names = "int0", "int1";
 398                 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
 399                 status = "disabled";
 400         };
 401
 402         mcu_mcan1: can@40568000 {
 403                 compatible = "bosch,m_can";
 404                 reg = <0x00 0x40568000 0x00 0x200>,
 405                       <0x00 0x40540000 0x00 0x8000>;
 406                 reg-names = "m_can", "message_ram";
 407                 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
 408                 clocks = <&k3_clks 264 6>, <&k3_clks 264 1>;
 409                 clock-names = "hclk", "cclk";
 410                 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
 411                              <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
 412                 interrupt-names = "int0", "int1";
 413                 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
 414                 status = "disabled";
 415         };
 416
 417         mcu_spi0: spi@40300000 {
 418                 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
 419                 reg = <0x00 0x040300000 0x00 0x400>;
 420                 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
 421                 #address-cells = <1>;
 422                 #size-cells = <0>;
 423                 power-domains = <&k3_pds 384 TI_SCI_PD_EXCLUSIVE>;
 424                 clocks = <&k3_clks 384 0>;
 425                 status = "disabled";
 426         };
 427
 428         mcu_spi1: spi@40310000 {
 429                 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
 430                 reg = <0x00 0x040310000 0x00 0x400>;
 431                 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
 432                 #address-cells = <1>;
 433                 #size-cells = <0>;
 434                 power-domains = <&k3_pds 385 TI_SCI_PD_EXCLUSIVE>;
 435                 clocks = <&k3_clks 385 0>;
 436                 status = "disabled";
 437         };
 438
 439         mcu_spi2: spi@40320000 {
 440                 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
 441                 reg = <0x00 0x040320000 0x00 0x400>;
 442                 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
 443                 #address-cells = <1>;
 444                 #size-cells = <0>;
 445                 power-domains = <&k3_pds 386 TI_SCI_PD_EXCLUSIVE>;
 446                 clocks = <&k3_clks 386 0>;
 447                 status = "disabled";
 448         };
 449
 450         mcu_navss: bus@28380000 {
 451                 bootph-all;
 452                 compatible = "simple-bus";
 453                 #address-cells = <2>;
 454                 #size-cells = <2>;
 455                 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
 456                 ti,sci-dev-id = <323>;
 457                 dma-coherent;
 458                 dma-ranges;
 459
 460                 mcu_ringacc: ringacc@2b800000 {
 461                         bootph-all;
 462                         compatible = "ti,am654-navss-ringacc";
 463                         reg = <0x00 0x2b800000 0x00 0x400000>,
 464                               <0x00 0x2b000000 0x00 0x400000>,
 465                               <0x00 0x28590000 0x00 0x100>,
 466                               <0x00 0x2a500000 0x00 0x40000>,
 467                               <0x00 0x28440000 0x00 0x40000>;
 468                         reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
 469                         ti,num-rings = <286>;
 470                         ti,sci-rm-range-gp-rings = <0x1>;
 471                         ti,sci = <&sms>;
 472                         ti,sci-dev-id = <328>;
 473                         msi-parent = <&main_udmass_inta>;
 474                 };
 475
 476                 mcu_udmap: dma-controller@285c0000 {
 477                         bootph-all;
 478                         compatible = "ti,j721e-navss-mcu-udmap";
 479                         reg = <0x00 0x285c0000 0x00 0x100>,
 480                               <0x00 0x2a800000 0x00 0x40000>,
 481                               <0x00 0x2aa00000 0x00 0x40000>;
 482                         reg-names = "gcfg", "rchanrt", "tchanrt";
 483                         msi-parent = <&main_udmass_inta>;
 484                         #dma-cells = <1>;
 485
 486                         ti,sci = <&sms>;
 487                         ti,sci-dev-id = <329>;
 488                         ti,ringacc = <&mcu_ringacc>;
 489                         ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
 490                                                 <0x0f>; /* TX_HCHAN */
 491                         ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
 492                                                 <0x0b>; /* RX_HCHAN */
 493                         ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
 494                 };
 495         };
 496
 497         secure_proxy_mcu: mailbox@2a480000 {
 498                 compatible = "ti,am654-secure-proxy";
 499                 #mbox-cells = <1>;
 500                 reg-names = "target_data", "rt", "scfg";
 501                 reg = <0x00 0x2a480000 0x00 0x80000>,
 502                       <0x00 0x2a380000 0x00 0x80000>,
 503                       <0x00 0x2a400000 0x00 0x80000>;
 504                 /*
 505                  * Marked Disabled:
 506                  * Node is incomplete as it is meant for bootloaders and
 507                  * firmware on non-MPU processors
 508                  */
 509                 status = "disabled";
 510         };
 511
 512         mcu_cpsw: ethernet@46000000 {
 513                 compatible = "ti,j721e-cpsw-nuss";
 514                 #address-cells = <2>;
 515                 #size-cells = <2>;
 516                 reg = <0x00 0x46000000 0x00 0x200000>;
 517                 reg-names = "cpsw_nuss";
 518                 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
 519                 dma-coherent;
 520                 clocks = <&k3_clks 63 0>;
 521                 clock-names = "fck";
 522                 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
 523
 524                 dmas = <&mcu_udmap 0xf000>,
 525                        <&mcu_udmap 0xf001>,
 526                        <&mcu_udmap 0xf002>,
 527                        <&mcu_udmap 0xf003>,
 528                        <&mcu_udmap 0xf004>,
 529                        <&mcu_udmap 0xf005>,
 530                        <&mcu_udmap 0xf006>,
 531                        <&mcu_udmap 0xf007>,
 532                        <&mcu_udmap 0x7000>;
 533                 dma-names = "tx0", "tx1", "tx2", "tx3",
 534                             "tx4", "tx5", "tx6", "tx7",
 535                             "rx";
 536                 status = "disabled";
 537
 538                 ethernet-ports {
 539                         #address-cells = <1>;
 540                         #size-cells = <0>;
 541
 542                         mcu_cpsw_port1: port@1 {
 543                                 reg = <1>;
 544                                 ti,mac-only;
 545                                 label = "port1";
 546                                 ti,syscon-efuse = <&mcu_conf 0x200>;
 547                                 phys = <&phy_gmii_sel 1>;
 548                         };
 549                 };
 550
 551                 davinci_mdio: mdio@f00 {
 552                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
 553                         reg = <0x00 0xf00 0x00 0x100>;
 554                         #address-cells = <1>;
 555                         #size-cells = <0>;
 556                         clocks = <&k3_clks 63 0>;
 557                         clock-names = "fck";
 558                         bus_freq = <1000000>;
 559                 };
 560
 561                 cpts@3d000 {
 562                         compatible = "ti,am65-cpts";
 563                         reg = <0x00 0x3d000 0x00 0x400>;
 564                         clocks = <&k3_clks 63 3>;
 565                         clock-names = "cpts";
 566                         assigned-clocks = <&k3_clks 63 3>; /* CPTS_RFT_CLK */
 567                         assigned-clock-parents = <&k3_clks 63 5>; /* MAIN_0_HSDIV6_CLK */
 568                         interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
 569                         interrupt-names = "cpts";
 570                         ti,cpts-ext-ts-inputs = <4>;
 571                         ti,cpts-periodic-outputs = <2>;
 572                 };
 573         };
 574
 575         mcu_r5fss0: r5fss@41000000 {
 576                 compatible = "ti,j721s2-r5fss";
 577                 ti,cluster-mode = <1>;
 578                 #address-cells = <1>;
 579                 #size-cells = <1>;
 580                 ranges = <0x41000000 0x00 0x41000000 0x20000>,
 581                          <0x41400000 0x00 0x41400000 0x20000>;
 582                 power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>;
 583
 584                 mcu_r5fss0_core0: r5f@41000000 {
 585                         compatible = "ti,j721s2-r5f";
 586                         reg = <0x41000000 0x00010000>,
 587                               <0x41010000 0x00010000>;
 588                         reg-names = "atcm", "btcm";
 589                         ti,sci = <&sms>;
 590                         ti,sci-dev-id = <346>;
 591                         ti,sci-proc-ids = <0x01 0xff>;
 592                         resets = <&k3_reset 346 1>;
 593                         firmware-name = "j784s4-mcu-r5f0_0-fw";
 594                         ti,atcm-enable = <1>;
 595                         ti,btcm-enable = <1>;
 596                         ti,loczrama = <1>;
 597                 };
 598
 599                 mcu_r5fss0_core1: r5f@41400000 {
 600                         compatible = "ti,j721s2-r5f";
 601                         reg = <0x41400000 0x00010000>,
 602                               <0x41410000 0x00010000>;
 603                         reg-names = "atcm", "btcm";
 604                         ti,sci = <&sms>;
 605                         ti,sci-dev-id = <347>;
 606                         ti,sci-proc-ids = <0x02 0xff>;
 607                         resets = <&k3_reset 347 1>;
 608                         firmware-name = "j784s4-mcu-r5f0_1-fw";
 609                         ti,atcm-enable = <1>;
 610                         ti,btcm-enable = <1>;
 611                         ti,loczrama = <1>;
 612                 };
 613         };
 614
 615         wkup_vtm0: temperature-sensor@42040000 {
 616                 compatible = "ti,j7200-vtm";
 617                 reg = <0x00 0x42040000 0x00 0x350>,
 618                       <0x00 0x42050000 0x00 0x350>;
 619                 power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>;
 620                 #thermal-sensor-cells = <1>;
 621         };
 622
 623         tscadc0: tscadc@40200000 {
 624                 compatible = "ti,am3359-tscadc";
 625                 reg = <0x00 0x40200000 0x00 0x1000>;
 626                 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
 627                 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
 628                 clocks = <&k3_clks 0 0>;
 629                 assigned-clocks = <&k3_clks 0 2>;
 630                 assigned-clock-rates = <60000000>;
 631                 clock-names = "fck";
 632                 dmas = <&main_udmap 0x7400>,
 633                         <&main_udmap 0x7401>;
 634                 dma-names = "fifo0", "fifo1";
 635                 status = "disabled";
 636
 637                 adc {
 638                         #io-channel-cells = <1>;
 639                         compatible = "ti,am3359-adc";
 640                 };
 641         };
 642
 643         tscadc1: tscadc@40210000 {
 644                 compatible = "ti,am3359-tscadc";
 645                 reg = <0x00 0x40210000 0x00 0x1000>;
 646                 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
 647                 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
 648                 clocks = <&k3_clks 1 0>;
 649                 assigned-clocks = <&k3_clks 1 2>;
 650                 assigned-clock-rates = <60000000>;
 651                 clock-names = "fck";
 652                 dmas = <&main_udmap 0x7402>,
 653                         <&main_udmap 0x7403>;
 654                 dma-names = "fifo0", "fifo1";
 655                 status = "disabled";
 656
 657                 adc {
 658                         #io-channel-cells = <1>;
 659                         compatible = "ti,am3359-adc";
 660                 };
 661         };
 662
 663         fss: bus@47000000 {
 664                 compatible = "simple-bus";
 665                 reg = <0x00 0x47000000 0x00 0x100>;
 666                 #address-cells = <2>;
 667                 #size-cells = <2>;
 668                 ranges;
 669
 670                 ospi0: spi@47040000 {
 671                         compatible = "ti,am654-ospi", "cdns,qspi-nor";
 672                         reg = <0x00 0x47040000 0x00 0x100>,
 673                               <0x05 0x0000000 0x01 0x0000000>;
 674                         interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
 675                         cdns,fifo-depth = <256>;
 676                         cdns,fifo-width = <4>;
 677                         cdns,trigger-address = <0x0>;
 678                         clocks = <&k3_clks 161 7>;
 679                         assigned-clocks = <&k3_clks 161 7>;
 680                         assigned-clock-parents = <&k3_clks 161 9>;
 681                         assigned-clock-rates = <166666666>;
 682                         power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
 683                         #address-cells = <1>;
 684                         #size-cells = <0>;
 685                         status = "disabled";
 686                 };
 687
 688                 ospi1: spi@47050000 {
 689                         compatible = "ti,am654-ospi", "cdns,qspi-nor";
 690                         reg = <0x00 0x47050000 0x00 0x100>,
 691                               <0x07 0x0000000 0x01 0x0000000>;
 692                         interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
 693                         cdns,fifo-depth = <256>;
 694                         cdns,fifo-width = <4>;
 695                         cdns,trigger-address = <0x0>;
 696                         clocks = <&k3_clks 162 7>;
 697                         power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
 698                         #address-cells = <1>;
 699                         #size-cells = <0>;
 700                         status = "disabled";
 701                 };
 702         };
 703
 704         mcu_esm: esm@40800000 {
 705                 compatible = "ti,j721e-esm";
 706                 reg = <0x00 0x40800000 0x00 0x1000>;
 707                 ti,esm-pins = <95>;
 708                 bootph-pre-ram;
 709         };
 710
 711         wkup_esm: esm@42080000 {
 712                 compatible = "ti,j721e-esm";
 713                 reg = <0x00 0x42080000 0x00 0x1000>;
 714                 ti,esm-pins = <63>;
 715                 bootph-pre-ram;
 716         };
 717
 718         /*
 719          * The 2 RTI instances are couple with MCU R5Fs so keeping them
 720          * reserved as these will be used by their respective firmware
 721          */
 722         mcu_watchdog0: watchdog@40600000 {
 723                 compatible = "ti,j7-rti-wdt";
 724                 reg = <0x00 0x40600000 0x00 0x100>;
 725                 clocks = <&k3_clks 367 1>;
 726                 power-domains = <&k3_pds 367 TI_SCI_PD_EXCLUSIVE>;
 727                 assigned-clocks = <&k3_clks 367 0>;
 728                 assigned-clock-parents = <&k3_clks 367 4>;
 729                 /* reserved for MCU_R5F0_0 */
 730                 status = "reserved";
 731         };
 732
 733         mcu_watchdog1: watchdog@40610000 {
 734                 compatible = "ti,j7-rti-wdt";
 735                 reg = <0x00 0x40610000 0x00 0x100>;
 736                 clocks = <&k3_clks 368 1>;
 737                 power-domains = <&k3_pds 368 TI_SCI_PD_EXCLUSIVE>;
 738                 assigned-clocks = <&k3_clks 368 0>;
 739                 assigned-clock-parents = <&k3_clks 368 4>;
 740                 /* reserved for MCU_R5F0_1 */
 741                 status = "reserved";
 742         };
 743 };