arch/arm64/boot/dts/ti/k3-j784s4-evm.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
   4  *
   5  * EVM Board Schematics: https://www.ti.com/lit/zip/sprr458
   6  */
   7
   8 /dts-v1/;
   9
  10 #include <dt-bindings/net/ti-dp83867.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include "k3-j784s4.dtsi"
  13
  14 / {
  15         compatible = "ti,j784s4-evm", "ti,j784s4";
  16         model = "Texas Instruments J784S4 EVM";
  17
  18         chosen {
  19                 stdout-path = "serial2:115200n8";
  20         };
  21
  22         aliases {
  23                 serial0 = &wkup_uart0;
  24                 serial1 = &mcu_uart0;
  25                 serial2 = &main_uart8;
  26                 mmc0 = &main_sdhci0;
  27                 mmc1 = &main_sdhci1;
  28                 i2c0 = &wkup_i2c0;
  29                 i2c3 = &main_i2c0;
  30         };
  31
  32         memory@80000000 {
  33                 device_type = "memory";
  34                 /* 32G RAM */
  35                 reg = <0x00 0x80000000 0x00 0x80000000>,
  36                       <0x08 0x80000000 0x07 0x80000000>;
  37         };
  38
  39         reserved_memory: reserved-memory {
  40                 #address-cells = <2>;
  41                 #size-cells = <2>;
  42                 ranges;
  43
  44                 secure_ddr: optee@9e800000 {
  45                         reg = <0x00 0x9e800000 0x00 0x01800000>;
  46                         no-map;
  47                 };
  48
  49                 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
  50                         compatible = "shared-dma-pool";
  51                         reg = <0x00 0xa0000000 0x00 0x100000>;
  52                         no-map;
  53                 };
  54
  55                 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
  56                         compatible = "shared-dma-pool";
  57                         reg = <0x00 0xa0100000 0x00 0xf00000>;
  58                         no-map;
  59                 };
  60
  61                 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
  62                         compatible = "shared-dma-pool";
  63                         reg = <0x00 0xa1000000 0x00 0x100000>;
  64                         no-map;
  65                 };
  66
  67                 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
  68                         compatible = "shared-dma-pool";
  69                         reg = <0x00 0xa1100000 0x00 0xf00000>;
  70                         no-map;
  71                 };
  72
  73                 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
  74                         compatible = "shared-dma-pool";
  75                         reg = <0x00 0xa2000000 0x00 0x100000>;
  76                         no-map;
  77                 };
  78
  79                 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
  80                         compatible = "shared-dma-pool";
  81                         reg = <0x00 0xa2100000 0x00 0xf00000>;
  82                         no-map;
  83                 };
  84
  85                 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
  86                         compatible = "shared-dma-pool";
  87                         reg = <0x00 0xa3000000 0x00 0x100000>;
  88                         no-map;
  89                 };
  90
  91                 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
  92                         compatible = "shared-dma-pool";
  93                         reg = <0x00 0xa3100000 0x00 0xf00000>;
  94                         no-map;
  95                 };
  96
  97                 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
  98                         compatible = "shared-dma-pool";
  99                         reg = <0x00 0xa4000000 0x00 0x100000>;
 100                         no-map;
 101                 };
 102
 103                 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
 104                         compatible = "shared-dma-pool";
 105                         reg = <0x00 0xa4100000 0x00 0xf00000>;
 106                         no-map;
 107                 };
 108
 109                 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
 110                         compatible = "shared-dma-pool";
 111                         reg = <0x00 0xa5000000 0x00 0x100000>;
 112                         no-map;
 113                 };
 114
 115                 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
 116                         compatible = "shared-dma-pool";
 117                         reg = <0x00 0xa5100000 0x00 0xf00000>;
 118                         no-map;
 119                 };
 120
 121                 main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 {
 122                         compatible = "shared-dma-pool";
 123                         reg = <0x00 0xa6000000 0x00 0x100000>;
 124                         no-map;
 125                 };
 126
 127                 main_r5fss2_core0_memory_region: r5f-memory@a6100000 {
 128                         compatible = "shared-dma-pool";
 129                         reg = <0x00 0xa6100000 0x00 0xf00000>;
 130                         no-map;
 131                 };
 132
 133                 main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 {
 134                         compatible = "shared-dma-pool";
 135                         reg = <0x00 0xa7000000 0x00 0x100000>;
 136                         no-map;
 137                 };
 138
 139                 main_r5fss2_core1_memory_region: r5f-memory@a7100000 {
 140                         compatible = "shared-dma-pool";
 141                         reg = <0x00 0xa7100000 0x00 0xf00000>;
 142                         no-map;
 143                 };
 144
 145                 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
 146                         compatible = "shared-dma-pool";
 147                         reg = <0x00 0xa8000000 0x00 0x100000>;
 148                         no-map;
 149                 };
 150
 151                 c71_0_memory_region: c71-memory@a8100000 {
 152                         compatible = "shared-dma-pool";
 153                         reg = <0x00 0xa8100000 0x00 0xf00000>;
 154                         no-map;
 155                 };
 156
 157                 c71_1_dma_memory_region: c71-dma-memory@a9000000 {
 158                         compatible = "shared-dma-pool";
 159                         reg = <0x00 0xa9000000 0x00 0x100000>;
 160                         no-map;
 161                 };
 162
 163                 c71_1_memory_region: c71-memory@a9100000 {
 164                         compatible = "shared-dma-pool";
 165                         reg = <0x00 0xa9100000 0x00 0xf00000>;
 166                         no-map;
 167                 };
 168
 169                 c71_2_dma_memory_region: c71-dma-memory@aa000000 {
 170                         compatible = "shared-dma-pool";
 171                         reg = <0x00 0xaa000000 0x00 0x100000>;
 172                         no-map;
 173                 };
 174
 175                 c71_2_memory_region: c71-memory@aa100000 {
 176                         compatible = "shared-dma-pool";
 177                         reg = <0x00 0xaa100000 0x00 0xf00000>;
 178                         no-map;
 179                 };
 180
 181                 c71_3_dma_memory_region: c71-dma-memory@ab000000 {
 182                         compatible = "shared-dma-pool";
 183                         reg = <0x00 0xab000000 0x00 0x100000>;
 184                         no-map;
 185                 };
 186
 187                 c71_3_memory_region: c71-memory@ab100000 {
 188                         compatible = "shared-dma-pool";
 189                         reg = <0x00 0xab100000 0x00 0xf00000>;
 190                         no-map;
 191                 };
 192         };
 193
 194         evm_12v0: regulator-evm12v0 {
 195                 /* main supply */
 196                 compatible = "regulator-fixed";
 197                 regulator-name = "evm_12v0";
 198                 regulator-min-microvolt = <12000000>;
 199                 regulator-max-microvolt = <12000000>;
 200                 regulator-always-on;
 201                 regulator-boot-on;
 202         };
 203
 204         vsys_3v3: regulator-vsys3v3 {
 205                 /* Output of LM5140 */
 206                 compatible = "regulator-fixed";
 207                 regulator-name = "vsys_3v3";
 208                 regulator-min-microvolt = <3300000>;
 209                 regulator-max-microvolt = <3300000>;
 210                 vin-supply = <&evm_12v0>;
 211                 regulator-always-on;
 212                 regulator-boot-on;
 213         };
 214
 215         vsys_5v0: regulator-vsys5v0 {
 216                 /* Output of LM5140 */
 217                 compatible = "regulator-fixed";
 218                 regulator-name = "vsys_5v0";
 219                 regulator-min-microvolt = <5000000>;
 220                 regulator-max-microvolt = <5000000>;
 221                 vin-supply = <&evm_12v0>;
 222                 regulator-always-on;
 223                 regulator-boot-on;
 224         };
 225
 226         vdd_mmc1: regulator-sd {
 227                 /* Output of TPS22918 */
 228                 compatible = "regulator-fixed";
 229                 regulator-name = "vdd_mmc1";
 230                 regulator-min-microvolt = <3300000>;
 231                 regulator-max-microvolt = <3300000>;
 232                 regulator-boot-on;
 233                 enable-active-high;
 234                 vin-supply = <&vsys_3v3>;
 235                 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
 236         };
 237
 238         vdd_sd_dv: regulator-TLV71033 {
 239                 /* Output of TLV71033 */
 240                 compatible = "regulator-gpio";
 241                 regulator-name = "tlv71033";
 242                 pinctrl-names = "default";
 243                 pinctrl-0 = <&vdd_sd_dv_pins_default>;
 244                 regulator-min-microvolt = <1800000>;
 245                 regulator-max-microvolt = <3300000>;
 246                 regulator-boot-on;
 247                 vin-supply = <&vsys_5v0>;
 248                 gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>;
 249                 states = <1800000 0x0>,
 250                          <3300000 0x1>;
 251         };
 252
 253         dp0_pwr_3v3: regulator-dp0-prw {
 254                 compatible = "regulator-fixed";
 255                 regulator-name = "dp0-pwr";
 256                 regulator-min-microvolt = <3300000>;
 257                 regulator-max-microvolt = <3300000>;
 258                 gpio = <&exp4 0 GPIO_ACTIVE_HIGH>;
 259                 enable-active-high;
 260         };
 261
 262         dp0: connector-dp0 {
 263                 compatible = "dp-connector";
 264                 label = "DP0";
 265                 type = "full-size";
 266                 dp-pwr-supply = <&dp0_pwr_3v3>;
 267
 268                 port {
 269                         dp0_connector_in: endpoint {
 270                                 remote-endpoint = <&dp0_out>;
 271                         };
 272                 };
 273         };
 274 };
 275
 276 &main_pmx0 {
 277         bootph-all;
 278         main_uart8_pins_default: main-uart8-default-pins {
 279                 bootph-all;
 280                 pinctrl-single,pins = <
 281                         J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */
 282                         J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */
 283                         J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */
 284                         J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */
 285                 >;
 286         };
 287
 288         main_i2c0_pins_default: main-i2c0-default-pins {
 289                 pinctrl-single,pins = <
 290                         J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */
 291                         J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */
 292                 >;
 293         };
 294
 295         main_mmc1_pins_default: main-mmc1-default-pins {
 296                 bootph-all;
 297                 pinctrl-single,pins = <
 298                         J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */
 299                         J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */
 300                         J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */
 301                         J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */
 302                         J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */
 303                         J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */
 304                         J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */
 305                         J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */
 306                 >;
 307         };
 308
 309         vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
 310                 pinctrl-single,pins = <
 311                         J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */
 312                 >;
 313         };
 314
 315         dp0_pins_default: dp0-default-pins {
 316                 pinctrl-single,pins = <
 317                         J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */
 318                 >;
 319         };
 320
 321         main_i2c4_pins_default: main-i2c4-default-pins {
 322                 pinctrl-single,pins = <
 323                         J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */
 324                         J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */
 325                 >;
 326         };
 327 };
 328
 329 &wkup_pmx2 {
 330         bootph-all;
 331         wkup_uart0_pins_default: wkup-uart0-default-pins {
 332                 bootph-all;
 333                 pinctrl-single,pins = <
 334                         J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */
 335                         J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */
 336                         J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */
 337                         J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */
 338                 >;
 339         };
 340
 341         wkup_i2c0_pins_default: wkup-i2c0-default-pins {
 342                 bootph-all;
 343                 pinctrl-single,pins = <
 344                         J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */
 345                         J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */
 346                 >;
 347         };
 348
 349         mcu_uart0_pins_default: mcu-uart0-default-pins {
 350                 bootph-all;
 351                 pinctrl-single,pins = <
 352                         J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */
 353                         J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */
 354                         J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */
 355                         J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */
 356                 >;
 357         };
 358
 359         mcu_cpsw_pins_default: mcu-cpsw-default-pins {
 360                 pinctrl-single,pins = <
 361                         J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */
 362                         J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */
 363                         J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */
 364                         J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */
 365                         J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */
 366                         J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */
 367                         J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */
 368                         J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */
 369                         J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */
 370                         J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */
 371                         J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */
 372                         J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */
 373                 >;
 374         };
 375
 376         mcu_mdio_pins_default: mcu-mdio-default-pins {
 377                 pinctrl-single,pins = <
 378                         J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */
 379                         J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */
 380                 >;
 381         };
 382
 383         mcu_adc0_pins_default: mcu-adc0-default-pins {
 384                 pinctrl-single,pins = <
 385                         J784S4_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */
 386                         J784S4_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */
 387                         J784S4_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */
 388                         J784S4_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */
 389                         J784S4_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */
 390                         J784S4_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */
 391                         J784S4_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */
 392                         J784S4_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */
 393                 >;
 394         };
 395
 396         mcu_adc1_pins_default: mcu-adc1-default-pins {
 397                 pinctrl-single,pins = <
 398                         J784S4_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */
 399                         J784S4_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */
 400                         J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */
 401                         J784S4_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */
 402                         J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */
 403                         J784S4_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */
 404                         J784S4_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */
 405                         J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */
 406                 >;
 407         };
 408 };
 409
 410 &wkup_pmx0 {
 411         bootph-all;
 412         mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
 413                 bootph-all;
 414                 pinctrl-single,pins = <
 415                         J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */
 416                         J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */
 417                         J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */
 418                         J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */
 419                         J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */
 420                         J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */
 421                         J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */
 422                         J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */
 423                         J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */
 424                         J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */
 425                         J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */
 426                 >;
 427         };
 428 };
 429
 430 &wkup_pmx1 {
 431         bootph-all;
 432         mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins {
 433                 bootph-all;
 434                 pinctrl-single,pins = <
 435                         J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */
 436                         J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */
 437                 >;
 438         };
 439
 440         mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins {
 441                 bootph-all;
 442                 pinctrl-single,pins = <
 443                         J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */
 444                         J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */
 445                         J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */
 446                         J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */
 447                         J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */
 448                         J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */
 449                         J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */
 450                         J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */
 451                 >;
 452         };
 453 };
 454
 455 &wkup_uart0 {
 456         /* Firmware usage */
 457         status = "reserved";
 458         pinctrl-names = "default";
 459         pinctrl-0 = <&wkup_uart0_pins_default>;
 460 };
 461
 462 &wkup_i2c0 {
 463         bootph-all;
 464         status = "okay";
 465         pinctrl-names = "default";
 466         pinctrl-0 = <&wkup_i2c0_pins_default>;
 467         clock-frequency = <400000>;
 468
 469         eeprom@50 {
 470                 /* CAV24C256WE-GT3 */
 471                 compatible = "atmel,24c256";
 472                 reg = <0x50>;
 473         };
 474 };
 475
 476 &mcu_uart0 {
 477         bootph-all;
 478         status = "okay";
 479         pinctrl-names = "default";
 480         pinctrl-0 = <&mcu_uart0_pins_default>;
 481 };
 482
 483 &main_uart8 {
 484         bootph-all;
 485         status = "okay";
 486         pinctrl-names = "default";
 487         pinctrl-0 = <&main_uart8_pins_default>;
 488 };
 489
 490 &ufs_wrapper {
 491         status = "okay";
 492 };
 493
 494 &fss {
 495         bootph-all;
 496         status = "okay";
 497 };
 498
 499 &ospi0 {
 500         bootph-all;
 501         status = "okay";
 502         pinctrl-names = "default";
 503         pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>;
 504
 505         flash@0 {
 506                 bootph-all;
 507                 compatible = "jedec,spi-nor";
 508                 reg = <0x0>;
 509                 spi-tx-bus-width = <8>;
 510                 spi-rx-bus-width = <8>;
 511                 spi-max-frequency = <25000000>;
 512                 cdns,tshsl-ns = <60>;
 513                 cdns,tsd2d-ns = <60>;
 514                 cdns,tchsh-ns = <60>;
 515                 cdns,tslch-ns = <60>;
 516                 cdns,read-delay = <4>;
 517
 518                 partitions {
 519                         compatible = "fixed-partitions";
 520                         #address-cells = <1>;
 521                         #size-cells = <1>;
 522
 523                         partition@0 {
 524                                 label = "ospi.tiboot3";
 525                                 reg = <0x0 0x80000>;
 526                         };
 527
 528                         partition@80000 {
 529                                 label = "ospi.tispl";
 530                                 reg = <0x80000 0x200000>;
 531                         };
 532
 533                         partition@280000 {
 534                                 label = "ospi.u-boot";
 535                                 reg = <0x280000 0x400000>;
 536                         };
 537
 538                         partition@680000 {
 539                                 label = "ospi.env";
 540                                 reg = <0x680000 0x40000>;
 541                         };
 542
 543                         partition@6c0000 {
 544                                 label = "ospi.env.backup";
 545                                 reg = <0x6c0000 0x40000>;
 546                         };
 547
 548                         partition@800000 {
 549                                 label = "ospi.rootfs";
 550                                 reg = <0x800000 0x37c0000>;
 551                         };
 552
 553                         partition@3fc0000 {
 554                                 bootph-all;
 555                                 label = "ospi.phypattern";
 556                                 reg = <0x3fc0000 0x40000>;
 557                         };
 558                 };
 559         };
 560 };
 561
 562 &ospi1 {
 563         bootph-all;
 564         status = "okay";
 565         pinctrl-names = "default";
 566         pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
 567
 568         flash@0 {
 569                 bootph-all;
 570                 compatible = "jedec,spi-nor";
 571                 reg = <0x0>;
 572                 spi-tx-bus-width = <1>;
 573                 spi-rx-bus-width = <4>;
 574                 spi-max-frequency = <40000000>;
 575                 cdns,tshsl-ns = <60>;
 576                 cdns,tsd2d-ns = <60>;
 577                 cdns,tchsh-ns = <60>;
 578                 cdns,tslch-ns = <60>;
 579                 cdns,read-delay = <2>;
 580
 581                 partitions {
 582                         compatible = "fixed-partitions";
 583                         #address-cells = <1>;
 584                         #size-cells = <1>;
 585
 586                         partition@0 {
 587                                 label = "qspi.tiboot3";
 588                                 reg = <0x0 0x80000>;
 589                         };
 590
 591                         partition@80000 {
 592                                 label = "qspi.tispl";
 593                                 reg = <0x80000 0x200000>;
 594                         };
 595
 596                         partition@280000 {
 597                                 label = "qspi.u-boot";
 598                                 reg = <0x280000 0x400000>;
 599                         };
 600
 601                         partition@680000 {
 602                                 label = "qspi.env";
 603                                 reg = <0x680000 0x40000>;
 604                         };
 605
 606                         partition@6c0000 {
 607                                 label = "qspi.env.backup";
 608                                 reg = <0x6c0000 0x40000>;
 609                         };
 610
 611                         partition@800000 {
 612                                 label = "qspi.rootfs";
 613                                 reg = <0x800000 0x37c0000>;
 614                         };
 615
 616                         partition@3fc0000 {
 617                                 bootph-all;
 618                                 label = "qspi.phypattern";
 619                                 reg = <0x3fc0000 0x40000>;
 620                         };
 621                 };
 622
 623         };
 624 };
 625
 626 &main_i2c0 {
 627         status = "okay";
 628         pinctrl-names = "default";
 629         pinctrl-0 = <&main_i2c0_pins_default>;
 630
 631         clock-frequency = <400000>;
 632
 633         exp1: gpio@20 {
 634                 compatible = "ti,tca6416";
 635                 reg = <0x20>;
 636                 gpio-controller;
 637                 #gpio-cells = <2>;
 638                 gpio-line-names = "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC_RSTZ",
 639                                   "PCIE1_2L_EP_RST_EN", "PCIE0_4L_MODE_SEL", "PCIE0_4L_PERSTZ",
 640                                   "PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#",
 641                                   "PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3",
 642                                   "AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ";
 643         };
 644
 645         exp2: gpio@22 {
 646                 compatible = "ti,tca6424";
 647                 reg = <0x22>;
 648                 gpio-controller;
 649                 #gpio-cells = <2>;
 650                 gpio-line-names = "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_PWR_EN",
 651                                   "USBC_PWR_EN", "USBC_MODE_SEL1", "USBC_MODE_SEL0",
 652                                   "GPIO_LIN_EN", "R_CAN_STB", "CTRL_PM_I2C_OE#",
 653                                   "ENET2_EXP_PWRDN", "ENET2_EXP_SPARE2", "CDCI2_RSTZ",
 654                                   "USB2.0_MUX_SEL", "CANUART_MUX_SEL0", "CANUART_MUX2_SEL1",
 655                                   "CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ",
 656                                   "ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ",
 657                                   "USER_INPUT1", "USER_LED1", "USER_LED2";
 658         };
 659 };
 660
 661 &main_sdhci0 {
 662         bootph-all;
 663         /* eMMC */
 664         status = "okay";
 665         non-removable;
 666         ti,driver-strength-ohm = <50>;
 667         disable-wp;
 668 };
 669
 670 &main_sdhci1 {
 671         bootph-all;
 672         /* SD card */
 673         status = "okay";
 674         pinctrl-0 = <&main_mmc1_pins_default>;
 675         pinctrl-names = "default";
 676         disable-wp;
 677         vmmc-supply = <&vdd_mmc1>;
 678         vqmmc-supply = <&vdd_sd_dv>;
 679 };
 680
 681 &main_gpio0 {
 682         status = "okay";
 683 };
 684
 685 &mcu_cpsw {
 686         status = "okay";
 687         pinctrl-names = "default";
 688         pinctrl-0 = <&mcu_cpsw_pins_default>;
 689 };
 690
 691 &davinci_mdio {
 692         pinctrl-names = "default";
 693         pinctrl-0 = <&mcu_mdio_pins_default>;
 694
 695         mcu_phy0: ethernet-phy@0 {
 696                 reg = <0>;
 697                 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 698                 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 699                 ti,min-output-impedance;
 700         };
 701 };
 702
 703 &mcu_cpsw_port1 {
 704         status = "okay";
 705         phy-mode = "rgmii-rxid";
 706         phy-handle = <&mcu_phy0>;
 707 };
 708
 709 &mailbox0_cluster0 {
 710         status = "okay";
 711         interrupts = <436>;
 712
 713         mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
 714                 ti,mbox-rx = <0 0 0>;
 715                 ti,mbox-tx = <1 0 0>;
 716         };
 717
 718         mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
 719                 ti,mbox-rx = <2 0 0>;
 720                 ti,mbox-tx = <3 0 0>;
 721         };
 722 };
 723
 724 &mailbox0_cluster1 {
 725         status = "okay";
 726         interrupts = <432>;
 727
 728         mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
 729                 ti,mbox-rx = <0 0 0>;
 730                 ti,mbox-tx = <1 0 0>;
 731         };
 732
 733         mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
 734                 ti,mbox-rx = <2 0 0>;
 735                 ti,mbox-tx = <3 0 0>;
 736         };
 737 };
 738
 739 &mailbox0_cluster2 {
 740         status = "okay";
 741         interrupts = <428>;
 742
 743         mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
 744                 ti,mbox-rx = <0 0 0>;
 745                 ti,mbox-tx = <1 0 0>;
 746         };
 747
 748         mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
 749                 ti,mbox-rx = <2 0 0>;
 750                 ti,mbox-tx = <3 0 0>;
 751         };
 752 };
 753
 754 &mailbox0_cluster3 {
 755         status = "okay";
 756         interrupts = <424>;
 757
 758         mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 {
 759                 ti,mbox-rx = <0 0 0>;
 760                 ti,mbox-tx = <1 0 0>;
 761         };
 762
 763         mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 {
 764                 ti,mbox-rx = <2 0 0>;
 765                 ti,mbox-tx = <3 0 0>;
 766         };
 767 };
 768
 769 &mailbox0_cluster4 {
 770         status = "okay";
 771         interrupts = <420>;
 772
 773         mbox_c71_0: mbox-c71-0 {
 774                 ti,mbox-rx = <0 0 0>;
 775                 ti,mbox-tx = <1 0 0>;
 776         };
 777
 778         mbox_c71_1: mbox-c71-1 {
 779                 ti,mbox-rx = <2 0 0>;
 780                 ti,mbox-tx = <3 0 0>;
 781         };
 782 };
 783
 784 &mailbox0_cluster5 {
 785         status = "okay";
 786         interrupts = <416>;
 787
 788         mbox_c71_2: mbox-c71-2 {
 789                 ti,mbox-rx = <0 0 0>;
 790                 ti,mbox-tx = <1 0 0>;
 791         };
 792
 793         mbox_c71_3: mbox-c71-3 {
 794                 ti,mbox-rx = <2 0 0>;
 795                 ti,mbox-tx = <3 0 0>;
 796         };
 797 };
 798
 799 &mcu_r5fss0_core0 {
 800         status = "okay";
 801         mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
 802         memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
 803                         <&mcu_r5fss0_core0_memory_region>;
 804 };
 805
 806 &mcu_r5fss0_core1 {
 807         status = "okay";
 808         mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
 809         memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
 810                         <&mcu_r5fss0_core1_memory_region>;
 811 };
 812
 813 &main_r5fss0_core0 {
 814         status = "okay";
 815         mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
 816         memory-region = <&main_r5fss0_core0_dma_memory_region>,
 817                         <&main_r5fss0_core0_memory_region>;
 818 };
 819
 820 &main_r5fss0_core1 {
 821         status = "okay";
 822         mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
 823         memory-region = <&main_r5fss0_core1_dma_memory_region>,
 824                         <&main_r5fss0_core1_memory_region>;
 825 };
 826
 827 &main_r5fss1_core0 {
 828         status = "okay";
 829         mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
 830         memory-region = <&main_r5fss1_core0_dma_memory_region>,
 831                         <&main_r5fss1_core0_memory_region>;
 832 };
 833
 834 &main_r5fss1_core1 {
 835         status = "okay";
 836         mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
 837         memory-region = <&main_r5fss1_core1_dma_memory_region>,
 838                         <&main_r5fss1_core1_memory_region>;
 839 };
 840
 841 &main_r5fss2_core0 {
 842         status = "okay";
 843         mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>;
 844         memory-region = <&main_r5fss2_core0_dma_memory_region>,
 845                         <&main_r5fss2_core0_memory_region>;
 846 };
 847
 848 &main_r5fss2_core1 {
 849         status = "okay";
 850         mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>;
 851         memory-region = <&main_r5fss2_core1_dma_memory_region>,
 852                         <&main_r5fss2_core1_memory_region>;
 853 };
 854
 855 &c71_0 {
 856         status = "okay";
 857         mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
 858         memory-region = <&c71_0_dma_memory_region>,
 859                         <&c71_0_memory_region>;
 860 };
 861
 862 &c71_1 {
 863         status = "okay";
 864         mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
 865         memory-region = <&c71_1_dma_memory_region>,
 866                         <&c71_1_memory_region>;
 867 };
 868
 869 &c71_2 {
 870         status = "okay";
 871         mboxes = <&mailbox0_cluster5 &mbox_c71_2>;
 872         memory-region = <&c71_2_dma_memory_region>,
 873                         <&c71_2_memory_region>;
 874 };
 875
 876 &c71_3 {
 877         status = "okay";
 878         mboxes = <&mailbox0_cluster5 &mbox_c71_3>;
 879         memory-region = <&c71_3_dma_memory_region>,
 880                         <&c71_3_memory_region>;
 881 };
 882
 883 &tscadc0 {
 884         pinctrl-0 = <&mcu_adc0_pins_default>;
 885         pinctrl-names = "default";
 886         status = "okay";
 887         adc {
 888                 ti,adc-channels = <0 1 2 3 4 5 6 7>;
 889         };
 890 };
 891
 892 &tscadc1 {
 893         pinctrl-0 = <&mcu_adc1_pins_default>;
 894         pinctrl-names = "default";
 895         status = "okay";
 896         adc {
 897                 ti,adc-channels = <0 1 2 3 4 5 6 7>;
 898         };
 899 };
 900
 901 &serdes_refclk {
 902         status = "okay";
 903         clock-frequency = <100000000>;
 904 };
 905
 906 &dss {
 907         status = "okay";
 908         assigned-clocks = <&k3_clks 218 2>,
 909                           <&k3_clks 218 5>,
 910                           <&k3_clks 218 14>,
 911                           <&k3_clks 218 18>;
 912         assigned-clock-parents = <&k3_clks 218 3>,
 913                                  <&k3_clks 218 7>,
 914                                  <&k3_clks 218 16>,
 915                                  <&k3_clks 218 22>;
 916 };
 917
 918 &serdes_wiz4 {
 919         status = "okay";
 920 };
 921
 922 &serdes4 {
 923         status = "okay";
 924         serdes4_dp_link: phy@0 {
 925                 reg = <0>;
 926                 cdns,num-lanes = <4>;
 927                 #phy-cells = <0>;
 928                 cdns,phy-type = <PHY_TYPE_DP>;
 929                 resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>,
 930                          <&serdes_wiz4 3>, <&serdes_wiz4 4>;
 931         };
 932 };
 933
 934 &mhdp {
 935         status = "okay";
 936         pinctrl-names = "default";
 937         pinctrl-0 = <&dp0_pins_default>;
 938         phys = <&serdes4_dp_link>;
 939         phy-names = "dpphy";
 940 };
 941
 942 &dss_ports {
 943         /* DP */
 944         port {
 945                 dpi0_out: endpoint {
 946                         remote-endpoint = <&dp0_in>;
 947                 };
 948         };
 949 };
 950
 951 &main_i2c4 {
 952         status = "okay";
 953         pinctrl-names = "default";
 954         pinctrl-0 = <&main_i2c4_pins_default>;
 955         clock-frequency = <400000>;
 956
 957         exp4: gpio@20 {
 958                 compatible = "ti,tca6408";
 959                 reg = <0x20>;
 960                 gpio-controller;
 961                 #gpio-cells = <2>;
 962         };
 963 };
 964
 965 &dp0_ports {
 966         port@0 {
 967                 reg = <0>;
 968
 969                 dp0_in: endpoint {
 970                         remote-endpoint = <&dpi0_out>;
 971                 };
 972         };
 973
 974         port@4 {
 975                 reg = <4>;
 976
 977                 dp0_out: endpoint {
 978                         remote-endpoint = <&dp0_connector_in>;
 979                 };
 980         };
 981 };