1 // SPDX-License-Identifier: GPL-2.0
3 * SoM: https://www.ti.com/lit/zip/sprr439
5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
10 #include "k3-j721s2.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
15 device_type = "memory";
17 reg = <0x00 0x80000000 0x00 0x80000000>,
18 <0x08 0x80000000 0x03 0x80000000>;
21 /* Reserving memory regions still pending */
22 reserved_memory: reserved-memory {
27 secure_ddr: optee@9e800000 {
28 reg = <0x00 0x9e800000 0x00 0x01800000>;
33 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
34 compatible = "shared-dma-pool";
35 reg = <0x00 0xa0000000 0x00 0x100000>;
39 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
40 compatible = "shared-dma-pool";
41 reg = <0x00 0xa0100000 0x00 0xf00000>;
45 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
46 compatible = "shared-dma-pool";
47 reg = <0x00 0xa1000000 0x00 0x100000>;
51 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
52 compatible = "shared-dma-pool";
53 reg = <0x00 0xa1100000 0x00 0xf00000>;
57 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
58 compatible = "shared-dma-pool";
59 reg = <0x00 0xa2000000 0x00 0x100000>;
63 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
64 compatible = "shared-dma-pool";
65 reg = <0x00 0xa2100000 0x00 0xf00000>;
69 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
70 compatible = "shared-dma-pool";
71 reg = <0x00 0xa3000000 0x00 0x100000>;
75 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
76 compatible = "shared-dma-pool";
77 reg = <0x00 0xa3100000 0x00 0xf00000>;
81 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
82 compatible = "shared-dma-pool";
83 reg = <0x00 0xa4000000 0x00 0x100000>;
87 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
88 compatible = "shared-dma-pool";
89 reg = <0x00 0xa4100000 0x00 0xf00000>;
93 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
94 compatible = "shared-dma-pool";
95 reg = <0x00 0xa5000000 0x00 0x100000>;
99 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
100 compatible = "shared-dma-pool";
101 reg = <0x00 0xa5100000 0x00 0xf00000>;
105 c71_0_dma_memory_region: c71-dma-memory@a6000000 {
106 compatible = "shared-dma-pool";
107 reg = <0x00 0xa6000000 0x00 0x100000>;
111 c71_0_memory_region: c71-memory@a6100000 {
112 compatible = "shared-dma-pool";
113 reg = <0x00 0xa6100000 0x00 0xf00000>;
117 c71_1_dma_memory_region: c71-dma-memory@a7000000 {
118 compatible = "shared-dma-pool";
119 reg = <0x00 0xa7000000 0x00 0x100000>;
123 c71_1_memory_region: c71-memory@a7100000 {
124 compatible = "shared-dma-pool";
125 reg = <0x00 0xa7100000 0x00 0xf00000>;
129 rtos_ipc_memory_region: ipc-memories@a8000000 {
130 reg = <0x00 0xa8000000 0x00 0x01c00000>;
131 alignment = <0x1000>;
136 mux0: mux-controller {
137 compatible = "gpio-mux";
138 #mux-state-cells = <1>;
139 mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>;
142 mux1: mux-controller {
143 compatible = "gpio-mux";
144 #mux-state-cells = <1>;
145 mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>;
148 transceiver0: can-phy0 {
149 /* standby pin has been grounded by default */
150 compatible = "ti,tcan1042";
152 max-bitrate = <5000000>;
157 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
158 pinctrl-single,pins = <
159 J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */
160 J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */
161 J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */
162 J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */
163 J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */
164 J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */
165 J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */
166 J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */
167 J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */
168 J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
169 J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
170 J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */
176 wkup_i2c0_pins_default: wkup-i2c0-default-pins {
177 pinctrl-single,pins = <
178 J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
179 J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
185 main_i2c0_pins_default: main-i2c0-default-pins {
186 pinctrl-single,pins = <
187 J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */
188 J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */
192 main_mcan16_pins_default: main-mcan16-default-pins {
193 pinctrl-single,pins = <
194 J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */
195 J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */
202 pinctrl-names = "default";
203 pinctrl-0 = <&wkup_i2c0_pins_default>;
204 clock-frequency = <400000>;
207 /* CAV24C256WE-GT3 */
208 compatible = "atmel,24c256";
215 pinctrl-names = "default";
216 pinctrl-0 = <&main_i2c0_pins_default>;
217 clock-frequency = <400000>;
220 compatible = "ti,tca6408";
224 gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
225 "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
226 "GPIO_RGMII1_RST", "GPIO_eDP_ENABLE",
227 "GPIO_LIN_EN", "CAN_STB";
233 pinctrl-0 = <&main_mcan16_pins_default>;
234 pinctrl-names = "default";
235 phys = <&transceiver0>;
240 pinctrl-names = "default";
241 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
244 compatible = "jedec,spi-nor";
246 spi-tx-bus-width = <8>;
247 spi-rx-bus-width = <8>;
248 spi-max-frequency = <25000000>;
249 cdns,tshsl-ns = <60>;
250 cdns,tsd2d-ns = <60>;
251 cdns,tchsh-ns = <60>;
252 cdns,tslch-ns = <60>;
253 cdns,read-delay = <4>;
260 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
261 ti,mbox-rx = <0 0 0>;
262 ti,mbox-tx = <1 0 0>;
265 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
266 ti,mbox-rx = <2 0 0>;
267 ti,mbox-tx = <3 0 0>;
274 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
275 ti,mbox-rx = <0 0 0>;
276 ti,mbox-tx = <1 0 0>;
279 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
280 ti,mbox-rx = <2 0 0>;
281 ti,mbox-tx = <3 0 0>;
288 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
289 ti,mbox-rx = <0 0 0>;
290 ti,mbox-tx = <1 0 0>;
293 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
294 ti,mbox-rx = <2 0 0>;
295 ti,mbox-tx = <3 0 0>;
302 mbox_c71_0: mbox-c71-0 {
303 ti,mbox-rx = <0 0 0>;
304 ti,mbox-tx = <1 0 0>;
307 mbox_c71_1: mbox-c71-1 {
308 ti,mbox-rx = <2 0 0>;
309 ti,mbox-tx = <3 0 0>;
314 mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
315 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
316 <&mcu_r5fss0_core0_memory_region>;
320 mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
321 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
322 <&mcu_r5fss0_core1_memory_region>;
326 mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
327 memory-region = <&main_r5fss0_core0_dma_memory_region>,
328 <&main_r5fss0_core0_memory_region>;
332 mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
333 memory-region = <&main_r5fss0_core1_dma_memory_region>,
334 <&main_r5fss0_core1_memory_region>;
338 mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
339 memory-region = <&main_r5fss1_core0_dma_memory_region>,
340 <&main_r5fss1_core0_memory_region>;
344 mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
345 memory-region = <&main_r5fss1_core1_dma_memory_region>,
346 <&main_r5fss1_core1_memory_region>;
351 mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
352 memory-region = <&c71_0_dma_memory_region>,
353 <&c71_0_memory_region>;
358 mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>;
359 memory-region = <&c71_1_dma_memory_region>,
360 <&c71_1_memory_region>;