arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals
   4  *
   5  * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 &cbass_mcu_wakeup {
   9         sms: system-controller@44083000 {
  10                 compatible = "ti,k2g-sci";
  11                 ti,host-id = <12>;
  12
  13                 mbox-names = "rx", "tx";
  14
  15                 mboxes = <&secure_proxy_main 11>,
  16                          <&secure_proxy_main 13>;
  17
  18                 reg-names = "debug_messages";
  19                 reg = <0x00 0x44083000 0x00 0x1000>;
  20
  21                 k3_pds: power-controller {
  22                         compatible = "ti,sci-pm-domain";
  23                         #power-domain-cells = <2>;
  24                 };
  25
  26                 k3_clks: clock-controller {
  27                         compatible = "ti,k2g-sci-clk";
  28                         #clock-cells = <2>;
  29                 };
  30
  31                 k3_reset: reset-controller {
  32                         compatible = "ti,sci-reset";
  33                         #reset-cells = <2>;
  34                 };
  35         };
  36
  37         chipid@43000014 {
  38                 compatible = "ti,am654-chipid";
  39                 reg = <0x00 0x43000014 0x00 0x4>;
  40         };
  41
  42         secure_proxy_sa3: mailbox@43600000 {
  43                 compatible = "ti,am654-secure-proxy";
  44                 #mbox-cells = <1>;
  45                 reg-names = "target_data", "rt", "scfg";
  46                 reg = <0x00 0x43600000 0x00 0x10000>,
  47                       <0x00 0x44880000 0x00 0x20000>,
  48                       <0x00 0x44860000 0x00 0x20000>;
  49                 /*
  50                  * Marked Disabled:
  51                  * Node is incomplete as it is meant for bootloaders and
  52                  * firmware on non-MPU processors
  53                  */
  54                 status = "disabled";
  55         };
  56
  57         mcu_ram: sram@41c00000 {
  58                 compatible = "mmio-sram";
  59                 reg = <0x00 0x41c00000 0x00 0x100000>;
  60                 ranges = <0x00 0x00 0x41c00000 0x100000>;
  61                 #address-cells = <1>;
  62                 #size-cells = <1>;
  63         };
  64
  65         wkup_pmx0: pinctrl@4301c000 {
  66                 compatible = "pinctrl-single";
  67                 /* Proxy 0 addressing */
  68                 reg = <0x00 0x4301c000 0x00 0x034>;
  69                 #pinctrl-cells = <1>;
  70                 pinctrl-single,register-width = <32>;
  71                 pinctrl-single,function-mask = <0xffffffff>;
  72         };
  73
  74         wkup_pmx1: pinctrl@4301c038 {
  75                 compatible = "pinctrl-single";
  76                 /* Proxy 0 addressing */
  77                 reg = <0x00 0x4301c038 0x00 0x02C>;
  78                 #pinctrl-cells = <1>;
  79                 pinctrl-single,register-width = <32>;
  80                 pinctrl-single,function-mask = <0xffffffff>;
  81         };
  82
  83         wkup_pmx2: pinctrl@4301c068 {
  84                 compatible = "pinctrl-single";
  85                 /* Proxy 0 addressing */
  86                 reg = <0x00 0x4301c068 0x00 0x120>;
  87                 #pinctrl-cells = <1>;
  88                 pinctrl-single,register-width = <32>;
  89                 pinctrl-single,function-mask = <0xffffffff>;
  90         };
  91
  92         wkup_pmx3: pinctrl@4301c190 {
  93                 compatible = "pinctrl-single";
  94                 /* Proxy 0 addressing */
  95                 reg = <0x00 0x4301c190 0x00 0x004>;
  96                 #pinctrl-cells = <1>;
  97                 pinctrl-single,register-width = <32>;
  98                 pinctrl-single,function-mask = <0xffffffff>;
  99         };
 100
 101         /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
 102         mcu_timerio_input: pinctrl@40f04200 {
 103                 compatible = "pinctrl-single";
 104                 reg = <0x00 0x40f04200 0x00 0x28>;
 105                 #pinctrl-cells = <1>;
 106                 pinctrl-single,register-width = <32>;
 107                 pinctrl-single,function-mask = <0x0000000f>;
 108                 /* Non-MPU Firmware usage */
 109                 status = "reserved";
 110         };
 111
 112         /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
 113         mcu_timerio_output: pinctrl@40f04280 {
 114                 compatible = "pinctrl-single";
 115                 reg = <0x00 0x40f04280 0x00 0x28>;
 116                 #pinctrl-cells = <1>;
 117                 pinctrl-single,register-width = <32>;
 118                 pinctrl-single,function-mask = <0x0000000f>;
 119                 /* Non-MPU Firmware usage */
 120                 status = "reserved";
 121         };
 122
 123         wkup_gpio_intr: interrupt-controller@42200000 {
 124                 compatible = "ti,sci-intr";
 125                 reg = <0x00 0x42200000 0x00 0x400>;
 126                 ti,intr-trigger-type = <1>;
 127                 interrupt-controller;
 128                 interrupt-parent = <&gic500>;
 129                 #interrupt-cells = <1>;
 130                 ti,sci = <&sms>;
 131                 ti,sci-dev-id = <125>;
 132                 ti,interrupt-ranges = <16 960 16>;
 133         };
 134
 135         mcu_conf: syscon@40f00000 {
 136                 compatible = "syscon", "simple-mfd";
 137                 reg = <0x0 0x40f00000 0x0 0x20000>;
 138                 #address-cells = <1>;
 139                 #size-cells = <1>;
 140                 ranges = <0x0 0x0 0x40f00000 0x20000>;
 141
 142                 phy_gmii_sel: phy@4040 {
 143                         compatible = "ti,am654-phy-gmii-sel";
 144                         reg = <0x4040 0x4>;
 145                         #phy-cells = <1>;
 146                 };
 147
 148         };
 149
 150         mcu_timer0: timer@40400000 {
 151                 compatible = "ti,am654-timer";
 152                 reg = <0x00 0x40400000 0x00 0x400>;
 153                 interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
 154                 clocks = <&k3_clks 35 1>;
 155                 clock-names = "fck";
 156                 assigned-clocks = <&k3_clks 35 1>;
 157                 assigned-clock-parents = <&k3_clks 35 2>;
 158                 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
 159                 ti,timer-pwm;
 160                 /* Non-MPU Firmware usage */
 161                 status = "reserved";
 162         };
 163
 164         mcu_timer1: timer@40410000 {
 165                 compatible = "ti,am654-timer";
 166                 reg = <0x00 0x40410000 0x00 0x400>;
 167                 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
 168                 clocks = <&k3_clks 83 1>;
 169                 clock-names = "fck";
 170                 assigned-clocks = <&k3_clks 83 1>;
 171                 assigned-clock-parents = <&k3_clks 83 2>;
 172                 power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
 173                 ti,timer-pwm;
 174                 /* Non-MPU Firmware usage */
 175                 status = "reserved";
 176         };
 177
 178         mcu_timer2: timer@40420000 {
 179                 compatible = "ti,am654-timer";
 180                 reg = <0x00 0x40420000 0x00 0x400>;
 181                 interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>;
 182                 clocks = <&k3_clks 84 1>;
 183                 clock-names = "fck";
 184                 assigned-clocks = <&k3_clks 84 1>;
 185                 assigned-clock-parents = <&k3_clks 84 2>;
 186                 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
 187                 ti,timer-pwm;
 188                 /* Non-MPU Firmware usage */
 189                 status = "reserved";
 190         };
 191
 192         mcu_timer3: timer@40430000 {
 193                 compatible = "ti,am654-timer";
 194                 reg = <0x00 0x40430000 0x00 0x400>;
 195                 interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>;
 196                 clocks = <&k3_clks 85 1>;
 197                 clock-names = "fck";
 198                 assigned-clocks = <&k3_clks 85 1>;
 199                 assigned-clock-parents = <&k3_clks 85 2>;
 200                 power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
 201                 ti,timer-pwm;
 202                 /* Non-MPU Firmware usage */
 203                 status = "reserved";
 204         };
 205
 206         mcu_timer4: timer@40440000 {
 207                 compatible = "ti,am654-timer";
 208                 reg = <0x00 0x40440000 0x00 0x400>;
 209                 interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>;
 210                 clocks = <&k3_clks 86 1>;
 211                 clock-names = "fck";
 212                 assigned-clocks = <&k3_clks 86 1>;
 213                 assigned-clock-parents = <&k3_clks 86 2>;
 214                 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
 215                 ti,timer-pwm;
 216                 /* Non-MPU Firmware usage */
 217                 status = "reserved";
 218         };
 219
 220         mcu_timer5: timer@40450000 {
 221                 compatible = "ti,am654-timer";
 222                 reg = <0x00 0x40450000 0x00 0x400>;
 223                 interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>;
 224                 clocks = <&k3_clks 87 1>;
 225                 clock-names = "fck";
 226                 assigned-clocks = <&k3_clks 87 1>;
 227                 assigned-clock-parents = <&k3_clks 87 2>;
 228                 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
 229                 ti,timer-pwm;
 230                 /* Non-MPU Firmware usage */
 231                 status = "reserved";
 232         };
 233
 234         mcu_timer6: timer@40460000 {
 235                 compatible = "ti,am654-timer";
 236                 reg = <0x00 0x40460000 0x00 0x400>;
 237                 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
 238                 clocks = <&k3_clks 88 1>;
 239                 clock-names = "fck";
 240                 assigned-clocks = <&k3_clks 88 1>;
 241                 assigned-clock-parents = <&k3_clks 88 2>;
 242                 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
 243                 ti,timer-pwm;
 244                 /* Non-MPU Firmware usage */
 245                 status = "reserved";
 246         };
 247
 248         mcu_timer7: timer@40470000 {
 249                 compatible = "ti,am654-timer";
 250                 reg = <0x00 0x40470000 0x00 0x400>;
 251                 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
 252                 clocks = <&k3_clks 89 1>;
 253                 clock-names = "fck";
 254                 assigned-clocks = <&k3_clks 89 1>;
 255                 assigned-clock-parents = <&k3_clks 89 2>;
 256                 power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>;
 257                 ti,timer-pwm;
 258                 /* Non-MPU Firmware usage */
 259                 status = "reserved";
 260         };
 261
 262         mcu_timer8: timer@40480000 {
 263                 compatible = "ti,am654-timer";
 264                 reg = <0x00 0x40480000 0x00 0x400>;
 265                 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
 266                 clocks = <&k3_clks 90 1>;
 267                 clock-names = "fck";
 268                 assigned-clocks = <&k3_clks 90 1>;
 269                 assigned-clock-parents = <&k3_clks 90 2>;
 270                 power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>;
 271                 ti,timer-pwm;
 272                 /* Non-MPU Firmware usage */
 273                 status = "reserved";
 274         };
 275
 276         mcu_timer9: timer@40490000 {
 277                 compatible = "ti,am654-timer";
 278                 reg = <0x00 0x40490000 0x00 0x400>;
 279                 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
 280                 clocks = <&k3_clks 91 1>;
 281                 clock-names = "fck";
 282                 assigned-clocks = <&k3_clks 91 1>;
 283                 assigned-clock-parents = <&k3_clks 91 2>;
 284                 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
 285                 ti,timer-pwm;
 286                 /* Non-MPU Firmware usage */
 287                 status = "reserved";
 288         };
 289
 290         wkup_uart0: serial@42300000 {
 291                 compatible = "ti,j721e-uart", "ti,am654-uart";
 292                 reg = <0x00 0x42300000 0x00 0x200>;
 293                 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
 294                 current-speed = <115200>;
 295                 clocks = <&k3_clks 359 3>;
 296                 clock-names = "fclk";
 297                 power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>;
 298                 status = "disabled";
 299         };
 300
 301         mcu_uart0: serial@40a00000 {
 302                 compatible = "ti,j721e-uart", "ti,am654-uart";
 303                 reg = <0x00 0x40a00000 0x00 0x200>;
 304                 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
 305                 current-speed = <115200>;
 306                 clocks = <&k3_clks 149 3>;
 307                 clock-names = "fclk";
 308                 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
 309                 status = "disabled";
 310         };
 311
 312         wkup_gpio0: gpio@42110000 {
 313                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 314                 reg = <0x00 0x42110000 0x00 0x100>;
 315                 gpio-controller;
 316                 #gpio-cells = <2>;
 317                 interrupt-parent = <&wkup_gpio_intr>;
 318                 interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
 319                 interrupt-controller;
 320                 #interrupt-cells = <2>;
 321                 ti,ngpio = <89>;
 322                 ti,davinci-gpio-unbanked = <0>;
 323                 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
 324                 clocks = <&k3_clks 115 0>;
 325                 clock-names = "gpio";
 326                 status = "disabled";
 327         };
 328
 329         wkup_gpio1: gpio@42100000 {
 330                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 331                 reg = <0x00 0x42100000 0x00 0x100>;
 332                 gpio-controller;
 333                 #gpio-cells = <2>;
 334                 interrupt-parent = <&wkup_gpio_intr>;
 335                 interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
 336                 interrupt-controller;
 337                 #interrupt-cells = <2>;
 338                 ti,ngpio = <89>;
 339                 ti,davinci-gpio-unbanked = <0>;
 340                 power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
 341                 clocks = <&k3_clks 116 0>;
 342                 clock-names = "gpio";
 343                 status = "disabled";
 344         };
 345
 346         wkup_i2c0: i2c@42120000 {
 347                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 348                 reg = <0x00 0x42120000 0x00 0x100>;
 349                 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
 350                 #address-cells = <1>;
 351                 #size-cells = <0>;
 352                 clocks = <&k3_clks 223 1>;
 353                 clock-names = "fck";
 354                 power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
 355                 status = "disabled";
 356         };
 357
 358         mcu_i2c0: i2c@40b00000 {
 359                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 360                 reg = <0x00 0x40b00000 0x00 0x100>;
 361                 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
 362                 #address-cells = <1>;
 363                 #size-cells = <0>;
 364                 clocks = <&k3_clks 221 1>;
 365                 clock-names = "fck";
 366                 power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>;
 367                 status = "disabled";
 368         };
 369
 370         mcu_i2c1: i2c@40b10000 {
 371                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 372                 reg = <0x00 0x40b10000 0x00 0x100>;
 373                 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
 374                 #address-cells = <1>;
 375                 #size-cells = <0>;
 376                 clocks = <&k3_clks 222 1>;
 377                 clock-names = "fck";
 378                 power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>;
 379                 status = "disabled";
 380         };
 381
 382         mcu_mcan0: can@40528000 {
 383                 compatible = "bosch,m_can";
 384                 reg = <0x00 0x40528000 0x00 0x200>,
 385                       <0x00 0x40500000 0x00 0x8000>;
 386                 reg-names = "m_can", "message_ram";
 387                 power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>;
 388                 clocks = <&k3_clks 207 0>, <&k3_clks 207 1>;
 389                 clock-names = "hclk", "cclk";
 390                 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
 391                              <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
 392                 interrupt-names = "int0", "int1";
 393                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 394                 status = "disabled";
 395         };
 396
 397         mcu_mcan1: can@40568000 {
 398                 compatible = "bosch,m_can";
 399                 reg = <0x00 0x40568000 0x00 0x200>,
 400                       <0x00 0x40540000 0x00 0x8000>;
 401                 reg-names = "m_can", "message_ram";
 402                 power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>;
 403                 clocks = <&k3_clks 208 0>, <&k3_clks 208 1>;
 404                 clock-names = "hclk", "cclk";
 405                 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
 406                              <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
 407                 interrupt-names = "int0", "int1";
 408                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 409                 status = "disabled";
 410         };
 411
 412         mcu_spi0: spi@40300000 {
 413                 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
 414                 reg = <0x00 0x040300000 0x00 0x400>;
 415                 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
 416                 #address-cells = <1>;
 417                 #size-cells = <0>;
 418                 power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>;
 419                 clocks = <&k3_clks 347 0>;
 420                 status = "disabled";
 421         };
 422
 423         mcu_spi1: spi@40310000 {
 424                 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
 425                 reg = <0x00 0x040310000 0x00 0x400>;
 426                 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
 427                 #address-cells = <1>;
 428                 #size-cells = <0>;
 429                 power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>;
 430                 clocks = <&k3_clks 348 0>;
 431                 status = "disabled";
 432         };
 433
 434         mcu_spi2: spi@40320000 {
 435                 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
 436                 reg = <0x00 0x040320000 0x00 0x400>;
 437                 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
 438                 #address-cells = <1>;
 439                 #size-cells = <0>;
 440                 power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>;
 441                 clocks = <&k3_clks 349 0>;
 442                 status = "disabled";
 443         };
 444
 445         mcu_navss: bus@28380000 {
 446                 compatible = "simple-bus";
 447                 #address-cells = <2>;
 448                 #size-cells = <2>;
 449                 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
 450                 dma-coherent;
 451                 dma-ranges;
 452
 453                 ti,sci-dev-id = <267>;
 454
 455                 mcu_ringacc: ringacc@2b800000 {
 456                         compatible = "ti,am654-navss-ringacc";
 457                         reg = <0x0 0x2b800000 0x0 0x400000>,
 458                               <0x0 0x2b000000 0x0 0x400000>,
 459                               <0x0 0x28590000 0x0 0x100>,
 460                               <0x0 0x2a500000 0x0 0x40000>,
 461                               <0x0 0x28440000 0x0 0x40000>;
 462                         reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
 463                         ti,num-rings = <286>;
 464                         ti,sci-rm-range-gp-rings = <0x1>;
 465                         ti,sci = <&sms>;
 466                         ti,sci-dev-id = <272>;
 467                         msi-parent = <&main_udmass_inta>;
 468                 };
 469
 470                 mcu_udmap: dma-controller@285c0000 {
 471                         compatible = "ti,j721e-navss-mcu-udmap";
 472                         reg = <0x0 0x285c0000 0x0 0x100>,
 473                               <0x0 0x2a800000 0x0 0x40000>,
 474                               <0x0 0x2aa00000 0x0 0x40000>;
 475                         reg-names = "gcfg", "rchanrt", "tchanrt";
 476                         msi-parent = <&main_udmass_inta>;
 477                         #dma-cells = <1>;
 478
 479                         ti,sci = <&sms>;
 480                         ti,sci-dev-id = <273>;
 481                         ti,ringacc = <&mcu_ringacc>;
 482                         ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
 483                                                 <0x0f>; /* TX_HCHAN */
 484                         ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
 485                                                 <0x0b>; /* RX_HCHAN */
 486                         ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
 487                 };
 488         };
 489
 490         secure_proxy_mcu: mailbox@2a480000 {
 491                 compatible = "ti,am654-secure-proxy";
 492                 #mbox-cells = <1>;
 493                 reg-names = "target_data", "rt", "scfg";
 494                 reg = <0x00 0x2a480000 0x00 0x80000>,
 495                       <0x00 0x2a380000 0x00 0x80000>,
 496                       <0x00 0x2a400000 0x00 0x80000>;
 497                 /*
 498                  * Marked Disabled:
 499                  * Node is incomplete as it is meant for bootloaders and
 500                  * firmware on non-MPU processors
 501                  */
 502                 status = "disabled";
 503         };
 504
 505         mcu_cpsw: ethernet@46000000 {
 506                 compatible = "ti,j721e-cpsw-nuss";
 507                 #address-cells = <2>;
 508                 #size-cells = <2>;
 509                 reg = <0x0 0x46000000 0x0 0x200000>;
 510                 reg-names = "cpsw_nuss";
 511                 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
 512                 dma-coherent;
 513                 clocks = <&k3_clks 29 28>;
 514                 clock-names = "fck";
 515                 power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
 516
 517                 dmas = <&mcu_udmap 0xf000>,
 518                        <&mcu_udmap 0xf001>,
 519                        <&mcu_udmap 0xf002>,
 520                        <&mcu_udmap 0xf003>,
 521                        <&mcu_udmap 0xf004>,
 522                        <&mcu_udmap 0xf005>,
 523                        <&mcu_udmap 0xf006>,
 524                        <&mcu_udmap 0xf007>,
 525                        <&mcu_udmap 0x7000>;
 526                 dma-names = "tx0", "tx1", "tx2", "tx3",
 527                             "tx4", "tx5", "tx6", "tx7",
 528                             "rx";
 529
 530                 ethernet-ports {
 531                         #address-cells = <1>;
 532                         #size-cells = <0>;
 533
 534                         cpsw_port1: port@1 {
 535                                 reg = <1>;
 536                                 ti,mac-only;
 537                                 label = "port1";
 538                                 ti,syscon-efuse = <&mcu_conf 0x200>;
 539                                 phys = <&phy_gmii_sel 1>;
 540                         };
 541                 };
 542
 543                 davinci_mdio: mdio@f00 {
 544                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
 545                         reg = <0x0 0xf00 0x0 0x100>;
 546                         #address-cells = <1>;
 547                         #size-cells = <0>;
 548                         clocks = <&k3_clks 29 28>;
 549                         clock-names = "fck";
 550                         bus_freq = <1000000>;
 551                 };
 552
 553                 cpts@3d000 {
 554                         compatible = "ti,am65-cpts";
 555                         reg = <0x0 0x3d000 0x0 0x400>;
 556                         clocks = <&k3_clks 29 3>;
 557                         clock-names = "cpts";
 558                         assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */
 559                         assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */
 560                         interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
 561                         interrupt-names = "cpts";
 562                         ti,cpts-ext-ts-inputs = <4>;
 563                         ti,cpts-periodic-outputs = <2>;
 564                 };
 565         };
 566
 567         tscadc0: tscadc@40200000 {
 568                 compatible = "ti,am3359-tscadc";
 569                 reg = <0x00 0x40200000 0x00 0x1000>;
 570                 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
 571                 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
 572                 clocks = <&k3_clks 0 0>;
 573                 assigned-clocks = <&k3_clks 0 2>;
 574                 assigned-clock-rates = <60000000>;
 575                 clock-names = "fck";
 576                 dmas = <&main_udmap 0x7400>,
 577                         <&main_udmap 0x7401>;
 578                 dma-names = "fifo0", "fifo1";
 579                 status = "disabled";
 580
 581                 adc {
 582                         #io-channel-cells = <1>;
 583                         compatible = "ti,am3359-adc";
 584                 };
 585         };
 586
 587         tscadc1: tscadc@40210000 {
 588                 compatible = "ti,am3359-tscadc";
 589                 reg = <0x00 0x40210000 0x00 0x1000>;
 590                 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
 591                 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
 592                 clocks = <&k3_clks 1 0>;
 593                 assigned-clocks = <&k3_clks 1 2>;
 594                 assigned-clock-rates = <60000000>;
 595                 clock-names = "fck";
 596                 dmas = <&main_udmap 0x7402>,
 597                         <&main_udmap 0x7403>;
 598                 dma-names = "fifo0", "fifo1";
 599                 status = "disabled";
 600
 601                 adc {
 602                         #io-channel-cells = <1>;
 603                         compatible = "ti,am3359-adc";
 604                 };
 605         };
 606
 607         fss: bus@47000000 {
 608                 compatible = "simple-bus";
 609                 #address-cells = <2>;
 610                 #size-cells = <2>;
 611                 ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
 612                          <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
 613                          <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
 614
 615                 ospi0: spi@47040000 {
 616                         compatible = "ti,am654-ospi", "cdns,qspi-nor";
 617                         reg = <0x00 0x47040000 0x00 0x100>,
 618                               <0x05 0x00000000 0x01 0x00000000>;
 619                         interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
 620                         cdns,fifo-depth = <256>;
 621                         cdns,fifo-width = <4>;
 622                         cdns,trigger-address = <0x0>;
 623                         clocks = <&k3_clks 109 5>;
 624                         assigned-clocks = <&k3_clks 109 5>;
 625                         assigned-clock-parents = <&k3_clks 109 7>;
 626                         assigned-clock-rates = <166666666>;
 627                         power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
 628                         #address-cells = <1>;
 629                         #size-cells = <0>;
 630
 631                         status = "disabled"; /* Needs pinmux */
 632                 };
 633
 634                 ospi1: spi@47050000 {
 635                         compatible = "ti,am654-ospi", "cdns,qspi-nor";
 636                         reg = <0x00 0x47050000 0x00 0x100>,
 637                               <0x07 0x00000000 0x01 0x00000000>;
 638                         interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
 639                         cdns,fifo-depth = <256>;
 640                         cdns,fifo-width = <4>;
 641                         cdns,trigger-address = <0x0>;
 642                         clocks = <&k3_clks 110 5>;
 643                         power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
 644                         #address-cells = <1>;
 645                         #size-cells = <0>;
 646
 647                         status = "disabled"; /* Needs pinmux */
 648                 };
 649         };
 650
 651         wkup_vtm0: temperature-sensor@42040000 {
 652                 compatible = "ti,j7200-vtm";
 653                 reg = <0x00 0x42040000 0x0 0x350>,
 654                       <0x00 0x42050000 0x0 0x350>;
 655                 power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>;
 656                 #thermal-sensor-cells = <1>;
 657         };
 658
 659         mcu_r5fss0: r5fss@41000000 {
 660                 compatible = "ti,j721s2-r5fss";
 661                 ti,cluster-mode = <1>;
 662                 #address-cells = <1>;
 663                 #size-cells = <1>;
 664                 ranges = <0x41000000 0x00 0x41000000 0x20000>,
 665                          <0x41400000 0x00 0x41400000 0x20000>;
 666                 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
 667
 668                 mcu_r5fss0_core0: r5f@41000000 {
 669                         compatible = "ti,j721s2-r5f";
 670                         reg = <0x41000000 0x00010000>,
 671                               <0x41010000 0x00010000>;
 672                         reg-names = "atcm", "btcm";
 673                         ti,sci = <&sms>;
 674                         ti,sci-dev-id = <284>;
 675                         ti,sci-proc-ids = <0x01 0xff>;
 676                         resets = <&k3_reset 284 1>;
 677                         firmware-name = "j721s2-mcu-r5f0_0-fw";
 678                         ti,atcm-enable = <1>;
 679                         ti,btcm-enable = <1>;
 680                         ti,loczrama = <1>;
 681                 };
 682
 683                 mcu_r5fss0_core1: r5f@41400000 {
 684                         compatible = "ti,j721s2-r5f";
 685                         reg = <0x41400000 0x00010000>,
 686                               <0x41410000 0x00010000>;
 687                         reg-names = "atcm", "btcm";
 688                         ti,sci = <&sms>;
 689                         ti,sci-dev-id = <285>;
 690                         ti,sci-proc-ids = <0x02 0xff>;
 691                         resets = <&k3_reset 285 1>;
 692                         firmware-name = "j721s2-mcu-r5f0_1-fw";
 693                         ti,atcm-enable = <1>;
 694                         ti,btcm-enable = <1>;
 695                         ti,loczrama = <1>;
 696                 };
 697         };
 698
 699         mcu_esm: esm@40800000 {
 700                 compatible = "ti,j721e-esm";
 701                 reg = <0x00 0x40800000 0x00 0x1000>;
 702                 ti,esm-pins = <95>;
 703                 bootph-pre-ram;
 704         };
 705
 706         wkup_esm: esm@42080000 {
 707                 compatible = "ti,j721e-esm";
 708                 reg = <0x00 0x42080000 0x00 0x1000>;
 709                 ti,esm-pins = <63>;
 710                 bootph-pre-ram;
 711         };
 712
 713         /*
 714          * The 2 RTI instances are couple with MCU R5Fs so keeping them
 715          * reserved as these will be used by their respective firmware
 716          */
 717         mcu_watchdog0: watchdog@40600000 {
 718                 compatible = "ti,j7-rti-wdt";
 719                 reg = <0x00 0x40600000 0x00 0x100>;
 720                 clocks = <&k3_clks 295 1>;
 721                 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
 722                 assigned-clocks = <&k3_clks 295 1>;
 723                 assigned-clock-parents = <&k3_clks 295 5>;
 724                 /* reserved for MCU_R5F0_0 */
 725                 status = "reserved";
 726         };
 727
 728         mcu_watchdog1: watchdog@40610000 {
 729                 compatible = "ti,j7-rti-wdt";
 730                 reg = <0x00 0x40610000 0x00 0x100>;
 731                 clocks = <&k3_clks 296 1>;
 732                 power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>;
 733                 assigned-clocks = <&k3_clks 296 1>;
 734                 assigned-clock-parents = <&k3_clks 296 5>;
 735                 /* reserved for MCU_R5F0_1 */
 736                 status = "reserved";
 737         };
 738 };