1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for AM6 SoC family in Quad core configuration
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
8 #include "k3-am65.dtsi"
37 compatible = "arm,cortex-a53";
40 enable-method = "psci";
41 i-cache-size = <0x8000>;
42 i-cache-line-size = <64>;
44 d-cache-size = <0x8000>;
45 d-cache-line-size = <64>;
47 next-level-cache = <&L2_0>;
51 compatible = "arm,cortex-a53";
54 enable-method = "psci";
55 i-cache-size = <0x8000>;
56 i-cache-line-size = <64>;
58 d-cache-size = <0x8000>;
59 d-cache-line-size = <64>;
61 next-level-cache = <&L2_0>;
65 compatible = "arm,cortex-a53";
68 enable-method = "psci";
69 i-cache-size = <0x8000>;
70 i-cache-line-size = <64>;
72 d-cache-size = <0x8000>;
73 d-cache-line-size = <64>;
75 next-level-cache = <&L2_1>;
79 compatible = "arm,cortex-a53";
82 enable-method = "psci";
83 i-cache-size = <0x8000>;
84 i-cache-line-size = <64>;
86 d-cache-size = <0x8000>;
87 d-cache-line-size = <64>;
89 next-level-cache = <&L2_1>;
97 cache-size = <0x80000>;
98 cache-line-size = <64>;
100 next-level-cache = <&msmc_l3>;
104 compatible = "cache";
107 cache-size = <0x80000>;
108 cache-line-size = <64>;
110 next-level-cache = <&msmc_l3>;
114 compatible = "cache";
119 thermal_zones: thermal-zones {
120 #include "k3-am654-industrial-thermal.dtsi"