arch/arm64/boot/dts/ti/k3-am65-main.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for AM6 SoC Family Main Domain peripherals
   4  *
   5  * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7 #include <dt-bindings/phy/phy-am654-serdes.h>
   8
   9 &cbass_main {
  10         msmc_ram: sram@70000000 {
  11                 compatible = "mmio-sram";
  12                 reg = <0x0 0x70000000 0x0 0x200000>;
  13                 #address-cells = <1>;
  14                 #size-cells = <1>;
  15                 ranges = <0x0 0x0 0x70000000 0x200000>;
  16
  17                 atf-sram@0 {
  18                         reg = <0x0 0x20000>;
  19                 };
  20
  21                 sysfw-sram@f0000 {
  22                         reg = <0xf0000 0x10000>;
  23                 };
  24
  25                 l3cache-sram@100000 {
  26                         reg = <0x100000 0x100000>;
  27                 };
  28         };
  29
  30         gic500: interrupt-controller@1800000 {
  31                 compatible = "arm,gic-v3";
  32                 #address-cells = <2>;
  33                 #size-cells = <2>;
  34                 ranges;
  35                 #interrupt-cells = <3>;
  36                 interrupt-controller;
  37                 reg = <0x00 0x01800000 0x00 0x10000>,   /* GICD */
  38                       <0x00 0x01880000 0x00 0x90000>;   /* GICR */
  39                 /*
  40                  * vcpumntirq:
  41                  * virtual CPU interface maintenance interrupt
  42                  */
  43                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  44
  45                 gic_its: gic-its@1820000 {
  46                         compatible = "arm,gic-v3-its";
  47                         reg = <0x00 0x01820000 0x00 0x10000>;
  48                         socionext,synquacer-pre-its = <0x1000000 0x400000>;
  49                         msi-controller;
  50                         #msi-cells = <1>;
  51                 };
  52         };
  53
  54         secure_proxy_main: mailbox@32c00000 {
  55                 compatible = "ti,am654-secure-proxy";
  56                 #mbox-cells = <1>;
  57                 reg-names = "target_data", "rt", "scfg";
  58                 reg = <0x00 0x32c00000 0x00 0x100000>,
  59                       <0x00 0x32400000 0x00 0x100000>,
  60                       <0x00 0x32800000 0x00 0x100000>;
  61                 interrupt-names = "rx_011";
  62                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  63         };
  64
  65         serdes0: serdes@900000 {
  66                 compatible = "ti,phy-am654-serdes";
  67                 reg = <0x0 0x900000 0x0 0x2000>;
  68                 reg-names = "serdes";
  69                 #phy-cells = <2>;
  70                 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
  71                 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
  72                 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
  73                 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
  74                 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
  75                 ti,serdes-clk = <&serdes0_clk>;
  76                 #clock-cells = <1>;
  77                 mux-controls = <&serdes_mux 0>;
  78         };
  79
  80         serdes1: serdes@910000 {
  81                 compatible = "ti,phy-am654-serdes";
  82                 reg = <0x0 0x910000 0x0 0x2000>;
  83                 reg-names = "serdes";
  84                 #phy-cells = <2>;
  85                 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
  86                 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
  87                 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
  88                 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
  89                 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
  90                 ti,serdes-clk = <&serdes1_clk>;
  91                 #clock-cells = <1>;
  92                 mux-controls = <&serdes_mux 1>;
  93         };
  94
  95         main_uart0: serial@2800000 {
  96                 compatible = "ti,am654-uart";
  97                 reg = <0x00 0x02800000 0x00 0x100>;
  98                 reg-shift = <2>;
  99                 reg-io-width = <4>;
 100                 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
 101                 clock-frequency = <48000000>;
 102                 current-speed = <115200>;
 103                 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
 104         };
 105
 106         main_uart1: serial@2810000 {
 107                 compatible = "ti,am654-uart";
 108                 reg = <0x00 0x02810000 0x00 0x100>;
 109                 reg-shift = <2>;
 110                 reg-io-width = <4>;
 111                 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 112                 clock-frequency = <48000000>;
 113                 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
 114         };
 115
 116         main_uart2: serial@2820000 {
 117                 compatible = "ti,am654-uart";
 118                 reg = <0x00 0x02820000 0x00 0x100>;
 119                 reg-shift = <2>;
 120                 reg-io-width = <4>;
 121                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
 122                 clock-frequency = <48000000>;
 123                 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
 124         };
 125
 126         main_pmx0: pinmux@11c000 {
 127                 compatible = "pinctrl-single";
 128                 reg = <0x0 0x11c000 0x0 0x2e4>;
 129                 #pinctrl-cells = <1>;
 130                 pinctrl-single,register-width = <32>;
 131                 pinctrl-single,function-mask = <0xffffffff>;
 132         };
 133
 134         main_pmx1: pinmux@11c2e8 {
 135                 compatible = "pinctrl-single";
 136                 reg = <0x0 0x11c2e8 0x0 0x24>;
 137                 #pinctrl-cells = <1>;
 138                 pinctrl-single,register-width = <32>;
 139                 pinctrl-single,function-mask = <0xffffffff>;
 140         };
 141
 142         main_i2c0: i2c@2000000 {
 143                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
 144                 reg = <0x0 0x2000000 0x0 0x100>;
 145                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 146                 #address-cells = <1>;
 147                 #size-cells = <0>;
 148                 clock-names = "fck";
 149                 clocks = <&k3_clks 110 1>;
 150                 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
 151         };
 152
 153         main_i2c1: i2c@2010000 {
 154                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
 155                 reg = <0x0 0x2010000 0x0 0x100>;
 156                 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 157                 #address-cells = <1>;
 158                 #size-cells = <0>;
 159                 clock-names = "fck";
 160                 clocks = <&k3_clks 111 1>;
 161                 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
 162         };
 163
 164         main_i2c2: i2c@2020000 {
 165                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
 166                 reg = <0x0 0x2020000 0x0 0x100>;
 167                 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
 168                 #address-cells = <1>;
 169                 #size-cells = <0>;
 170                 clock-names = "fck";
 171                 clocks = <&k3_clks 112 1>;
 172                 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
 173         };
 174
 175         main_i2c3: i2c@2030000 {
 176                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
 177                 reg = <0x0 0x2030000 0x0 0x100>;
 178                 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 179                 #address-cells = <1>;
 180                 #size-cells = <0>;
 181                 clock-names = "fck";
 182                 clocks = <&k3_clks 113 1>;
 183                 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
 184         };
 185
 186         ecap0: pwm@3100000 {
 187                 compatible = "ti,am654-ecap", "ti,am3352-ecap";
 188                 #pwm-cells = <3>;
 189                 reg = <0x0 0x03100000 0x0 0x60>;
 190                 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
 191                 clocks = <&k3_clks 39 0>;
 192                 clock-names = "fck";
 193         };
 194
 195         main_spi0: spi@2100000 {
 196                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 197                 reg = <0x0 0x2100000 0x0 0x400>;
 198                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 199                 clocks = <&k3_clks 137 1>;
 200                 power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
 201                 #address-cells = <1>;
 202                 #size-cells = <0>;
 203         };
 204
 205         main_spi1: spi@2110000 {
 206                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 207                 reg = <0x0 0x2110000 0x0 0x400>;
 208                 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
 209                 clocks = <&k3_clks 138 1>;
 210                 power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
 211                 #address-cells = <1>;
 212                 #size-cells = <0>;
 213                 assigned-clocks = <&k3_clks 137 1>;
 214                 assigned-clock-rates = <48000000>;
 215         };
 216
 217         main_spi2: spi@2120000 {
 218                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 219                 reg = <0x0 0x2120000 0x0 0x400>;
 220                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 221                 clocks = <&k3_clks 139 1>;
 222                 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
 223                 #address-cells = <1>;
 224                 #size-cells = <0>;
 225         };
 226
 227         main_spi3: spi@2130000 {
 228                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 229                 reg = <0x0 0x2130000 0x0 0x400>;
 230                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 231                 clocks = <&k3_clks 140 1>;
 232                 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
 233                 #address-cells = <1>;
 234                 #size-cells = <0>;
 235         };
 236
 237         main_spi4: spi@2140000 {
 238                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 239                 reg = <0x0 0x2140000 0x0 0x400>;
 240                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 241                 clocks = <&k3_clks 141 1>;
 242                 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
 243                 #address-cells = <1>;
 244                 #size-cells = <0>;
 245         };
 246
 247         sdhci0: sdhci@4f80000 {
 248                 compatible = "ti,am654-sdhci-5.1";
 249                 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
 250                 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
 251                 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
 252                 clock-names = "clk_ahb", "clk_xin";
 253                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 254                 mmc-ddr-1_8v;
 255                 mmc-hs200-1_8v;
 256                 ti,otap-del-sel = <0x2>;
 257                 ti,trm-icp = <0x8>;
 258                 dma-coherent;
 259         };
 260
 261         scm_conf: scm_conf@100000 {
 262                 compatible = "syscon", "simple-mfd";
 263                 reg = <0 0x00100000 0 0x1c000>;
 264                 #address-cells = <1>;
 265                 #size-cells = <1>;
 266                 ranges = <0x0 0x0 0x00100000 0x1c000>;
 267
 268                 pcie0_mode: pcie-mode@4060 {
 269                         compatible = "syscon";
 270                         reg = <0x00004060 0x4>;
 271                 };
 272
 273                 pcie1_mode: pcie-mode@4070 {
 274                         compatible = "syscon";
 275                         reg = <0x00004070 0x4>;
 276                 };
 277
 278                 pcie_devid: pcie-devid@210 {
 279                         compatible = "syscon";
 280                         reg = <0x00000210 0x4>;
 281                 };
 282
 283                 serdes0_clk: serdes_clk@4080 {
 284                         compatible = "syscon";
 285                         reg = <0x00004080 0x4>;
 286                 };
 287
 288                 serdes1_clk: serdes_clk@4090 {
 289                         compatible = "syscon";
 290                         reg = <0x00004090 0x4>;
 291                 };
 292
 293                 serdes_mux: mux-controller {
 294                         compatible = "mmio-mux";
 295                         #mux-control-cells = <1>;
 296                         mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
 297                                         <0x4090 0x3>; /* SERDES1 lane select */
 298                 };
 299         };
 300
 301         dwc3_0: dwc3@4000000 {
 302                 compatible = "ti,am654-dwc3";
 303                 reg = <0x0 0x4000000 0x0 0x4000>;
 304                 #address-cells = <1>;
 305                 #size-cells = <1>;
 306                 ranges = <0x0 0x0 0x4000000 0x20000>;
 307                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 308                 dma-coherent;
 309                 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
 310                 clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
 311                 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
 312                 assigned-clock-parents = <&k3_clks 151 4>,      /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
 313                                          <&k3_clks 151 9>;      /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
 314
 315                 usb0: usb@10000 {
 316                         compatible = "snps,dwc3";
 317                         reg = <0x10000 0x10000>;
 318                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 319                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 320                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 321                         interrupt-names = "peripheral",
 322                                           "host",
 323                                           "otg";
 324                         maximum-speed = "high-speed";
 325                         dr_mode = "otg";
 326                         phys = <&usb0_phy>;
 327                         phy-names = "usb2-phy";
 328                         snps,dis_u3_susphy_quirk;
 329                 };
 330         };
 331
 332         usb0_phy: phy@4100000 {
 333                 compatible = "ti,am654-usb2", "ti,omap-usb2";
 334                 reg = <0x0 0x4100000 0x0 0x54>;
 335                 syscon-phy-power = <&scm_conf 0x4000>;
 336                 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
 337                 clock-names = "wkupclk", "refclk";
 338                 #phy-cells = <0>;
 339         };
 340
 341         dwc3_1: dwc3@4020000 {
 342                 compatible = "ti,am654-dwc3";
 343                 reg = <0x0 0x4020000 0x0 0x4000>;
 344                 #address-cells = <1>;
 345                 #size-cells = <1>;
 346                 ranges = <0x0 0x0 0x4020000 0x20000>;
 347                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 348                 dma-coherent;
 349                 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
 350                 clocks = <&k3_clks 152 2>;
 351                 assigned-clocks = <&k3_clks 152 2>;
 352                 assigned-clock-parents = <&k3_clks 152 4>;      /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
 353
 354                 usb1: usb@10000 {
 355                         compatible = "snps,dwc3";
 356                         reg = <0x10000 0x10000>;
 357                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 358                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 359                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 360                         interrupt-names = "peripheral",
 361                                           "host",
 362                                           "otg";
 363                         maximum-speed = "high-speed";
 364                         dr_mode = "otg";
 365                         phys = <&usb1_phy>;
 366                         phy-names = "usb2-phy";
 367                 };
 368         };
 369
 370         usb1_phy: phy@4110000 {
 371                 compatible = "ti,am654-usb2", "ti,omap-usb2";
 372                 reg = <0x0 0x4110000 0x0 0x54>;
 373                 syscon-phy-power = <&scm_conf 0x4020>;
 374                 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
 375                 clock-names = "wkupclk", "refclk";
 376                 #phy-cells = <0>;
 377         };
 378
 379         intr_main_gpio: interrupt-controller0 {
 380                 compatible = "ti,sci-intr";
 381                 ti,intr-trigger-type = <1>;
 382                 interrupt-controller;
 383                 interrupt-parent = <&gic500>;
 384                 #interrupt-cells = <2>;
 385                 ti,sci = <&dmsc>;
 386                 ti,sci-dst-id = <56>;
 387                 ti,sci-rm-range-girq = <0x1>;
 388         };
 389
 390         cbass_main_navss: interconnect0 {
 391                 compatible = "simple-bus";
 392                 #address-cells = <2>;
 393                 #size-cells = <2>;
 394                 ranges;
 395
 396                 intr_main_navss: interrupt-controller1 {
 397                         compatible = "ti,sci-intr";
 398                         ti,intr-trigger-type = <4>;
 399                         interrupt-controller;
 400                         interrupt-parent = <&gic500>;
 401                         #interrupt-cells = <2>;
 402                         ti,sci = <&dmsc>;
 403                         ti,sci-dst-id = <56>;
 404                         ti,sci-rm-range-girq = <0x0>, <0x2>;
 405                 };
 406
 407                 inta_main_udmass: interrupt-controller@33d00000 {
 408                         compatible = "ti,sci-inta";
 409                         reg = <0x0 0x33d00000 0x0 0x100000>;
 410                         interrupt-controller;
 411                         interrupt-parent = <&intr_main_navss>;
 412                         msi-controller;
 413                         ti,sci = <&dmsc>;
 414                         ti,sci-dev-id = <179>;
 415                         ti,sci-rm-range-vint = <0x0>;
 416                         ti,sci-rm-range-global-event = <0x1>;
 417                 };
 418
 419                 hwspinlock: spinlock@30e00000 {
 420                         compatible = "ti,am654-hwspinlock";
 421                         reg = <0x00 0x30e00000 0x00 0x1000>;
 422                         #hwlock-cells = <1>;
 423                 };
 424         };
 425
 426         main_gpio0:  main_gpio0@600000 {
 427                 compatible = "ti,am654-gpio", "ti,keystone-gpio";
 428                 reg = <0x0 0x600000 0x0 0x100>;
 429                 gpio-controller;
 430                 #gpio-cells = <2>;
 431                 interrupt-parent = <&intr_main_gpio>;
 432                 interrupts = <57 256>, <57 257>, <57 258>, <57 259>, <57 260>,
 433                                 <57 261>;
 434                 interrupt-controller;
 435                 #interrupt-cells = <2>;
 436                 ti,ngpio = <96>;
 437                 ti,davinci-gpio-unbanked = <0>;
 438                 clocks = <&k3_clks 57 0>;
 439                 clock-names = "gpio";
 440         };
 441
 442         main_gpio1:  main_gpio1@601000 {
 443                 compatible = "ti,am654-gpio", "ti,keystone-gpio";
 444                 reg = <0x0 0x601000 0x0 0x100>;
 445                 gpio-controller;
 446                 #gpio-cells = <2>;
 447                 interrupt-parent = <&intr_main_gpio>;
 448                 interrupts = <58 256>, <58 257>, <58 258>, <58 259>, <58 260>,
 449                                 <58 261>;
 450                 interrupt-controller;
 451                 #interrupt-cells = <2>;
 452                 ti,ngpio = <90>;
 453                 ti,davinci-gpio-unbanked = <0>;
 454                 clocks = <&k3_clks 58 0>;
 455                 clock-names = "gpio";
 456         };
 457
 458         pcie0_rc: pcie@5500000 {
 459                 compatible = "ti,am654-pcie-rc";
 460                 reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
 461                 reg-names = "app", "dbics", "config", "atu";
 462                 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
 463                 #address-cells = <3>;
 464                 #size-cells = <2>;
 465                 ranges = <0x81000000 0 0          0x0 0x10020000 0 0x00010000
 466                           0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
 467                 ti,syscon-pcie-id = <&pcie_devid>;
 468                 ti,syscon-pcie-mode = <&pcie0_mode>;
 469                 bus-range = <0x0 0xff>;
 470                 num-viewport = <16>;
 471                 max-link-speed = <3>;
 472                 dma-coherent;
 473                 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
 474                 msi-map = <0x0 &gic_its 0x0 0x10000>;
 475         };
 476
 477         pcie0_ep: pcie-ep@5500000 {
 478                 compatible = "ti,am654-pcie-ep";
 479                 reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
 480                 reg-names = "app", "dbics", "addr_space", "atu";
 481                 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
 482                 ti,syscon-pcie-mode = <&pcie0_mode>;
 483                 num-ib-windows = <16>;
 484                 num-ob-windows = <16>;
 485                 max-link-speed = <3>;
 486                 dma-coherent;
 487                 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
 488         };
 489
 490         pcie1_rc: pcie@5600000 {
 491                 compatible = "ti,am654-pcie-rc";
 492                 reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
 493                 reg-names = "app", "dbics", "config", "atu";
 494                 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
 495                 #address-cells = <3>;
 496                 #size-cells = <2>;
 497                 ranges = <0x81000000 0 0          0x0   0x18020000 0 0x00010000
 498                           0x82000000 0 0x18030000 0x0   0x18030000 0 0x07FD0000>;
 499                 ti,syscon-pcie-id = <&pcie_devid>;
 500                 ti,syscon-pcie-mode = <&pcie1_mode>;
 501                 bus-range = <0x0 0xff>;
 502                 num-viewport = <16>;
 503                 max-link-speed = <3>;
 504                 dma-coherent;
 505                 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
 506                 msi-map = <0x0 &gic_its 0x10000 0x10000>;
 507         };
 508
 509         pcie1_ep: pcie-ep@5600000 {
 510                 compatible = "ti,am654-pcie-ep";
 511                 reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
 512                 reg-names = "app", "dbics", "addr_space", "atu";
 513                 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
 514                 ti,syscon-pcie-mode = <&pcie1_mode>;
 515                 num-ib-windows = <16>;
 516                 num-ob-windows = <16>;
 517                 max-link-speed = <3>;
 518                 dma-coherent;
 519                 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
 520         };
 521 };