1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
7 #include "k3-am642.dtsi"
17 device_type = "memory";
18 /* 1G RAM - default variant */
19 reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
28 secure_ddr: optee@9e800000 {
29 reg = <0x00 0x9e800000 0x00 0x01800000>;
34 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
35 compatible = "shared-dma-pool";
36 reg = <0x00 0xa0000000 0x00 0x100000>;
40 main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
41 compatible = "shared-dma-pool";
42 reg = <0x00 0xa0100000 0x00 0xf00000>;
46 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
47 compatible = "shared-dma-pool";
48 reg = <0x00 0xa1000000 0x00 0x100000>;
52 main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
53 compatible = "shared-dma-pool";
54 reg = <0x00 0xa1100000 0x00 0xf00000>;
58 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
59 compatible = "shared-dma-pool";
60 reg = <0x00 0xa2000000 0x00 0x100000>;
64 main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
65 compatible = "shared-dma-pool";
66 reg = <0x00 0xa2100000 0x00 0xf00000>;
70 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
71 compatible = "shared-dma-pool";
72 reg = <0x00 0xa3000000 0x00 0x100000>;
76 main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
77 compatible = "shared-dma-pool";
78 reg = <0x00 0xa3100000 0x00 0xf00000>;
82 rtos_ipc_memory_region: ipc-memories@a5000000 {
83 reg = <0x00 0xa5000000 0x00 0x00800000>;
89 reg_1v8: regulator-1v8 {
90 compatible = "regulator-fixed";
91 regulator-name = "V_1V8";
92 regulator-min-microvolt = <1800000>;
93 regulator-max-microvolt = <1800000>;
100 pinctrl-names = "default";
101 pinctrl-0 = <&main_i2c0_pins>;
102 clock-frequency = <400000>;
105 tmp1075: temperature-sensor@4a {
106 compatible = "ti,tmp1075";
108 vs-supply = <®_1v8>;
112 compatible = "st,24c02", "atmel,24c02";
114 vcc-supply = <®_1v8>;
120 compatible = "nxp,pcf85063a";
122 quartz-load-femtofarads = <12500>;
126 compatible = "st,24c64", "atmel,24c64";
128 vcc-supply = <®_1v8>;
136 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
137 ti,mbox-rx = <0 0 2>;
138 ti,mbox-tx = <1 0 2>;
141 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
142 ti,mbox-rx = <2 0 2>;
143 ti,mbox-tx = <3 0 2>;
150 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
151 ti,mbox-rx = <0 0 2>;
152 ti,mbox-tx = <1 0 2>;
155 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
156 ti,mbox-rx = <2 0 2>;
157 ti,mbox-tx = <3 0 2>;
164 mbox_m4_0: mbox-m4-0 {
165 ti,mbox-rx = <0 0 2>;
166 ti,mbox-tx = <1 0 2>;
171 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
172 memory-region = <&main_r5fss0_core0_dma_memory_region>,
173 <&main_r5fss0_core0_memory_region>;
177 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
178 memory-region = <&main_r5fss0_core1_dma_memory_region>,
179 <&main_r5fss0_core1_memory_region>;
183 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
184 memory-region = <&main_r5fss1_core0_dma_memory_region>,
185 <&main_r5fss1_core0_memory_region>;
189 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
190 memory-region = <&main_r5fss1_core1_dma_memory_region>,
191 <&main_r5fss1_core1_memory_region>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&ospi0_pins>;
200 compatible = "jedec,spi-nor";
202 spi-tx-bus-width = <8>;
203 spi-rx-bus-width = <8>;
204 spi-max-frequency = <84000000>;
205 cdns,tshsl-ns = <60>;
206 cdns,tsd2d-ns = <60>;
207 cdns,tchsh-ns = <60>;
208 cdns,tslch-ns = <60>;
209 cdns,read-delay = <2>;
212 compatible = "fixed-partitions";
213 #address-cells = <1>;
216 /* Filled by bootloader */
226 ti,driver-strength-ohm = <50>;
230 main_i2c0_pins: main-i2c0-pins {
231 pinctrl-single,pins = <
233 AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0)
235 AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0)
239 ospi0_pins: ospi0-pins {
240 pinctrl-single,pins = <
241 /* (N20) OSPI0_CLK */
242 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0)
243 /* (L19) OSPI0_CSn0 */
244 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0)
246 AM64X_IOPAD(0x000c, PIN_INPUT, 0)
248 AM64X_IOPAD(0x0010, PIN_INPUT, 0)
250 AM64X_IOPAD(0x0014, PIN_INPUT, 0)
252 AM64X_IOPAD(0x0018, PIN_INPUT, 0)
254 AM64X_IOPAD(0x001c, PIN_INPUT, 0)
256 AM64X_IOPAD(0x0020, PIN_INPUT, 0)
258 AM64X_IOPAD(0x0024, PIN_INPUT, 0)
260 AM64X_IOPAD(0x0028, PIN_INPUT, 0)
261 /* (N19) OSPI0_DQS */
262 AM64X_IOPAD(0x0008, PIN_INPUT, 0)