1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for the AM62P main domain peripherals
4 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
8 oc_sram: sram@70000000 {
9 compatible = "mmio-sram";
10 reg = <0x00 0x70000000 0x00 0x10000>;
13 ranges = <0x00 0x00 0x70000000 0x10000>;
16 gic500: interrupt-controller@1800000 {
17 compatible = "arm,gic-v3";
21 #interrupt-cells = <3>;
23 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
24 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
25 <0x01 0x00000000 0x00 0x2000>, /* GICC */
26 <0x01 0x00010000 0x00 0x1000>, /* GICH */
27 <0x01 0x00020000 0x00 0x2000>; /* GICV */
30 * virtual CPU interface maintenance interrupt
32 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
34 gic_its: msi-controller@1820000 {
35 compatible = "arm,gic-v3-its";
36 reg = <0x00 0x01820000 0x00 0x10000>;
37 socionext,synquacer-pre-its = <0x1000000 0x400000>;
43 main_conf: bus@100000 {
44 compatible = "simple-bus";
45 reg = <0x00 0x00100000 0x00 0x20000>;
48 ranges = <0x00 0x00 0x00100000 0x20000>;
50 phy_gmii_sel: phy@4044 {
51 compatible = "ti,am654-phy-gmii-sel";
56 epwm_tbclk: clock-controller@4130 {
57 compatible = "ti,am62-epwm-tbclk";
64 compatible = "simple-bus";
68 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
73 secure_proxy_main: mailbox@4d000000 {
74 compatible = "ti,am654-secure-proxy";
76 reg-names = "target_data", "rt", "scfg";
77 reg = <0x00 0x4d000000 0x00 0x80000>,
78 <0x00 0x4a600000 0x00 0x80000>,
79 <0x00 0x4a400000 0x00 0x80000>;
80 interrupt-names = "rx_012";
81 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
85 inta_main_dmss: interrupt-controller@48000000 {
86 compatible = "ti,sci-inta";
87 reg = <0x00 0x48000000 0x00 0x100000>;
88 #interrupt-cells = <0>;
90 interrupt-parent = <&gic500>;
94 ti,interrupt-ranges = <5 69 35>;
95 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
98 main_bcdma: dma-controller@485c0100 {
99 compatible = "ti,am64-dmss-bcdma";
100 reg = <0x00 0x485c0100 0x00 0x100>,
101 <0x00 0x4c000000 0x00 0x20000>,
102 <0x00 0x4a820000 0x00 0x20000>,
103 <0x00 0x4aa40000 0x00 0x20000>,
104 <0x00 0x4bc00000 0x00 0x100000>;
105 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
106 msi-parent = <&inta_main_dmss>;
110 ti,sci-dev-id = <26>;
111 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
112 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
113 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
117 main_pktdma: dma-controller@485c0000 {
118 compatible = "ti,am64-dmss-pktdma";
119 reg = <0x00 0x485c0000 0x00 0x100>,
120 <0x00 0x4a800000 0x00 0x20000>,
121 <0x00 0x4aa00000 0x00 0x40000>,
122 <0x00 0x4b800000 0x00 0x400000>;
123 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
124 msi-parent = <&inta_main_dmss>;
129 ti,sci-dev-id = <30>;
130 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
131 <0x24>, /* CPSW_TX_CHAN */
132 <0x25>, /* SAUL_TX_0_CHAN */
133 <0x26>; /* SAUL_TX_1_CHAN */
134 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
135 <0x11>, /* RING_CPSW_TX_CHAN */
136 <0x12>, /* RING_SAUL_TX_0_CHAN */
137 <0x13>; /* RING_SAUL_TX_1_CHAN */
138 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
139 <0x2b>, /* CPSW_RX_CHAN */
140 <0x2d>, /* SAUL_RX_0_CHAN */
141 <0x2f>, /* SAUL_RX_1_CHAN */
142 <0x31>, /* SAUL_RX_2_CHAN */
143 <0x33>; /* SAUL_RX_3_CHAN */
144 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
145 <0x2c>, /* FLOW_CPSW_RX_CHAN */
146 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
147 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
151 dmsc: system-controller@44043000 {
152 compatible = "ti,k2g-sci";
154 mbox-names = "rx", "tx";
155 mboxes = <&secure_proxy_main 12>,
156 <&secure_proxy_main 13>;
157 reg-names = "debug_messages";
158 reg = <0x00 0x44043000 0x00 0xfe0>;
161 k3_pds: power-controller {
162 compatible = "ti,sci-pm-domain";
163 #power-domain-cells = <2>;
167 k3_clks: clock-controller {
168 compatible = "ti,k2g-sci-clk";
173 k3_reset: reset-controller {
174 compatible = "ti,sci-reset";
180 crypto: crypto@40900000 {
181 compatible = "ti,am62-sa3ul";
182 reg = <0x00 0x40900000 0x00 0x1200>;
183 #address-cells = <2>;
185 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
187 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
188 <&main_pktdma 0x7507 0>;
189 dma-names = "tx", "rx1", "rx2";
192 secure_proxy_sa3: mailbox@43600000 {
193 compatible = "ti,am654-secure-proxy";
195 reg-names = "target_data", "rt", "scfg";
196 reg = <0x00 0x43600000 0x00 0x10000>,
197 <0x00 0x44880000 0x00 0x20000>,
198 <0x00 0x44860000 0x00 0x20000>;
201 * Node is incomplete as it is meant for bootloaders and
202 * firmware on non-MPU processors
208 main_pmx0: pinctrl@f4000 {
209 compatible = "pinctrl-single";
210 reg = <0x00 0xf4000 0x00 0x2ac>;
211 #pinctrl-cells = <1>;
212 pinctrl-single,register-width = <32>;
213 pinctrl-single,function-mask = <0xffffffff>;
217 main_esm: esm@420000 {
218 compatible = "ti,j721e-esm";
219 reg = <0x00 0x420000 0x00 0x1000>;
220 ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
224 main_timer0: timer@2400000 {
225 compatible = "ti,am654-timer";
226 reg = <0x00 0x2400000 0x00 0x400>;
227 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&k3_clks 36 2>;
230 assigned-clocks = <&k3_clks 36 2>;
231 assigned-clock-parents = <&k3_clks 36 3>;
232 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
237 main_timer1: timer@2410000 {
238 compatible = "ti,am654-timer";
239 reg = <0x00 0x2410000 0x00 0x400>;
240 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&k3_clks 37 2>;
243 assigned-clocks = <&k3_clks 37 2>;
244 assigned-clock-parents = <&k3_clks 37 3>;
245 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
249 main_timer2: timer@2420000 {
250 compatible = "ti,am654-timer";
251 reg = <0x00 0x2420000 0x00 0x400>;
252 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&k3_clks 38 2>;
255 assigned-clocks = <&k3_clks 38 2>;
256 assigned-clock-parents = <&k3_clks 38 3>;
257 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
261 main_timer3: timer@2430000 {
262 compatible = "ti,am654-timer";
263 reg = <0x00 0x2430000 0x00 0x400>;
264 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
265 clocks = <&k3_clks 39 2>;
267 assigned-clocks = <&k3_clks 39 2>;
268 assigned-clock-parents = <&k3_clks 39 3>;
269 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
273 main_timer4: timer@2440000 {
274 compatible = "ti,am654-timer";
275 reg = <0x00 0x2440000 0x00 0x400>;
276 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&k3_clks 40 2>;
279 assigned-clocks = <&k3_clks 40 2>;
280 assigned-clock-parents = <&k3_clks 40 3>;
281 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
285 main_timer5: timer@2450000 {
286 compatible = "ti,am654-timer";
287 reg = <0x00 0x2450000 0x00 0x400>;
288 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&k3_clks 41 2>;
291 assigned-clocks = <&k3_clks 41 2>;
292 assigned-clock-parents = <&k3_clks 41 3>;
293 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
297 main_timer6: timer@2460000 {
298 compatible = "ti,am654-timer";
299 reg = <0x00 0x2460000 0x00 0x400>;
300 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&k3_clks 42 2>;
303 assigned-clocks = <&k3_clks 42 2>;
304 assigned-clock-parents = <&k3_clks 42 3>;
305 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
309 main_timer7: timer@2470000 {
310 compatible = "ti,am654-timer";
311 reg = <0x00 0x2470000 0x00 0x400>;
312 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&k3_clks 43 2>;
315 assigned-clocks = <&k3_clks 43 2>;
316 assigned-clock-parents = <&k3_clks 43 3>;
317 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
321 main_uart0: serial@2800000 {
322 compatible = "ti,am64-uart", "ti,am654-uart";
323 reg = <0x00 0x02800000 0x00 0x100>;
324 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
325 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
326 clocks = <&k3_clks 146 0>;
327 clock-names = "fclk";
331 main_uart1: serial@2810000 {
332 compatible = "ti,am64-uart", "ti,am654-uart";
333 reg = <0x00 0x02810000 0x00 0x100>;
334 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
335 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
336 clocks = <&k3_clks 152 0>;
337 clock-names = "fclk";
341 main_uart2: serial@2820000 {
342 compatible = "ti,am64-uart", "ti,am654-uart";
343 reg = <0x00 0x02820000 0x00 0x100>;
344 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
345 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
346 clocks = <&k3_clks 153 0>;
347 clock-names = "fclk";
351 main_uart3: serial@2830000 {
352 compatible = "ti,am64-uart", "ti,am654-uart";
353 reg = <0x00 0x02830000 0x00 0x100>;
354 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
355 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
356 clocks = <&k3_clks 154 0>;
357 clock-names = "fclk";
361 main_uart4: serial@2840000 {
362 compatible = "ti,am64-uart", "ti,am654-uart";
363 reg = <0x00 0x02840000 0x00 0x100>;
364 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
365 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
366 clocks = <&k3_clks 155 0>;
367 clock-names = "fclk";
371 main_uart5: serial@2850000 {
372 compatible = "ti,am64-uart", "ti,am654-uart";
373 reg = <0x00 0x02850000 0x00 0x100>;
374 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
375 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
376 clocks = <&k3_clks 156 0>;
377 clock-names = "fclk";
381 main_uart6: serial@2860000 {
382 compatible = "ti,am64-uart", "ti,am654-uart";
383 reg = <0x00 0x02860000 0x00 0x100>;
384 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
385 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
386 clocks = <&k3_clks 158 0>;
387 clock-names = "fclk";
391 main_i2c0: i2c@20000000 {
392 compatible = "ti,am64-i2c", "ti,omap4-i2c";
393 reg = <0x00 0x20000000 0x00 0x100>;
394 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
395 #address-cells = <1>;
397 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
398 clocks = <&k3_clks 102 2>;
403 main_i2c1: i2c@20010000 {
404 compatible = "ti,am64-i2c", "ti,omap4-i2c";
405 reg = <0x00 0x20010000 0x00 0x100>;
406 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
407 #address-cells = <1>;
409 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
410 clocks = <&k3_clks 103 2>;
415 main_i2c2: i2c@20020000 {
416 compatible = "ti,am64-i2c", "ti,omap4-i2c";
417 reg = <0x00 0x20020000 0x00 0x100>;
418 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
419 #address-cells = <1>;
421 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
422 clocks = <&k3_clks 104 2>;
427 main_i2c3: i2c@20030000 {
428 compatible = "ti,am64-i2c", "ti,omap4-i2c";
429 reg = <0x00 0x20030000 0x00 0x100>;
430 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
431 #address-cells = <1>;
433 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
434 clocks = <&k3_clks 105 2>;
439 main_spi0: spi@20100000 {
440 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
441 reg = <0x00 0x20100000 0x00 0x400>;
442 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
443 #address-cells = <1>;
445 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
446 clocks = <&k3_clks 141 0>;
450 main_spi1: spi@20110000 {
451 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
452 reg = <0x00 0x20110000 0x00 0x400>;
453 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
454 #address-cells = <1>;
456 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
457 clocks = <&k3_clks 142 0>;
461 main_spi2: spi@20120000 {
462 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
463 reg = <0x00 0x20120000 0x00 0x400>;
464 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
465 #address-cells = <1>;
467 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
468 clocks = <&k3_clks 143 0>;
472 main_gpio_intr: interrupt-controller@a00000 {
473 compatible = "ti,sci-intr";
474 reg = <0x00 0x00a00000 0x00 0x800>;
475 ti,intr-trigger-type = <1>;
476 interrupt-controller;
477 interrupt-parent = <&gic500>;
478 #interrupt-cells = <1>;
481 ti,interrupt-ranges = <0 32 16>;
484 main_gpio0: gpio@600000 {
485 compatible = "ti,am64-gpio", "ti,keystone-gpio";
486 reg = <0x00 0x00600000 0x00 0x100>;
489 interrupt-parent = <&main_gpio_intr>;
490 interrupts = <190>, <191>, <192>,
492 interrupt-controller;
493 #interrupt-cells = <2>;
495 ti,davinci-gpio-unbanked = <0>;
496 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
497 clocks = <&k3_clks 77 0>;
498 clock-names = "gpio";
501 main_gpio1: gpio@601000 {
502 compatible = "ti,am64-gpio", "ti,keystone-gpio";
503 reg = <0x00 0x00601000 0x00 0x100>;
506 interrupt-parent = <&main_gpio_intr>;
507 interrupts = <180>, <181>, <182>,
509 interrupt-controller;
510 #interrupt-cells = <2>;
512 ti,davinci-gpio-unbanked = <0>;
513 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
514 clocks = <&k3_clks 78 0>;
515 clock-names = "gpio";
518 sdhci0: mmc@fa10000 {
519 compatible = "ti,am64-sdhci-8bit";
520 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
521 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
522 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
523 clocks = <&k3_clks 57 1>, <&k3_clks 57 2>;
524 clock-names = "clk_ahb", "clk_xin";
525 assigned-clocks = <&k3_clks 57 2>;
526 assigned-clock-parents = <&k3_clks 57 4>;
527 ti,otap-del-sel-legacy = <0x0>;
531 sdhci1: mmc@fa00000 {
532 compatible = "ti,am62-sdhci";
533 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
534 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
535 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
536 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
537 clock-names = "clk_ahb", "clk_xin";
538 ti,otap-del-sel-legacy = <0x8>;
542 sdhci2: mmc@fa20000 {
543 compatible = "ti,am62-sdhci";
544 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
545 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
546 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
547 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
548 clock-names = "clk_ahb", "clk_xin";
549 ti,otap-del-sel-legacy = <0x8>;
554 compatible = "simple-bus";
555 reg = <0x00 0x0fc00000 0x00 0x70000>;
556 #address-cells = <2>;
561 compatible = "ti,am654-ospi", "cdns,qspi-nor";
562 reg = <0x00 0x0fc40000 0x00 0x100>,
563 <0x05 0x00000000 0x01 0x00000000>;
564 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
565 cdns,fifo-depth = <256>;
566 cdns,fifo-width = <4>;
567 cdns,trigger-address = <0x0>;
568 clocks = <&k3_clks 75 7>;
569 assigned-clocks = <&k3_clks 75 7>;
570 assigned-clock-parents = <&k3_clks 75 8>;
571 assigned-clock-rates = <166666666>;
572 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
573 #address-cells = <1>;
579 cpsw3g: ethernet@8000000 {
580 compatible = "ti,am642-cpsw-nuss";
581 #address-cells = <2>;
583 reg = <0x00 0x08000000 0x00 0x200000>;
584 reg-names = "cpsw_nuss";
585 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
586 clocks = <&k3_clks 13 0>;
587 assigned-clocks = <&k3_clks 13 3>;
588 assigned-clock-parents = <&k3_clks 13 11>;
590 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
592 dmas = <&main_pktdma 0xc600 15>,
593 <&main_pktdma 0xc601 15>,
594 <&main_pktdma 0xc602 15>,
595 <&main_pktdma 0xc603 15>,
596 <&main_pktdma 0xc604 15>,
597 <&main_pktdma 0xc605 15>,
598 <&main_pktdma 0xc606 15>,
599 <&main_pktdma 0xc607 15>,
600 <&main_pktdma 0x4600 15>;
601 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
605 #address-cells = <1>;
612 phys = <&phy_gmii_sel 1>;
613 mac-address = [00 00 00 00 00 00];
620 phys = <&phy_gmii_sel 2>;
621 mac-address = [00 00 00 00 00 00];
625 cpsw3g_mdio: mdio@f00 {
626 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
627 reg = <0x00 0xf00 0x00 0x100>;
628 #address-cells = <1>;
630 clocks = <&k3_clks 13 0>;
632 bus_freq = <1000000>;
637 compatible = "ti,j721e-cpts";
638 reg = <0x00 0x3d000 0x00 0x400>;
639 clocks = <&k3_clks 13 3>;
640 clock-names = "cpts";
641 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
642 interrupt-names = "cpts";
643 ti,cpts-ext-ts-inputs = <4>;
644 ti,cpts-periodic-outputs = <2>;
648 hwspinlock: spinlock@2a000000 {
649 compatible = "ti,am64-hwspinlock";
650 reg = <0x00 0x2a000000 0x00 0x1000>;
654 mailbox0_cluster0: mailbox@29000000 {
655 compatible = "ti,am64-mailbox";
656 reg = <0x00 0x29000000 0x00 0x200>;
657 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
659 ti,mbox-num-users = <4>;
660 ti,mbox-num-fifos = <16>;
663 mailbox0_cluster1: mailbox@29010000 {
664 compatible = "ti,am64-mailbox";
665 reg = <0x00 0x29010000 0x00 0x200>;
666 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
668 ti,mbox-num-users = <4>;
669 ti,mbox-num-fifos = <16>;
672 mailbox0_cluster2: mailbox@29020000 {
673 compatible = "ti,am64-mailbox";
674 reg = <0x00 0x29020000 0x00 0x200>;
675 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
677 ti,mbox-num-users = <4>;
678 ti,mbox-num-fifos = <16>;
681 mailbox0_cluster3: mailbox@29030000 {
682 compatible = "ti,am64-mailbox";
683 reg = <0x00 0x29030000 0x00 0x200>;
684 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
686 ti,mbox-num-users = <4>;
687 ti,mbox-num-fifos = <16>;
690 ecap0: pwm@23100000 {
691 compatible = "ti,am3352-ecap";
693 reg = <0x00 0x23100000 0x00 0x100>;
694 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
695 clocks = <&k3_clks 51 0>;
700 ecap1: pwm@23110000 {
701 compatible = "ti,am3352-ecap";
703 reg = <0x00 0x23110000 0x00 0x100>;
704 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
705 clocks = <&k3_clks 52 0>;
710 ecap2: pwm@23120000 {
711 compatible = "ti,am3352-ecap";
713 reg = <0x00 0x23120000 0x00 0x100>;
714 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
715 clocks = <&k3_clks 53 0>;
720 main_mcan0: can@20701000 {
721 compatible = "bosch,m_can";
722 reg = <0x00 0x20701000 0x00 0x200>,
723 <0x00 0x20708000 0x00 0x8000>;
724 reg-names = "m_can", "message_ram";
725 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
726 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
727 clock-names = "hclk", "cclk";
728 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
729 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
730 interrupt-names = "int0", "int1";
731 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
735 main_mcan1: can@20711000 {
736 compatible = "bosch,m_can";
737 reg = <0x00 0x20711000 0x00 0x200>,
738 <0x00 0x20718000 0x00 0x8000>;
739 reg-names = "m_can", "message_ram";
740 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
741 clocks = <&k3_clks 99 6>, <&k3_clks 99 1>;
742 clock-names = "hclk", "cclk";
743 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
745 interrupt-names = "int0", "int1";
746 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
750 main_rti0: watchdog@e000000 {
751 compatible = "ti,j7-rti-wdt";
752 reg = <0x00 0x0e000000 0x00 0x100>;
753 clocks = <&k3_clks 125 0>;
754 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
755 assigned-clocks = <&k3_clks 125 0>;
756 assigned-clock-parents = <&k3_clks 125 2>;
759 main_rti1: watchdog@e010000 {
760 compatible = "ti,j7-rti-wdt";
761 reg = <0x00 0x0e010000 0x00 0x100>;
762 clocks = <&k3_clks 126 0>;
763 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
764 assigned-clocks = <&k3_clks 126 0>;
765 assigned-clock-parents = <&k3_clks 126 2>;
768 main_rti2: watchdog@e020000 {
769 compatible = "ti,j7-rti-wdt";
770 reg = <0x00 0x0e020000 0x00 0x100>;
771 clocks = <&k3_clks 127 0>;
772 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>;
773 assigned-clocks = <&k3_clks 127 0>;
774 assigned-clock-parents = <&k3_clks 127 2>;
777 main_rti3: watchdog@e030000 {
778 compatible = "ti,j7-rti-wdt";
779 reg = <0x00 0x0e030000 0x00 0x100>;
780 clocks = <&k3_clks 128 0>;
781 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>;
782 assigned-clocks = <&k3_clks 128 0>;
783 assigned-clock-parents = <&k3_clks 128 2>;
786 main_rti15: watchdog@e0f0000 {
787 compatible = "ti,j7-rti-wdt";
788 reg = <0x00 0x0e0f0000 0x00 0x100>;
789 clocks = <&k3_clks 130 0>;
790 power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>;
791 assigned-clocks = <&k3_clks 130 0>;
792 assigned-clock-parents = <&k3_clks 130 2>;
795 epwm0: pwm@23000000 {
796 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
798 reg = <0x00 0x23000000 0x00 0x100>;
799 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
800 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
801 clock-names = "tbclk", "fck";
805 epwm1: pwm@23010000 {
806 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
808 reg = <0x00 0x23010000 0x00 0x100>;
809 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
810 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
811 clock-names = "tbclk", "fck";
815 epwm2: pwm@23020000 {
816 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
818 reg = <0x00 0x23020000 0x00 0x100>;
819 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
820 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
821 clock-names = "tbclk", "fck";
825 mcasp0: audio-controller@2b00000 {
826 compatible = "ti,am33xx-mcasp-audio";
827 reg = <0x00 0x02b00000 0x00 0x2000>,
828 <0x00 0x02b08000 0x00 0x400>;
829 reg-names = "mpu", "dat";
830 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
831 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
832 interrupt-names = "tx", "rx";
834 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
835 dma-names = "tx", "rx";
837 clocks = <&k3_clks 190 0>;
839 assigned-clocks = <&k3_clks 190 0>;
840 assigned-clock-parents = <&k3_clks 190 2>;
841 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
845 mcasp1: audio-controller@2b10000 {
846 compatible = "ti,am33xx-mcasp-audio";
847 reg = <0x00 0x02b10000 0x00 0x2000>,
848 <0x00 0x02b18000 0x00 0x400>;
849 reg-names = "mpu", "dat";
850 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
851 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
852 interrupt-names = "tx", "rx";
854 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
855 dma-names = "tx", "rx";
857 clocks = <&k3_clks 191 0>;
859 assigned-clocks = <&k3_clks 191 0>;
860 assigned-clock-parents = <&k3_clks 191 2>;
861 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
865 mcasp2: audio-controller@2b20000 {
866 compatible = "ti,am33xx-mcasp-audio";
867 reg = <0x00 0x02b20000 0x00 0x2000>,
868 <0x00 0x02b28000 0x00 0x400>;
869 reg-names = "mpu", "dat";
870 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
871 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
872 interrupt-names = "tx", "rx";
874 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
875 dma-names = "tx", "rx";
877 clocks = <&k3_clks 192 0>;
879 assigned-clocks = <&k3_clks 192 0>;
880 assigned-clock-parents = <&k3_clks 192 2>;
881 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;