1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2015 Marvell Technology Group Ltd.
5 * Author: Jisheng Zhang <jszhang@marvell.com>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "marvell,berlin4ct", "marvell,berlin";
12 interrupt-parent = <&gic>;
21 compatible = "arm,psci-1.0", "arm,psci-0.2";
30 compatible = "arm,cortex-a53";
33 enable-method = "psci";
34 next-level-cache = <&l2>;
35 cpu-idle-states = <&CPU_SLEEP_0>;
39 compatible = "arm,cortex-a53";
42 enable-method = "psci";
43 next-level-cache = <&l2>;
44 cpu-idle-states = <&CPU_SLEEP_0>;
48 compatible = "arm,cortex-a53";
51 enable-method = "psci";
52 next-level-cache = <&l2>;
53 cpu-idle-states = <&CPU_SLEEP_0>;
57 compatible = "arm,cortex-a53";
60 enable-method = "psci";
61 next-level-cache = <&l2>;
62 cpu-idle-states = <&CPU_SLEEP_0>;
72 entry-method = "psci";
73 CPU_SLEEP_0: cpu-sleep-0 {
74 compatible = "arm,idle-state";
76 arm,psci-suspend-param = <0x0010000>;
77 entry-latency-us = <75>;
78 exit-latency-us = <155>;
79 min-residency-us = <1000>;
85 compatible = "fixed-clock";
87 clock-frequency = <25000000>;
91 compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
92 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
96 interrupt-affinity = <&cpu0>,
103 compatible = "arm,armv8-timer";
104 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
105 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
106 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
107 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
111 compatible = "simple-bus";
112 #address-cells = <1>;
114 ranges = <0 0 0xf7000000 0x1000000>;
116 gic: interrupt-controller@901000 {
117 compatible = "arm,gic-400";
118 #interrupt-cells = <3>;
119 interrupt-controller;
120 reg = <0x901000 0x1000>,
124 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
128 compatible = "simple-bus";
129 #address-cells = <1>;
132 ranges = <0 0xe80000 0x10000>;
133 interrupt-parent = <&aic>;
136 compatible = "snps,dw-apb-gpio";
137 reg = <0x0400 0x400>;
138 #address-cells = <1>;
142 compatible = "snps,dw-apb-gpio-port";
147 interrupt-controller;
148 #interrupt-cells = <2>;
154 compatible = "snps,dw-apb-gpio";
155 reg = <0x0800 0x400>;
156 #address-cells = <1>;
160 compatible = "snps,dw-apb-gpio-port";
165 interrupt-controller;
166 #interrupt-cells = <2>;
172 compatible = "snps,dw-apb-gpio";
173 reg = <0x0c00 0x400>;
174 #address-cells = <1>;
178 compatible = "snps,dw-apb-gpio-port";
183 interrupt-controller;
184 #interrupt-cells = <2>;
190 compatible = "snps,dw-apb-gpio";
191 reg = <0x1000 0x400>;
192 #address-cells = <1>;
196 compatible = "snps,dw-apb-gpio-port";
201 interrupt-controller;
202 #interrupt-cells = <2>;
207 aic: interrupt-controller@3800 {
208 compatible = "snps,dw-apb-ictl";
210 interrupt-controller;
211 #interrupt-cells = <1>;
212 interrupt-parent = <&gic>;
213 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
217 soc_pinctrl: pin-controller@ea8000 {
218 compatible = "marvell,berlin4ct-soc-pinctrl";
219 reg = <0xea8000 0x14>;
222 avio_pinctrl: pin-controller@ea8400 {
223 compatible = "marvell,berlin4ct-avio-pinctrl";
224 reg = <0xea8400 0x8>;
228 compatible = "simple-bus";
229 #address-cells = <1>;
231 ranges = <0 0xfc0000 0x10000>;
232 interrupt-parent = <&sic>;
234 sic: interrupt-controller@1000 {
235 compatible = "snps,dw-apb-ictl";
237 interrupt-controller;
238 #interrupt-cells = <1>;
239 interrupt-parent = <&gic>;
240 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
243 wdt0: watchdog@3000 {
244 compatible = "snps,dw-wdt";
245 reg = <0x3000 0x100>;
250 wdt1: watchdog@4000 {
251 compatible = "snps,dw-wdt";
252 reg = <0x4000 0x100>;
257 wdt2: watchdog@5000 {
258 compatible = "snps,dw-wdt";
259 reg = <0x5000 0x100>;
264 sm_gpio0: gpio@8000 {
265 compatible = "snps,dw-apb-gpio";
266 reg = <0x8000 0x400>;
267 #address-cells = <1>;
271 compatible = "snps,dw-apb-gpio-port";
279 sm_gpio1: gpio@9000 {
280 compatible = "snps,dw-apb-gpio";
281 reg = <0x9000 0x400>;
282 #address-cells = <1>;
286 compatible = "snps,dw-apb-gpio-port";
295 compatible = "snps,dw-apb-uart";
296 reg = <0xd000 0x100>;
301 pinctrl-0 = <&uart0_pmux>;
302 pinctrl-names = "default";
306 system_pinctrl: pin-controller@fe2200 {
307 compatible = "marvell,berlin4ct-system-pinctrl";
308 reg = <0xfe2200 0xc>;
310 uart0_pmux: uart0-pmux {
311 groups = "SM_URT0_TXD", "SM_URT0_RXD";