arch/arm64/boot/dts/synaptics/berlin4ct.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (C) 2015 Marvell Technology Group Ltd.
   4  *
   5  * Author: Jisheng Zhang <jszhang@marvell.com>
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9
  10 / {
  11         compatible = "marvell,berlin4ct", "marvell,berlin";
  12         interrupt-parent = <&gic>;
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         aliases {
  17                 serial0 = &uart0;
  18         };
  19
  20         psci {
  21                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  22                 method = "smc";
  23         };
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 cpu0: cpu@0 {
  30                         compatible = "arm,cortex-a53";
  31                         device_type = "cpu";
  32                         reg = <0x0>;
  33                         enable-method = "psci";
  34                         next-level-cache = <&l2>;
  35                         cpu-idle-states = <&CPU_SLEEP_0>;
  36                 };
  37
  38                 cpu1: cpu@1 {
  39                         compatible = "arm,cortex-a53";
  40                         device_type = "cpu";
  41                         reg = <0x1>;
  42                         enable-method = "psci";
  43                         next-level-cache = <&l2>;
  44                         cpu-idle-states = <&CPU_SLEEP_0>;
  45                 };
  46
  47                 cpu2: cpu@2 {
  48                         compatible = "arm,cortex-a53";
  49                         device_type = "cpu";
  50                         reg = <0x2>;
  51                         enable-method = "psci";
  52                         next-level-cache = <&l2>;
  53                         cpu-idle-states = <&CPU_SLEEP_0>;
  54                 };
  55
  56                 cpu3: cpu@3 {
  57                         compatible = "arm,cortex-a53";
  58                         device_type = "cpu";
  59                         reg = <0x3>;
  60                         enable-method = "psci";
  61                         next-level-cache = <&l2>;
  62                         cpu-idle-states = <&CPU_SLEEP_0>;
  63                 };
  64
  65                 l2: cache {
  66                         compatible = "cache";
  67                         cache-level = <2>;
  68                         cache-unified;
  69                 };
  70
  71                 idle-states {
  72                         entry-method = "psci";
  73                         CPU_SLEEP_0: cpu-sleep-0 {
  74                                 compatible = "arm,idle-state";
  75                                 local-timer-stop;
  76                                 arm,psci-suspend-param = <0x0010000>;
  77                                 entry-latency-us = <75>;
  78                                 exit-latency-us = <155>;
  79                                 min-residency-us = <1000>;
  80                         };
  81                 };
  82         };
  83
  84         osc: osc {
  85                 compatible = "fixed-clock";
  86                 #clock-cells = <0>;
  87                 clock-frequency = <25000000>;
  88         };
  89
  90         pmu {
  91                 compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
  92                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
  93                              <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
  94                              <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
  95                              <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  96                 interrupt-affinity = <&cpu0>,
  97                                      <&cpu1>,
  98                                      <&cpu2>,
  99                                      <&cpu3>;
 100         };
 101
 102         timer {
 103                 compatible = "arm,armv8-timer";
 104                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 105                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 106                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 107                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 108         };
 109
 110         soc@f7000000 {
 111                 compatible = "simple-bus";
 112                 #address-cells = <1>;
 113                 #size-cells = <1>;
 114                 ranges = <0 0 0xf7000000 0x1000000>;
 115
 116                 gic: interrupt-controller@901000 {
 117                         compatible = "arm,gic-400";
 118                         #interrupt-cells = <3>;
 119                         interrupt-controller;
 120                         reg = <0x901000 0x1000>,
 121                               <0x902000 0x2000>,
 122                               <0x904000 0x2000>,
 123                               <0x906000 0x2000>;
 124                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 125                 };
 126
 127                 apb@e80000 {
 128                         compatible = "simple-bus";
 129                         #address-cells = <1>;
 130                         #size-cells = <1>;
 131
 132                         ranges = <0 0xe80000 0x10000>;
 133                         interrupt-parent = <&aic>;
 134
 135                         gpio0: gpio@400 {
 136                                 compatible = "snps,dw-apb-gpio";
 137                                 reg = <0x0400 0x400>;
 138                                 #address-cells = <1>;
 139                                 #size-cells = <0>;
 140
 141                                 porta: gpio-port@0 {
 142                                         compatible = "snps,dw-apb-gpio-port";
 143                                         gpio-controller;
 144                                         #gpio-cells = <2>;
 145                                         ngpios = <32>;
 146                                         reg = <0>;
 147                                         interrupt-controller;
 148                                         #interrupt-cells = <2>;
 149                                         interrupts = <0>;
 150                                 };
 151                         };
 152
 153                         gpio1: gpio@800 {
 154                                 compatible = "snps,dw-apb-gpio";
 155                                 reg = <0x0800 0x400>;
 156                                 #address-cells = <1>;
 157                                 #size-cells = <0>;
 158
 159                                 portb: gpio-port@1 {
 160                                         compatible = "snps,dw-apb-gpio-port";
 161                                         gpio-controller;
 162                                         #gpio-cells = <2>;
 163                                         ngpios = <32>;
 164                                         reg = <0>;
 165                                         interrupt-controller;
 166                                         #interrupt-cells = <2>;
 167                                         interrupts = <1>;
 168                                 };
 169                         };
 170
 171                         gpio2: gpio@c00 {
 172                                 compatible = "snps,dw-apb-gpio";
 173                                 reg = <0x0c00 0x400>;
 174                                 #address-cells = <1>;
 175                                 #size-cells = <0>;
 176
 177                                 portc: gpio-port@2 {
 178                                         compatible = "snps,dw-apb-gpio-port";
 179                                         gpio-controller;
 180                                         #gpio-cells = <2>;
 181                                         ngpios = <32>;
 182                                         reg = <0>;
 183                                         interrupt-controller;
 184                                         #interrupt-cells = <2>;
 185                                         interrupts = <2>;
 186                                 };
 187                         };
 188
 189                         gpio3: gpio@1000 {
 190                                 compatible = "snps,dw-apb-gpio";
 191                                 reg = <0x1000 0x400>;
 192                                 #address-cells = <1>;
 193                                 #size-cells = <0>;
 194
 195                                 portd: gpio-port@3 {
 196                                         compatible = "snps,dw-apb-gpio-port";
 197                                         gpio-controller;
 198                                         #gpio-cells = <2>;
 199                                         ngpios = <32>;
 200                                         reg = <0>;
 201                                         interrupt-controller;
 202                                         #interrupt-cells = <2>;
 203                                         interrupts = <3>;
 204                                 };
 205                         };
 206
 207                         aic: interrupt-controller@3800 {
 208                                 compatible = "snps,dw-apb-ictl";
 209                                 reg = <0x3800 0x30>;
 210                                 interrupt-controller;
 211                                 #interrupt-cells = <1>;
 212                                 interrupt-parent = <&gic>;
 213                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 214                         };
 215                 };
 216
 217                 soc_pinctrl: pin-controller@ea8000 {
 218                         compatible = "marvell,berlin4ct-soc-pinctrl";
 219                         reg = <0xea8000 0x14>;
 220                 };
 221
 222                 avio_pinctrl: pin-controller@ea8400 {
 223                         compatible = "marvell,berlin4ct-avio-pinctrl";
 224                         reg = <0xea8400 0x8>;
 225                 };
 226
 227                 apb@fc0000 {
 228                         compatible = "simple-bus";
 229                         #address-cells = <1>;
 230                         #size-cells = <1>;
 231                         ranges = <0 0xfc0000 0x10000>;
 232                         interrupt-parent = <&sic>;
 233
 234                         sic: interrupt-controller@1000 {
 235                                 compatible = "snps,dw-apb-ictl";
 236                                 reg = <0x1000 0x30>;
 237                                 interrupt-controller;
 238                                 #interrupt-cells = <1>;
 239                                 interrupt-parent = <&gic>;
 240                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 241                         };
 242
 243                         wdt0: watchdog@3000 {
 244                                 compatible = "snps,dw-wdt";
 245                                 reg = <0x3000 0x100>;
 246                                 clocks = <&osc>;
 247                                 interrupts = <0>;
 248                         };
 249
 250                         wdt1: watchdog@4000 {
 251                                 compatible = "snps,dw-wdt";
 252                                 reg = <0x4000 0x100>;
 253                                 clocks = <&osc>;
 254                                 interrupts = <1>;
 255                         };
 256
 257                         wdt2: watchdog@5000 {
 258                                 compatible = "snps,dw-wdt";
 259                                 reg = <0x5000 0x100>;
 260                                 clocks = <&osc>;
 261                                 interrupts = <2>;
 262                         };
 263
 264                         sm_gpio0: gpio@8000 {
 265                                 compatible = "snps,dw-apb-gpio";
 266                                 reg = <0x8000 0x400>;
 267                                 #address-cells = <1>;
 268                                 #size-cells = <0>;
 269
 270                                 porte: gpio-port@4 {
 271                                         compatible = "snps,dw-apb-gpio-port";
 272                                         gpio-controller;
 273                                         #gpio-cells = <2>;
 274                                         ngpios = <32>;
 275                                         reg = <0>;
 276                                 };
 277                         };
 278
 279                         sm_gpio1: gpio@9000 {
 280                                 compatible = "snps,dw-apb-gpio";
 281                                 reg = <0x9000 0x400>;
 282                                 #address-cells = <1>;
 283                                 #size-cells = <0>;
 284
 285                                 portf: gpio-port@5 {
 286                                         compatible = "snps,dw-apb-gpio-port";
 287                                         gpio-controller;
 288                                         #gpio-cells = <2>;
 289                                         ngpios = <32>;
 290                                         reg = <0>;
 291                                 };
 292                         };
 293
 294                         uart0: serial@d000 {
 295                                 compatible = "snps,dw-apb-uart";
 296                                 reg = <0xd000 0x100>;
 297                                 interrupts = <8>;
 298                                 clocks = <&osc>;
 299                                 reg-shift = <2>;
 300                                 status = "disabled";
 301                                 pinctrl-0 = <&uart0_pmux>;
 302                                 pinctrl-names = "default";
 303                         };
 304                 };
 305
 306                 system_pinctrl: pin-controller@fe2200 {
 307                         compatible = "marvell,berlin4ct-system-pinctrl";
 308                         reg = <0xfe2200 0xc>;
 309
 310                         uart0_pmux: uart0-pmux {
 311                                 groups = "SM_URT0_TXD", "SM_URT0_RXD";
 312                                 function = "uart0";
 313                         };
 314                 };
 315         };
 316 };