1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 compatible = "arm,cortex-a35";
20 enable-method = "psci";
25 compatible = "arm,cortex-a35-pmu";
26 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
27 interrupt-affinity = <&cpu0>;
28 interrupt-parent = <&intc>;
32 compatible = "arm,smc-wdt";
33 arm,smc-id = <0xb200005a>;
38 ck_flexgen_08: ck-flexgen-08 {
40 compatible = "fixed-clock";
41 clock-frequency = <100000000>;
44 ck_flexgen_51: ck-flexgen-51 {
46 compatible = "fixed-clock";
47 clock-frequency = <200000000>;
50 ck_icn_ls_mcu: ck-icn-ls-mcu {
52 compatible = "fixed-clock";
53 clock-frequency = <200000000>;
59 compatible = "linaro,optee-tz";
64 compatible = "linaro,scmi-optee";
67 linaro,optee-channel-id = <0>;
69 scmi_clk: protocol@14 {
74 scmi_reset: protocol@16 {
81 intc: interrupt-controller@4ac00000 {
82 compatible = "arm,cortex-a7-gic";
83 #interrupt-cells = <3>;
86 reg = <0x0 0x4ac10000 0x0 0x1000>,
87 <0x0 0x4ac20000 0x0 0x2000>,
88 <0x0 0x4ac40000 0x0 0x2000>,
89 <0x0 0x4ac60000 0x0 0x2000>;
93 compatible = "arm,psci-1.0";
98 compatible = "arm,armv8-timer";
99 interrupt-parent = <&intc>;
100 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
101 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
102 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
103 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
108 compatible = "simple-bus";
109 #address-cells = <1>;
111 interrupt-parent = <&intc>;
112 ranges = <0x0 0x0 0x0 0x80000000>;
114 rifsc: rifsc-bus@42080000 {
115 compatible = "simple-bus";
116 reg = <0x42080000 0x1000>;
117 #address-cells = <1>;
121 usart2: serial@400e0000 {
122 compatible = "st,stm32h7-uart";
123 reg = <0x400e0000 0x400>;
124 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
125 clocks = <&ck_flexgen_08>;
129 sdmmc1: mmc@48220000 {
130 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell";
131 arm,primecell-periphid = <0x00353180>;
132 reg = <0x48220000 0x400>, <0x44230400 0x8>;
133 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&ck_flexgen_51>;
135 clock-names = "apb_pclk";
138 max-frequency = <120000000>;
143 syscfg: syscon@44230000 {
144 compatible = "st,stm32mp25-syscfg", "syscon";
145 reg = <0x44230000 0x10000>;
148 pinctrl: pinctrl@44240000 {
149 #address-cells = <1>;
151 compatible = "st,stm32mp257-pinctrl";
152 ranges = <0 0x44240000 0xa0400>;
155 gpioa: gpio@44240000 {
158 interrupt-controller;
159 #interrupt-cells = <2>;
161 clocks = <&ck_icn_ls_mcu>;
162 st,bank-name = "GPIOA";
166 gpiob: gpio@44250000 {
169 interrupt-controller;
170 #interrupt-cells = <2>;
171 reg = <0x10000 0x400>;
172 clocks = <&ck_icn_ls_mcu>;
173 st,bank-name = "GPIOB";
177 gpioc: gpio@44260000 {
180 interrupt-controller;
181 #interrupt-cells = <2>;
182 reg = <0x20000 0x400>;
183 clocks = <&ck_icn_ls_mcu>;
184 st,bank-name = "GPIOC";
188 gpiod: gpio@44270000 {
191 interrupt-controller;
192 #interrupt-cells = <2>;
193 reg = <0x30000 0x400>;
194 clocks = <&ck_icn_ls_mcu>;
195 st,bank-name = "GPIOD";
199 gpioe: gpio@44280000 {
202 interrupt-controller;
203 #interrupt-cells = <2>;
204 reg = <0x40000 0x400>;
205 clocks = <&ck_icn_ls_mcu>;
206 st,bank-name = "GPIOE";
210 gpiof: gpio@44290000 {
213 interrupt-controller;
214 #interrupt-cells = <2>;
215 reg = <0x50000 0x400>;
216 clocks = <&ck_icn_ls_mcu>;
217 st,bank-name = "GPIOF";
221 gpiog: gpio@442a0000 {
224 interrupt-controller;
225 #interrupt-cells = <2>;
226 reg = <0x60000 0x400>;
227 clocks = <&ck_icn_ls_mcu>;
228 st,bank-name = "GPIOG";
232 gpioh: gpio@442b0000 {
235 interrupt-controller;
236 #interrupt-cells = <2>;
237 reg = <0x70000 0x400>;
238 clocks = <&ck_icn_ls_mcu>;
239 st,bank-name = "GPIOH";
243 gpioi: gpio@442c0000 {
246 interrupt-controller;
247 #interrupt-cells = <2>;
248 reg = <0x80000 0x400>;
249 clocks = <&ck_icn_ls_mcu>;
250 st,bank-name = "GPIOI";
254 gpioj: gpio@442d0000 {
257 interrupt-controller;
258 #interrupt-cells = <2>;
259 reg = <0x90000 0x400>;
260 clocks = <&ck_icn_ls_mcu>;
261 st,bank-name = "GPIOJ";
265 gpiok: gpio@442e0000 {
268 interrupt-controller;
269 #interrupt-cells = <2>;
270 reg = <0xa0000 0x400>;
271 clocks = <&ck_icn_ls_mcu>;
272 st,bank-name = "GPIOK";
277 pinctrl_z: pinctrl@46200000 {
278 #address-cells = <1>;
280 compatible = "st,stm32mp257-z-pinctrl";
281 ranges = <0 0x46200000 0x400>;
284 gpioz: gpio@46200000 {
287 interrupt-controller;
288 #interrupt-cells = <2>;
290 clocks = <&ck_icn_ls_mcu>;
291 st,bank-name = "GPIOZ";
292 st,bank-ioport = <11>;